[llvm] [Thumb] Replace AddLikeOrOp with or_disjoint (NFC) (PR #195573)

[via llvm-commits]

https://github.com/LumioseSil created https://github.com/llvm/llvm-project/pull/195573

AddLikeOrOp is redundant now that we have or_disjoint.

>From 8739079db5774db5bc908e90a68abc61daecbb1e Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sun, 3 May 2026 21:38:33 -0400
Subject: [PATCH] [Thumb] Replace AddLikeOrOp with or_disjoint (NFC)

AddLikeOrOp is redundant now that we have or_disjoint.
---
 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 19 +++----------------
 llvm/lib/Target/ARM/ARMInstrThumb.td    | 11 +++--------
 llvm/lib/Target/ARM/ARMInstrThumb2.td   |  6 +++---
 3 files changed, 9 insertions(+), 27 deletions(-)

diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 61b679d55fb47..10ee30c950378 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -60,15 +60,15 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
   ARMDAGToDAGISel() = delete;
 
   explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm, CodeGenOptLevel OptLevel)
-      : SelectionDAGISel(tm, OptLevel) {}
+      : SelectionDAGISel(tm, OptLevel), Subtarget(nullptr) {}
 
   bool runOnMachineFunction(MachineFunction &MF) override {
     // Reset the subtarget each time through.
     Subtarget = &MF.getSubtarget<ARMSubtarget>();
-    SelectionDAGISel::runOnMachineFunction(MF);
-    return true;
+    return SelectionDAGISel::runOnMachineFunction(MF);
   }
 
+  void Select(SDNode *N) override;
   void PreprocessISelDAG() override;
 
   /// getI32Imm - Return a target constant of type i32 with the specified
@@ -77,8 +77,6 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
     return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
   }
 
-  void Select(SDNode *N) override;
-
   /// Return true as some complex patterns, like those that call
   /// canExtractShiftFromMul can modify the DAG inplace.
   bool ComplexPatternFuncMutatesDAG() const override { return true; }
@@ -106,8 +104,6 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
     return SelectImmShifterOperand(N, A, B, false);
   }
 
-  bool SelectAddLikeOr(SDNode *Parent, SDValue N, SDValue &Out);
-
   bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
   bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
 
@@ -653,15 +649,6 @@ bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N,
   return true;
 }
 
-// Determine whether an ISD::OR's operands are suitable to turn the operation
-// into an addition, which often has more compact encodings.
-bool ARMDAGToDAGISel::SelectAddLikeOr(SDNode *Parent, SDValue N, SDValue &Out) {
-  assert(Parent->getOpcode() == ISD::OR && "unexpected parent");
-  Out = N;
-  return CurDAG->haveNoCommonBitsSet(N, Parent->getOperand(1));
-}
-
-
 bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
                                           SDValue &Base,
                                           SDValue &OffImm) {
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td
index 1e2e3c30a78f7..20bbc7e727398 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -286,11 +286,6 @@ def t_addrmode_sp : MemOperand,
   let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
 }
 
-// Inspects parent to determine whether an or instruction can be implemented as
-// an add (i.e. whether we know overflow won't occur in the add).
-let WantsParent = true in
-def AddLikeOrOp : ComplexPattern<i32, 1, "SelectAddLikeOr">;
-
 // Pattern to exclude immediates from matching
 def non_imm32 : PatLeaf<(i32 GPR), [{ return !isa<ConstantSDNode>(N); }]>;
 
@@ -1062,11 +1057,11 @@ let isAdd = 1, hasSideEffects = 0 in {
 
 // Thumb has more flexible short encodings for ADD than ORR, so use those where
 // possible.
-def : T1Pat<(or AddLikeOrOp:$Rn, imm0_7:$imm), (tADDi3 $Rn, imm0_7:$imm)>;
+def : T1Pat<(or_disjoint tGPR:$Rn, imm0_7:$imm), (tADDi3 $Rn, imm0_7:$imm)>;
 
-def : T1Pat<(or AddLikeOrOp:$Rn, imm8_255:$imm), (tADDi8 $Rn, imm8_255:$imm)>;
+def : T1Pat<(or_disjoint tGPR:$Rn, imm8_255:$imm), (tADDi8 $Rn, imm8_255:$imm)>;
 
-def : T1Pat<(or AddLikeOrOp:$Rn, tGPR:$Rm), (tADDrr $Rn, $Rm)>;
+def : T1Pat<(or_disjoint tGPR:$Rn, tGPR:$Rm), (tADDrr $Rn, $Rm)>;
 
 
 def : tInstAlias <"add${s}${p} $Rdn, $Rm",
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td
index e79adb370798e..1276d5b78f12d 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -3040,13 +3040,13 @@ def : T2Pat<(t2_so_imm_not:$src),
 // There are shorter Thumb encodings for ADD than ORR, so to increase
 // Thumb2SizeReduction's chances later on we select a t2ADD for an or where
 // possible.
-def : T2Pat<(or AddLikeOrOp:$Rn, t2_so_imm:$imm),
+def : T2Pat<(or_disjoint rGPR:$Rn, t2_so_imm:$imm),
             (t2ADDri rGPR:$Rn, t2_so_imm:$imm)>;
 
-def : T2Pat<(or AddLikeOrOp:$Rn, imm0_4095:$Rm),
+def : T2Pat<(or_disjoint rGPR:$Rn, imm0_4095:$Rm),
             (t2ADDri12 rGPR:$Rn, imm0_4095:$Rm)>;
 
-def : T2Pat<(or AddLikeOrOp:$Rn, non_imm32:$Rm),
+def : T2Pat<(or_disjoint rGPR:$Rn, non_imm32:$Rm),
             (t2ADDrr $Rn, $Rm)>;
 
 //===----------------------------------------------------------------------===//