[llvm] [Docs] Match body/toctree ordering on Reference and UserGuides (PR #195542)
Anshul Nigham via llvm-commits
llvm-commits at lists.llvm.org
Sun May 3 12:38:35 PDT 2026
https://github.com/nigham created https://github.com/llvm/llvm-project/pull/195542
The `toctree` section is hidden but used for previous/next breadcrumbs.
This was suggested in https://github.com/llvm/llvm-project/pull/184440#issuecomment-4351195402
>From 6e72277fda6b387fad0d86e4df7c1de0d6d280af Mon Sep 17 00:00:00 2001
From: Anshul Nigham <nigham at google.com>
Date: Mon, 27 Apr 2026 21:21:07 -0700
Subject: [PATCH 1/3] [Docs] Fixes indents for InstrRefDebugInfo and
KeyInstructionsDebugInfo
---
llvm/docs/InstrRefDebugInfo.md | 14 +++++++-------
llvm/docs/KeyInstructionsDebugInfo.md | 22 +++++++++++-----------
2 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/llvm/docs/InstrRefDebugInfo.md b/llvm/docs/InstrRefDebugInfo.md
index eb7a0464b90a0..e0a85f99cb4f3 100644
--- a/llvm/docs/InstrRefDebugInfo.md
+++ b/llvm/docs/InstrRefDebugInfo.md
@@ -6,7 +6,7 @@ generation stage of compilation. This content is aimed at those working on code
generation targets and optimisation passes. It may also be of interest to anyone
curious about low-level debug info handling.
-# Problem statement
+## Problem statement
At the end of compilation, LLVM must produce a DWARF location list (or similar)
describing what register or stack location a variable can be found in, for each
@@ -15,7 +15,7 @@ register that the variable resides in through compilation, however this is
vulnerable to register optimisations during regalloc, and instruction
movements.
-# Solution: instruction referencing
+## Solution: instruction referencing
Rather than identify the virtual register that a variable value resides in,
instead in instruction referencing mode, LLVM refers to the machine instruction
@@ -61,7 +61,7 @@ location is safely dropped and marked "optimised out". The exception is
instructions that are mutated rather than replaced, which always need debug info
maintenance.
-# Register allocator considerations
+## Register allocator considerations
When the register allocator runs, debugging instructions do not directly refer
to any virtual registers, and thus there is no need for expensive location
@@ -91,7 +91,7 @@ bb.2:
DBG_PHI $rax, 1
```
-# `LiveDebugValues`
+## `LiveDebugValues`
After optimisations and code layout complete, information about variable
values must be translated into variable locations, i.e. registers and stack
@@ -111,7 +111,7 @@ Key to this process is being able to identify the movement of values between
registers and stack locations, so that the location of values can be preserved
for the full time that they are resident in the machine.
-# Required target support and transition guide
+## Required target support and transition guide
Instruction referencing will work on any target, but likely with poor coverage.
Supporting instruction referencing well requires:
@@ -120,7 +120,7 @@ Supporting instruction referencing well requires:
* Target-specific optimisations to be instrumented, to preserve instruction
numbers.
-## Target hooks
+### Target hooks
`TargetInstrInfo::isCopyInstrImpl` must be implemented to recognise any
instructions that are copy-like -- `LiveDebugValues` uses this to identify when
@@ -134,7 +134,7 @@ the stack slot. In addition, any instruction that writes to a stack spill
should have a `MachineMemoryOperand` attached, so that `LiveDebugValues` can
recognise that a slot has been clobbered.
-## Target-specific optimisation instrumentation
+### Target-specific optimisation instrumentation
Optimisations come in two flavours: those that mutate a `MachineInstr` to make
it do something different, and those that create a new instruction to replace
diff --git a/llvm/docs/KeyInstructionsDebugInfo.md b/llvm/docs/KeyInstructionsDebugInfo.md
index d93151a236680..22f83f2b0a381 100644
--- a/llvm/docs/KeyInstructionsDebugInfo.md
+++ b/llvm/docs/KeyInstructionsDebugInfo.md
@@ -14,9 +14,9 @@ This is a DWARF-based feature. There is currently no plan to support CodeView.
Set LLVM flag `-dwarf-use-key-instructions` to `false` to ignore Key Instructions metadata when emitting DWARF.
-# LLVM
+## LLVM
-## Problem statement
+### Problem statement
A lot of the noise in stepping comes from code motion and instruction scheduling. Consider a long expression on a single line. It may involve multiple operations that optimisations move, re-order, and interleave with other instructions that have different line numbers.
@@ -24,7 +24,7 @@ DWARF provides a helpful tool the compiler can employ to mitigate this jumpiness
(Note: It's up to the debugger if it wants to interpret `is_stmt` or not, and at time of writing LLDB doesn't; possibly because until now LLVM's `is_stmt`s convey no information that can't already be deduced from the rest of the line table.)
-## Solution overview
+### Solution overview
Taking ideas from two papers [1][2] that explore the issue, especially C. Tice's:
@@ -36,7 +36,7 @@ From the perspective of a source-level debugger user:
* Communicating where the key instructions are to the debugger (using DWARF’s is_stmt) avoids jumpiness introduced by scheduling non-key instructions without losing source attribution (because non-key instructions retain an associated source location, they’re just ignored for stepping).
-## Solution implementation
+### Solution implementation
1. `DILocation` has 2 new fields, `atomGroup` and `atomRank`. `DISubprogram` has a new field `keyInstructions`.
2. Clang creates `DILocations` using the new fields to communicate which instructions are "interesting", and sets `keyInstructions` true in `DISubprogram`s to tell LLVM to interpret the new metadata in those functions.
@@ -55,9 +55,9 @@ The `DILocations` carry over from IR to MIR as normal, without any changes.
4. *DWARF emission* - Iterate over all instructions in a function. For each `(atomGroup, inlinedAt)` pair we find the set of instructions sharing the lowest rank. Only the last of these instructions in each basic block is included in the set. The instructions in this set get `is_stmt` applied to their source locations. That `is_stmt` then "floats" to the top of contiguous sequence of instructions with the same line number in the same basic block. That has two benefits when optimisations are enabled. First, this floats `is_stmt` to the top of epilogue instructions (rather than applying it to the `ret` instruction itself) which is important to avoid losing variable location coverage at return statements. Second, it reduces the difference in optimized code stepping behaviour between when Key Instructions is enabled and disabled in “uninteresting” cases. I.e., it appears to generally reduce unnecessary changes in stepping.\
We’ve used contiguous line numbers rather than atom membership as the test there because of our choice to represent source atoms with a single integer ID. We can’t have instructions belonging to multiple atom groups or represent any kind of grouping hierarchy. That means we can’t rely on all the call setup instructions being in the same group currently (e.g., if one of the argument expressions contains key functionality such as a store, it will be in its own group).
-## Limitations
+### Limitations
-### Lack of multiple atom membership
+#### Lack of multiple atom membership
Using a number to represent atom membership is limiting; currently an instruction that belongs to multiple source atoms cannot belong to multiple atom groups. This does occur in practice, both in the front end and during optimisations. Consider this C code:
```c
@@ -73,7 +73,7 @@ The load of `c` is used by both stores (which are the Key Instructions for each
Certain optimisations merge source locations, which presents another case where it might make sense to be able to represent an instruction belonging to multiple atoms. Currently we deterministically pick one (choosing to keep the lower rank one if there is one).
-### Disabled at O0
+#### Disabled at O0
Consider the following code without optimisations:
```c
@@ -101,11 +101,11 @@ Without multiple-atom-membership or some kind of atom hierarchy it's not apparen
O0 isn't a key use-case so solving this is not a priority for the initial implementation. The trade off, smoother stepping at the cost of not being able to edit variables to affect an expression in some cases (and at particular stop points), becomes more attractive when optimisations are enabled (we find that editing variables in the debugger in optimized code often produces unexpected effects, so it's not a big concern that Key Instructions makes it harder sometimes).
-# Clang and other front ends
+## Clang and other front ends
Tell Clang [not] to produce Key Instructions metadata with `-g[no-]key-instructions`.
-## Implementation
+### Implementation
Clang needs to annotate key instructions with the new metadata. Variable assignments (stores, memory intrinsics), control flow (branches and their conditions, some unconditional branches), and exception handling instructions are annotated. Calls are ignored as they're unconditionally marked `is_stmt`. This is achieved with a few simple constructs:
@@ -117,7 +117,7 @@ Class `ApplyAtomGroup` - This is a scoped helper similar to `ApplyDebugLocation`
`CodeGenFunction::addInstToSpecificSourceAtom(llvm::Instruction *KeyInstruction, llvm::Value *Backup, uint64_t Atom)` adds the instruction (and backup instruction if non-null) to the specific group `Atom`. This is currently only used for `rets` which is explored in the examples below. Special handling is needed due to the fact that an existing atom group needs to be reused in some circumstances, so neither of the other helper functions are appropriate.
-## Examples
+### Examples
A simple example walk through:
```c
@@ -147,7 +147,7 @@ The implicit return is also key (`atomGroup` 2) so that it's stepped on, to matc
Explicit return statements are handled uniquely. Rather than emit a `ret` for each `return` Clang, in all but the simplest cases (as in the first example) emits a branch to a dedicated block with a single `ret`. That branch is the key instruction for the return statement. If there's only one branch to that block, because there's only one `return` (as in this example), Clang folds the block into its only predecessor. Handily `EmitReturnBlock` returns the `DebugLoc` associated with the single branch in that case, which is fed into `addInstToSpecificSourceAtom` to ensure the `ret` gets the right group.
-## Supporting Key Instructions from another front end
+### Supporting Key Instructions from another front end
Front ends that want to use the feature need to group and rank instructions according to their source atoms and interingness by attaching `DILocations` with the necessary `atomGroup` and `atomRank` values. They also need to set the `keyInstructions` field to `true` in `DISubprogram`s to tell LLVM to interpret the new metadata in those functions.
>From 4f7a696a26c59bacc12f7e54bcd6aa90202888a6 Mon Sep 17 00:00:00 2001
From: Anshul Nigham <nigham at google.com>
Date: Tue, 28 Apr 2026 22:11:41 -0700
Subject: [PATCH 2/3] [Docs] Normalize ReleaseNotes headers and indents
---
llvm/docs/ReleaseNotes.md | 123 ++++++++++-------------------
llvm/docs/ReleaseNotesTemplate.txt | 108 +++++++++----------------
2 files changed, 79 insertions(+), 152 deletions(-)
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 7ee15d42b6837..ccc6c6ee6c145 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -4,8 +4,7 @@ MyST (https://myst-parser.readthedocs.io/en/latest/). -->
<!-- If you want to modify sections/contents permanently, you should modify both
ReleaseNotes.md and ReleaseNotesTemplate.txt. -->
-LLVM {{env.config.release}} Release Notes
-=========================================
+# LLVM {{env.config.release}} Release Notes
```{contents}
```
@@ -17,8 +16,7 @@ LLVM {{env.config.release}} Release Notes
```
````
-Introduction
-============
+## Introduction
This document contains the release notes for the LLVM Compiler Infrastructure,
release {{env.config.release}}. Here we describe the status of LLVM, including
@@ -36,8 +34,7 @@ LLVM web page, this document applies to the *next* release, not the current
one. To see the release notes for a specific release, please see the
[releases page](https://llvm.org/releases/).
-Non-comprehensive list of changes in this release
-=================================================
+## Non-comprehensive list of changes in this release
<!-- For small 1-3 sentence descriptions, just add an entry at the end of
this list. If your description won't fit comfortably in one bullet
@@ -50,14 +47,12 @@ for adding a new subsection. -->
<!-- If you would like to document a larger change, then you can add a
subsection about it right here. You can copy the following boilerplate:
-Special New Feature
--------------------
+### Special New Feature
Makes programs 10x faster by doing Special New Thing.
-->
-Changes to the LLVM IR
-----------------------
+### Changes to the LLVM IR
* Removed `llvm.convert.to.fp16` and `llvm.convert.from.fp16`
intrinsics. These are equivalent to `fptrunc` and `fpext` with half
@@ -78,8 +73,7 @@ Changes to the LLVM IR
* Special values for infinities and NaNs, including NaN payloads, are added.
-Changes to LLVM infrastructure
-------------------------------
+### Changes to LLVM infrastructure
* Removed ``Constant::isZeroValue``. It was functionally identical to
``Constant::isNullValue`` for all types except floating-point negative
@@ -110,23 +104,18 @@ Changes to LLVM infrastructure
this may fail if symlink permissions are not available.
* Added ``readlink``, which reads the target of a symbolic link.
-Changes to building LLVM
-------------------------
+### Changes to building LLVM
-Changes to TableGen
--------------------
+### Changes to TableGen
* Outer let statements use ``ID{n-m}`` instead of ``ID<n-m>`` to be consistent
with inner let statements.
-Changes to Interprocedural Optimizations
-----------------------------------------
+### Changes to Interprocedural Optimizations
-Changes to Vectorizers
-----------------------
+### Changes to Vectorizers
-Changes to the AArch64 Backend
-------------------------------
+### Changes to the AArch64 Backend
* The `sysp`, `mrrs`, and `msrr` instructions are now accepted without
requiring the `+d128` feature gating.
@@ -136,8 +125,7 @@ Changes to the AArch64 Backend
toolchains that do not define the `R_AARCH64_TLS_DTPREL64` static relocation
type for TLS offsets.
-Changes to the AMDGPU Backend
------------------------------
+### Changes to the AMDGPU Backend
* Initial support for gfx1310
* The `"amdgpu-num-sgpr"` and `"amdgpu-num-vgpr"` IR function attributes
@@ -146,43 +134,34 @@ Changes to the AMDGPU Backend
honors the attributes; Clang emits a `-Wdeprecated-declarations` warning when
the source attributes are used.
-Changes to the ARM Backend
---------------------------
+### Changes to the ARM Backend
* The `r14` register can now be used as an alias for the link register `lr`
in inline assembly. Clang always canonicalizes the name to `lr`, but other
frontends may not.
-Changes to the AVR Backend
---------------------------
+### Changes to the AVR Backend
-Changes to the DirectX Backend
-------------------------------
+### Changes to the DirectX Backend
-Changes to the Hexagon Backend
-------------------------------
+### Changes to the Hexagon Backend
-Changes to the LoongArch Backend
---------------------------------
+### Changes to the LoongArch Backend
* DWARF fission is now compatible with linker relaxations, allowing `-gsplit-dwarf` and `-mrelax`
to be used together when building for the LoongArch platform.
-Changes to the MIPS Backend
----------------------------
+### Changes to the MIPS Backend
-Changes to the NVPTX Backend
-----------------------------
+### Changes to the NVPTX Backend
* The default SM version has been changed from `sm_30` to `sm_75`. `sm_75` is
the oldest GPU variant compatible with the widest range of recent major CUDA
Toolkit versions (11/12/13).
-Changes to the PowerPC Backend
-------------------------------
+### Changes to the PowerPC Backend
-Changes to the RISC-V Backend
------------------------------
+### Changes to the RISC-V Backend
* `llvm-objdump` now has support for `--symbolize-operands` with RISC-V.
* `-mcpu=spacemit-x100` was added.
@@ -202,30 +181,24 @@ Changes to the RISC-V Backend
* `-mcpu=sifive-x160` and `-mcpu=sifive-x180` were added.
* Support for the experimental `XRivosVisni` vendor extension has been removed.
-Changes to the WebAssembly Backend
-----------------------------------
+### Changes to the WebAssembly Backend
-Changes to the Windows Target
------------------------------
+### Changes to the Windows Target
* The `.seh_startchained` and `.seh_endchained` assembly instructions have been removed and replaced
with a new `.seh_splitchained` instruction.
-Changes to the X86 Backend
---------------------------
+### Changes to the X86 Backend
* `.att_syntax` directive is now emitted for assembly files when AT&T syntax is
in use. This matches the behaviour of Intel syntax and aids with
compatibility when changing the default Clang syntax to the Intel syntax.
-Changes to the OCaml bindings
------------------------------
+### Changes to the OCaml bindings
-Changes to the Python bindings
-------------------------------
+### Changes to the Python bindings
-Changes to the C API
---------------------
+### Changes to the C API
* Replaced opcode ``LLVMBr`` with ``LLVMUncondBr`` and ``LLVMCondBr``.
@@ -233,17 +206,13 @@ Changes to the C API
successor order. This can cause subtle breakage when using ``LLVMGetOperand``
or ``LLVMSetOperand`` to access successors.
-Changes to the CodeGen infrastructure
--------------------------------------
+### Changes to the CodeGen infrastructure
-Changes to the Metadata Info
-----------------------------
+### Changes to the Metadata Info
-Changes to the Debug Info
--------------------------
+### Changes to the Debug Info
-Changes to the LLVM tools
--------------------------
+### Changes to the LLVM tools
* `llvm-profgen` now supports ETM trace decoding using the OpenCSD library for Cortex-M targets.
@@ -253,27 +222,26 @@ Changes to the LLVM tools
* Add `-mtune` option to `llc`.
* Add `-mtune` option to `opt`.
-Changes to LLDB
----------------
+### Changes to LLDB
* A new ``webinspector-wasm`` platform was added to list and attach to WebAssembly processes in Safari.
* The default for `load-script-from-symbol-file` was changed from `warn` to `trusted`. This means that scripts from
code signed dSYM bundles are now loaded automatically, while untrusted bundles continue to produce a warning.
-### Deprecated APIs
+#### Deprecated APIs
* ``SBTarget::GetDataByteSize()``, ``SBTarget::GetCodeByteSize()``, and ``SBSection::GetTargetByteSize()``
have been deprecated. They always return `1`, as before.
-### FreeBSD
+#### FreeBSD
-#### Userspace Debugging
+##### Userspace Debugging
* Support for MIPS64 has been removed.
* The minimum assumed FreeBSD version is now 14. The effect of which is that watchpoints are
assumed to be supported.
-#### Kernel Debugging
+##### Kernel Debugging
* The plugin that analyzes FreeBSD kernel core dump and live core has been renamed from `freebsd-kernel` to
`freebsd-kernel-core`. Remote kernel debugging is still handled by the `gdb-remote` plugin.
@@ -292,7 +260,7 @@ Changes to LLDB
so users can resync live kernel thread state without restarting LLDB. Note that this has no impact on full dump
and minidump files.
-### Linux
+#### Linux
* On Arm Linux, the `tpidruro` register can now be read. Writing to this register is not supported.
* Thread local variables are now supported on Arm and RISC-V Linux if the program being debugged is using glibc.
@@ -311,26 +279,21 @@ Changes to LLDB
See the [LLDB on AArch64 Linux](https://lldb.llvm.org/use/aarch64-linux.html#permission-overlay-extension-poe)
guide for more information.
-### Windows
+#### Windows
* Python 3.11 or later is now recommended for building LLDB 23 on Windows. From LLDB 24, Python 3.11 or later will be required.
-Changes to BOLT
----------------
+### Changes to BOLT
-Changes to Sanitizers
----------------------
+### Changes to Sanitizers
* Add a random delay into ThreadSanitizer to help find rare thread interleavings.
-Other Changes
--------------
+### Other Changes
-External Open Source Projects Using LLVM {{env.config.release}}
-===============================================================
+## External Open Source Projects Using LLVM {{env.config.release}}
-Additional Information
-======================
+## Additional Information
A wide variety of additional information is available on the
[LLVM web page](https://llvm.org/), in particular in the
diff --git a/llvm/docs/ReleaseNotesTemplate.txt b/llvm/docs/ReleaseNotesTemplate.txt
index ea1e4906fbe2e..d0c4c1edbf5af 100644
--- a/llvm/docs/ReleaseNotesTemplate.txt
+++ b/llvm/docs/ReleaseNotesTemplate.txt
@@ -4,8 +4,7 @@ MyST (https://myst-parser.readthedocs.io/en/latest/). -->
<!-- If you want to modify sections/contents permanently, you should modify both
ReleaseNotes.md and ReleaseNotesTemplate.txt. -->
-LLVM {{env.config.release}} Release Notes
-=========================================
+# LLVM {{env.config.release}} Release Notes
```{contents}
```
@@ -17,8 +16,7 @@ LLVM {{env.config.release}} Release Notes
```
````
-Introduction
-============
+## Introduction
This document contains the release notes for the LLVM Compiler Infrastructure,
release {{env.config.release}}. Here we describe the status of LLVM, including
@@ -36,8 +34,7 @@ LLVM web page, this document applies to the *next* release, not the current
one. To see the release notes for a specific release, please see the
[releases page](https://llvm.org/releases/).
-Non-comprehensive list of changes in this release
-=================================================
+## Non-comprehensive list of changes in this release
<!-- For small 1-3 sentence descriptions, just add an entry at the end of
this list. If your description won't fit comfortably in one bullet
@@ -50,107 +47,74 @@ for adding a new subsection. -->
<!-- If you would like to document a larger change, then you can add a
subsection about it right here. You can copy the following boilerplate:
-Special New Feature
--------------------
+### Special New Feature
Makes programs 10x faster by doing Special New Thing.
-->
-Changes to the LLVM IR
-----------------------
+### Changes to the LLVM IR
-Changes to LLVM infrastructure
-------------------------------
+### Changes to LLVM infrastructure
-Changes to building LLVM
-------------------------
+### Changes to building LLVM
-Changes to TableGen
--------------------
+### Changes to TableGen
-Changes to Interprocedural Optimizations
-----------------------------------------
+### Changes to Interprocedural Optimizations
-Changes to Vectorizers
-----------------------
+### Changes to Vectorizers
-Changes to the AArch64 Backend
-------------------------------
+### Changes to the AArch64 Backend
-Changes to the AMDGPU Backend
------------------------------
+### Changes to the AMDGPU Backend
-Changes to the ARM Backend
---------------------------
+### Changes to the ARM Backend
-Changes to the AVR Backend
---------------------------
+### Changes to the AVR Backend
-Changes to the DirectX Backend
-------------------------------
+### Changes to the DirectX Backend
-Changes to the Hexagon Backend
-------------------------------
+### Changes to the Hexagon Backend
-Changes to the LoongArch Backend
---------------------------------
+### Changes to the LoongArch Backend
-Changes to the MIPS Backend
----------------------------
+### Changes to the MIPS Backend
-Changes to the PowerPC Backend
-------------------------------
+### Changes to the PowerPC Backend
-Changes to the RISC-V Backend
------------------------------
+### Changes to the RISC-V Backend
-Changes to the WebAssembly Backend
-----------------------------------
+### Changes to the WebAssembly Backend
-Changes to the Windows Target
------------------------------
+### Changes to the Windows Target
-Changes to the X86 Backend
---------------------------
+### Changes to the X86 Backend
-Changes to the OCaml bindings
------------------------------
+### Changes to the OCaml bindings
-Changes to the Python bindings
-------------------------------
+### Changes to the Python bindings
-Changes to the C API
---------------------
+### Changes to the C API
-Changes to the CodeGen infrastructure
--------------------------------------
+### Changes to the CodeGen infrastructure
-Changes to the Metadata Info
-----------------------------
+### Changes to the Metadata Info
-Changes to the Debug Info
--------------------------
+### Changes to the Debug Info
-Changes to the LLVM tools
--------------------------
+### Changes to the LLVM tools
-Changes to LLDB
----------------
+### Changes to LLDB
-Changes to BOLT
----------------
+### Changes to BOLT
-Changes to Sanitizers
----------------------
+### Changes to Sanitizers
-Other Changes
--------------
+### Other Changes
-External Open Source Projects Using LLVM {{env.config.release}}
-===============================================================
+## External Open Source Projects Using LLVM {{env.config.release}}
-Additional Information
-======================
+## Additional Information
A wide variety of additional information is available on the
[LLVM web page](https://llvm.org/), in particular in the
>From 67f280da3044464610fe7db2bef2aaa4ebeb398a Mon Sep 17 00:00:00 2001
From: Anshul Nigham <nigham at google.com>
Date: Sun, 3 May 2026 12:34:23 -0700
Subject: [PATCH 3/3] [Docs] Match body/toctree ordering on Reference and
UserGuides
---
llvm/docs/Reference.rst | 82 ++++++++++++++--------------
llvm/docs/UserGuides.rst | 112 ++++++++++++++++++++-------------------
2 files changed, 99 insertions(+), 95 deletions(-)
diff --git a/llvm/docs/Reference.rst b/llvm/docs/Reference.rst
index cfbb98b578e76..56e367388b1a8 100644
--- a/llvm/docs/Reference.rst
+++ b/llvm/docs/Reference.rst
@@ -9,61 +9,63 @@ LLVM and API reference documentation.
.. toctree::
:hidden:
- AIToolPolicy
- Atomics
- BitCodeFormat
- BlockFrequencyTerminology
- BranchWeightMetadata
- CalleeTypeMetadata
- CallGraphSection
- CIBestPractices
+ HowToUseAttributes
CommandGuide/index
- ContentAddressableStorage
- ConvergenceAndUniformity
- ConvergentOperations
- Coroutines
- DependenceGraphs/index
- ExceptionHandling
- Extensions
- FaultMaps
- FuzzingLLVM
+ CommandGuide/llvm-reduce
+ OptBisect
+ SymbolizerMarkupFormat
+ PDB/index
GarbageCollection
- GetElementPtr
+ Statepoints
+ LibFuzzer
+ FuzzingLLVM
+ LangRef
+ UndefinedBehavior
+ InAlloca
+ BitCodeFormat
+ MIRLangRef
GlobalISel/index
+ ConvergentOperations
+ TestingGuide
+ TestSuiteGuide
GwpAsan
+ XRay
+ XRayExample
+ FaultMaps
+ Atomics
+ ExceptionHandling
+ Extensions
HowToSetUpLLVMStyleRTTI
- HowToUseAttributes
- InAlloca
- InterfaceExportAnnotations
- LangRef
- LibFuzzer
- MarkedUpDisassembly
- MIRLangRef
- OptBisect
- PCSectionsMetadata
- PDB/index
- PointerAuth
- MLGO
+ BlockFrequencyTerminology
+ BranchWeightMetadata
+ GetElementPtr
ScudoHardenedAllocator
MemoryModelRelaxationAnnotations
MemTagSanitizer
+ DependenceGraphs/index
+ SpeculativeLoadHardening
+ SegmentedStacks
+ MarkedUpDisassembly
+ StackMaps
+ Coroutines
+ PointerAuth
+ YamlIO
+ ConvergenceAndUniformity
+ MLGO
+ ContentAddressableStorage
+ CIBestPractices
+ AIToolPolicy
+ CalleeTypeMetadata
+ CallGraphSection
+ InterfaceExportAnnotations
+ PCSectionsMetadata
QualGroup
Security
SecurityTransparencyReports
- SegmentedStacks
- StackMaps
- SpeculativeLoadHardening
- Statepoints
- SymbolizerMarkupFormat
SystemLibrary
- TestingGuide
TransformMetadata
TypeMetadata
- UndefinedBehavior
- XRay
- XRayExample
XRayFDRFormat
- YamlIO
API Reference
-------------
diff --git a/llvm/docs/UserGuides.rst b/llvm/docs/UserGuides.rst
index f33ddcabc8d89..97c2431213546 100644
--- a/llvm/docs/UserGuides.rst
+++ b/llvm/docs/UserGuides.rst
@@ -12,78 +12,80 @@ intermediate LLVM representation.
.. toctree::
:hidden:
- AArch64SME
- AddingConstrainedIntrinsics
- AdminTasks
- AdvancedBuilds
- AliasAnalysis
- AMDGPUUsage
- AMDGPUAsyncOperations
- Benchmarking
- BigEndianNEON
- BuildingADistribution
+ HowToBuildOnARM
+ HowToBuildWithPGO
+ HowToCrossCompileLLVM
+ CoverageMappingFormat
CFIVerify
+ BuildingADistribution
CMake
- CMakePrimer
- CodeGenerator
- CodeOfConduct
- CommandLine
- CompileCudaWithLLVM
- CoverageMappingFormat
- CycleTerminology
- DebuggingJITedCode
- DirectXUsage
Docker
+ SupportLibrary
+ AdvancedBuilds
+ WritingAnLLVMNewPMPass
+ WritingAnLLVMPass
+ Passes
+ StackSafetyAnalysis
+ MergeFunctions
+ AliasAnalysis
+ MemorySSA
+ MemProf
+ LoopTerminology
+ CycleTerminology
+ Vectorizers
+ LinkTimeOptimization
DTLTO
- FatLTO
- ExtendingLLVM
- GitHub
GoldPlugin
- GlobalISel/MIRPatterns
- HowToBuildOnARM
- HowToBuildWithPGO
- HowToBuildWindowsItaniumPrograms
- HowToCrossCompileBuiltinsOnArm
- HowToCrossCompileLLVM
+ Remarks
+ SourceLevelDebugging
HowToUpdateDebugInfo
- InstCombineContributorGuide
- InstrProfileFormat
InstrRefDebugInfo
+ RemoveDIsDebugInfo
KeyInstructionsDebugInfo
- LFI
- LinkTimeOptimization
- LoopTerminology
- MarkdownQuickstartTemplate
- MemorySSA
- MemProf
- MergeFunctions
+ InstrProfileFormat
+ InstCombineContributorGuide
+ WritingAnLLVMBackend
+ CodeGenerator
+ TableGen/index
+ GlobalISel/MIRPatterns
MCJITDesignAndImplementation
- MisExpect
ORCv2
- OpaquePointers
JITLink
- NewPassManager
+ DebuggingJITedCode
+ CommandLine
+ ExtendingLLVM
+ AddingConstrainedIntrinsics
+ HowToBuildWindowsItaniumPrograms
+ HowToCrossCompileBuiltinsOnArm
+ BigEndianNEON
+ AArch64SME
+ CompileCudaWithLLVM
NVPTXUsage
- Passes
- ReportingGuide
- ResponseGuide
- Remarks
- RemoveDIsDebugInfo
+ AMDGPUUsage
+ AMDGPUAsyncOperations
+ AMDGPUDwarfExtensionsForHeterogeneousDebugging
+ AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack
+ SPIRVUsage
+ DirectXUsage
RISCVUsage
RISCV/RISCVVectorExtension
RISCV/RISCVVCIX
- SourceLevelDebugging
- SPIRVUsage
SandboxIR
- StackSafetyAnalysis
- SupportLibrary
- TableGen/index
- TableGenFundamentals
Telemetry
- Vectorizers
- WritingAnLLVMPass
- WritingAnLLVMNewPMPass
- WritingAnLLVMBackend
+ LFI
+ AdminTasks
+ Benchmarking
+ CMakePrimer
+ CodeOfConduct
+ FatLTO
+ GitHub
+ MarkdownQuickstartTemplate
+ MisExpect
+ OpaquePointers
+ NewPassManager
+ ReportingGuide
+ ResponseGuide
+ TableGenFundamentals
yaml2obj
Clang
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