[llvm] [SelectionDAG] Look through FREEZE in getCopyToRegs when checking isZExtFree (PR #195285)
Henry Jiang via llvm-commits
llvm-commits at lists.llvm.org
Sun May 3 09:56:22 PDT 2026
https://github.com/mustartt updated https://github.com/llvm/llvm-project/pull/195285
>From 4a635e2851ce0fa0345684c18f75276033ae99b9 Mon Sep 17 00:00:00 2001
From: Henry Jiang <henry_jiang2 at apple.com>
Date: Thu, 30 Apr 2026 22:24:57 -0700
Subject: [PATCH] Lowering CopyToReg for freeze(load) lowers to zero_extend
instead of any_extend
---
.../SelectionDAG/SelectionDAGBuilder.cpp | 9 +-
.../AArch64/freeze-load-zext-copytoreg.ll | 148 ++++++++++++++++
.../PowerPC/freeze-load-zext-copytoreg.ll | 162 ++++++++++++++++++
.../RISCV/freeze-load-zext-copytoreg.ll | 156 +++++++++++++++++
4 files changed, 473 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/freeze-load-zext-copytoreg.ll
create mode 100644 llvm/test/CodeGen/PowerPC/freeze-load-zext-copytoreg.ll
create mode 100644 llvm/test/CodeGen/RISCV/freeze-load-zext-copytoreg.ll
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 458fd21c5ab6d..71faad9329ddb 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -993,8 +993,13 @@ void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
*DAG.getContext(), *CallConv, RegVTs[Value])
: RegVTs[Value];
- if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
- ExtendKind = ISD::ZERO_EXTEND;
+ if (ExtendKind == ISD::ANY_EXTEND) {
+ SDValue PeeledVal = Val;
+ if (PeeledVal.getOpcode() == ISD::FREEZE)
+ PeeledVal = PeeledVal.getOperand(0);
+ if (TLI.isZExtFree(PeeledVal, RegisterVT))
+ ExtendKind = ISD::ZERO_EXTEND;
+ }
getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), &Parts[Part],
NumParts, RegisterVT, V, CallConv, ExtendKind);
diff --git a/llvm/test/CodeGen/AArch64/freeze-load-zext-copytoreg.ll b/llvm/test/CodeGen/AArch64/freeze-load-zext-copytoreg.ll
new file mode 100644
index 0000000000000..b2cdd7dc7d5b7
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/freeze-load-zext-copytoreg.ll
@@ -0,0 +1,148 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-apple-darwin < %s | FileCheck %s
+
+define i32 @freeze_i8_load_multi_bb(ptr %p, i64 %len) {
+; CHECK-LABEL: freeze_i8_load_multi_bb:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: mov x8, xzr
+; CHECK-NEXT: b LBB0_2
+; CHECK-NEXT: LBB0_1: ; %for.end
+; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
+; CHECK-NEXT: cmp x8, x1
+; CHECK-NEXT: add x8, x8, #1
+; CHECK-NEXT: b.eq LBB0_7
+; CHECK-NEXT: LBB0_2: ; %for.cond
+; CHECK-NEXT: ; =>This Loop Header: Depth=1
+; CHECK-NEXT: ; Child Loop BB0_3 Depth 2
+; CHECK-NEXT: cmp x8, x1
+; CHECK-NEXT: b.hs LBB0_8
+; CHECK-NEXT: LBB0_3: ; %for.body
+; CHECK-NEXT: ; Parent Loop BB0_2 Depth=1
+; CHECK-NEXT: ; => This Inner Loop Header: Depth=2
+; CHECK-NEXT: ldrb w9, [x0, x8]
+; CHECK-NEXT: cmp w9, #32
+; CHECK-NEXT: b.lo LBB0_1
+; CHECK-NEXT: ; %bb.4: ; %switch.test
+; CHECK-NEXT: ; in Loop: Header=BB0_3 Depth=2
+; CHECK-NEXT: cmp w9, #34
+; CHECK-NEXT: b.eq LBB0_1
+; CHECK-NEXT: ; %bb.5: ; %switch.test
+; CHECK-NEXT: ; in Loop: Header=BB0_3 Depth=2
+; CHECK-NEXT: cmp w9, #92
+; CHECK-NEXT: b.eq LBB0_1
+; CHECK-NEXT: ; %bb.6: ; %for.inc
+; CHECK-NEXT: ; in Loop: Header=BB0_3 Depth=2
+; CHECK-NEXT: add x9, x8, #1
+; CHECK-NEXT: cmp x9, x1
+; CHECK-NEXT: b.ne LBB0_3
+; CHECK-NEXT: LBB0_7:
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB0_8:
+; CHECK-NEXT: mov w0, #1 ; =0x1
+; CHECK-NEXT: ret
+ br label %for.cond
+
+for.cond:
+ %i = phi i64 [ 0, %0 ], [ %add, %for.end ]
+ %cmp = icmp ult i64 %i, %len
+ br i1 %cmp, label %for.body, label %ret1
+
+for.body:
+ %arrayidx = getelementptr inbounds i8, ptr %p, i64 %i
+ %load = load i8, ptr %arrayidx, align 1
+ %freeze = freeze i8 %load
+ %cmp.lo = icmp ugt i8 %freeze, 31
+ br i1 %cmp.lo, label %switch.test, label %for.end
+
+switch.test:
+ switch i8 %freeze, label %for.inc [
+ i8 92, label %for.end
+ i8 34, label %for.end
+ ]
+
+for.inc:
+ %inc = add nuw i64 %i, 1
+ %exitcond = icmp eq i64 %inc, %len
+ br i1 %exitcond, label %ret0, label %for.body
+
+for.end:
+ %cmp.end = icmp eq i64 %i, %len
+ %add = add i64 %i, 1
+ br i1 %cmp.end, label %ret0, label %for.cond
+
+ret0:
+ ret i32 0
+
+ret1:
+ ret i32 1
+}
+
+define i32 @freeze_i8_load_loop(ptr %p, i32 %n) {
+; CHECK-LABEL: freeze_i8_load_loop:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: mov x8, x0
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: mov w9, wzr
+; CHECK-NEXT: ldrb w8, [x8]
+; CHECK-NEXT: LBB1_1: ; %loop
+; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: add w9, w9, #1
+; CHECK-NEXT: add w0, w0, w8
+; CHECK-NEXT: cmp w9, w1
+; CHECK-NEXT: b.lt LBB1_1
+; CHECK-NEXT: ; %bb.2: ; %exit
+; CHECK-NEXT: ret
+ %load = load i8, ptr %p
+ %freeze = freeze i8 %load
+ %zext = zext i8 %freeze to i32
+ br label %loop
+
+loop:
+ %acc = phi i32 [ 0, %0 ], [ %sum, %loop ]
+ %i = phi i32 [ 0, %0 ], [ %inc, %loop ]
+ %sum = add i32 %acc, %zext
+ %inc = add i32 %i, 1
+ %cmp = icmp slt i32 %inc, %n
+ br i1 %cmp, label %loop, label %exit
+
+exit:
+ ret i32 %sum
+}
+
+define i32 @freeze_i16_load_cross_bb(ptr %p, i1 %cond) {
+; CHECK-LABEL: freeze_i16_load_cross_bb:
+; CHECK: ; %bb.0: ; %common.ret
+; CHECK-NEXT: ldrh w8, [x0]
+; CHECK-NEXT: tst w1, #0x1
+; CHECK-NEXT: csel w0, w8, wzr, ne
+; CHECK-NEXT: ret
+ %load = load i16, ptr %p
+ %freeze = freeze i16 %load
+ br i1 %cond, label %then, label %else
+
+then:
+ %zext = zext i16 %freeze to i32
+ ret i32 %zext
+
+else:
+ ret i32 0
+}
+
+define i32 @freeze_non_load_cross_bb(i8 %val, i1 %cond) {
+; CHECK-LABEL: freeze_non_load_cross_bb:
+; CHECK: ; %bb.0: ; %common.ret
+; CHECK-NEXT: and w8, w0, #0xff
+; CHECK-NEXT: tst w1, #0x1
+; CHECK-NEXT: csel w0, w8, wzr, ne
+; CHECK-NEXT: ret
+ %freeze = freeze i8 %val
+ br i1 %cond, label %then, label %else
+
+then:
+ %zext = zext i8 %freeze to i32
+ ret i32 %zext
+
+else:
+ ret i32 0
+}
diff --git a/llvm/test/CodeGen/PowerPC/freeze-load-zext-copytoreg.ll b/llvm/test/CodeGen/PowerPC/freeze-load-zext-copytoreg.ll
new file mode 100644
index 0000000000000..37ae57dabadf7
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/freeze-load-zext-copytoreg.ll
@@ -0,0 +1,162 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc64le-linux-gnu < %s | FileCheck %s
+
+define i32 @freeze_i8_load_multi_bb(ptr %p, i64 %len) {
+; CHECK-LABEL: freeze_i8_load_multi_bb:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi 6, 4, 1
+; CHECK-NEXT: addi 5, 4, -1
+; CHECK-NEXT: mtctr 6
+; CHECK-NEXT: li 6, 0
+; CHECK-NEXT: b .LBB0_2
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: .LBB0_1: # %for.end
+; CHECK-NEXT: #
+; CHECK-NEXT: cmpld 6, 4
+; CHECK-NEXT: addi 6, 6, 1
+; CHECK-NEXT: beq 0, .LBB0_8
+; CHECK-NEXT: .LBB0_2: # %for.cond
+; CHECK-NEXT: # =>This Loop Header: Depth=1
+; CHECK-NEXT: # Child Loop BB0_4 Depth 2
+; CHECK-NEXT: bdz .LBB0_9
+; CHECK-NEXT: # %bb.3: # %for.body.preheader
+; CHECK-NEXT: #
+; CHECK-NEXT: lbzx 7, 3, 6
+; CHECK-NEXT: cmpd 1, 6, 5
+; CHECK-NEXT: cmplwi 7, 31
+; CHECK-NEXT: cmplwi 5, 7, 34
+; CHECK-NEXT: .p2align 5
+; CHECK-NEXT: .LBB0_4: # %for.body
+; CHECK-NEXT: # Parent Loop BB0_2 Depth=1
+; CHECK-NEXT: # => This Inner Loop Header: Depth=2
+; CHECK-NEXT: bc 4, 1, .LBB0_1
+; CHECK-NEXT: # %bb.5: # %switch.test
+; CHECK-NEXT: #
+; CHECK-NEXT: beq 5, .LBB0_1
+; CHECK-NEXT: # %bb.6: # %switch.test
+; CHECK-NEXT: #
+; CHECK-NEXT: cmplwi 6, 7, 92
+; CHECK-NEXT: beq 6, .LBB0_1
+; CHECK-NEXT: # %bb.7: # %for.inc
+; CHECK-NEXT: #
+; CHECK-NEXT: bc 4, 6, .LBB0_4
+; CHECK-NEXT: .LBB0_8: # %ret0
+; CHECK-NEXT: li 3, 0
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB0_9: # %ret1
+; CHECK-NEXT: li 3, 1
+; CHECK-NEXT: blr
+ br label %for.cond
+
+for.cond:
+ %i = phi i64 [ 0, %0 ], [ %add, %for.end ]
+ %cmp = icmp ult i64 %i, %len
+ br i1 %cmp, label %for.body, label %ret1
+
+for.body:
+ %arrayidx = getelementptr inbounds i8, ptr %p, i64 %i
+ %load = load i8, ptr %arrayidx, align 1
+ %freeze = freeze i8 %load
+ %cmp.lo = icmp ugt i8 %freeze, 31
+ br i1 %cmp.lo, label %switch.test, label %for.end
+
+switch.test:
+ switch i8 %freeze, label %for.inc [
+ i8 92, label %for.end
+ i8 34, label %for.end
+ ]
+
+for.inc:
+ %inc = add nuw i64 %i, 1
+ %exitcond = icmp eq i64 %inc, %len
+ br i1 %exitcond, label %ret0, label %for.body
+
+for.end:
+ %cmp.end = icmp eq i64 %i, %len
+ %add = add i64 %i, 1
+ br i1 %cmp.end, label %ret0, label %for.cond
+
+ret0:
+ ret i32 0
+
+ret1:
+ ret i32 1
+}
+
+define i32 @freeze_i8_load_loop(ptr %p, i32 %n) {
+; CHECK-LABEL: freeze_i8_load_loop:
+; CHECK: # %bb.0:
+; CHECK-NEXT: cmpwi 4, 1
+; CHECK-NEXT: li 5, 1
+; CHECK-NEXT: lbz 3, 0(3)
+; CHECK-NEXT: iselgt 4, 4, 5
+; CHECK-NEXT: mullw 3, 4, 3
+; CHECK-NEXT: clrldi 4, 4, 32
+; CHECK-NEXT: mtctr 4
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: .LBB1_1: # %loop
+; CHECK-NEXT: #
+; CHECK-NEXT: bdnz .LBB1_1
+; CHECK-NEXT: # %bb.2: # %exit
+; CHECK-NEXT: blr
+ %load = load i8, ptr %p
+ %freeze = freeze i8 %load
+ %zext = zext i8 %freeze to i32
+ br label %loop
+
+loop:
+ %acc = phi i32 [ 0, %0 ], [ %sum, %loop ]
+ %i = phi i32 [ 0, %0 ], [ %inc, %loop ]
+ %sum = add i32 %acc, %zext
+ %inc = add i32 %i, 1
+ %cmp = icmp slt i32 %inc, %n
+ br i1 %cmp, label %loop, label %exit
+
+exit:
+ ret i32 %sum
+}
+
+define i32 @freeze_i16_load_cross_bb(ptr %p, i1 %cond) {
+; CHECK-LABEL: freeze_i16_load_cross_bb:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andi. 4, 4, 1
+; CHECK-NEXT: bc 4, 1, .LBB2_2
+; CHECK-NEXT: # %bb.1: # %then
+; CHECK-NEXT: lhz 3, 0(3)
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB2_2: # %else
+; CHECK-NEXT: li 3, 0
+; CHECK-NEXT: blr
+ %load = load i16, ptr %p
+ %freeze = freeze i16 %load
+ br i1 %cond, label %then, label %else
+
+then:
+ %zext = zext i16 %freeze to i32
+ ret i32 %zext
+
+else:
+ ret i32 0
+}
+
+define i32 @freeze_non_load_cross_bb(i8 %val, i1 %cond) {
+; CHECK-LABEL: freeze_non_load_cross_bb:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andi. 4, 4, 1
+; CHECK-NEXT: bc 4, 1, .LBB3_2
+; CHECK-NEXT: # %bb.1: # %then
+; CHECK-NEXT: clrldi 3, 3, 56
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB3_2: # %else
+; CHECK-NEXT: li 3, 0
+; CHECK-NEXT: blr
+ %freeze = freeze i8 %val
+ br i1 %cond, label %then, label %else
+
+then:
+ %zext = zext i8 %freeze to i32
+ ret i32 %zext
+
+else:
+ ret i32 0
+}
diff --git a/llvm/test/CodeGen/RISCV/freeze-load-zext-copytoreg.ll b/llvm/test/CodeGen/RISCV/freeze-load-zext-copytoreg.ll
new file mode 100644
index 0000000000000..447912f731865
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/freeze-load-zext-copytoreg.ll
@@ -0,0 +1,156 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s
+
+define i32 @freeze_i8_load_multi_bb(ptr %p, i64 %len) {
+; CHECK-LABEL: freeze_i8_load_multi_bb:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a5, 0
+; CHECK-NEXT: li a2, 32
+; CHECK-NEXT: li a3, 34
+; CHECK-NEXT: li a4, 92
+; CHECK-NEXT: j .LBB0_2
+; CHECK-NEXT: .LBB0_1: # %for.end
+; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1
+; CHECK-NEXT: beq a6, a1, .LBB0_8
+; CHECK-NEXT: .LBB0_2: # %for.cond
+; CHECK-NEXT: # =>This Loop Header: Depth=1
+; CHECK-NEXT: # Child Loop BB0_4 Depth 2
+; CHECK-NEXT: bgeu a5, a1, .LBB0_9
+; CHECK-NEXT: # %bb.3: # %for.body.preheader
+; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1
+; CHECK-NEXT: mv a6, a5
+; CHECK-NEXT: add a7, a0, a5
+; CHECK-NEXT: addi a5, a5, 1
+; CHECK-NEXT: .LBB0_4: # %for.body
+; CHECK-NEXT: # Parent Loop BB0_2 Depth=1
+; CHECK-NEXT: # => This Inner Loop Header: Depth=2
+; CHECK-NEXT: lbu t0, 0(a7)
+; CHECK-NEXT: bltu t0, a2, .LBB0_1
+; CHECK-NEXT: # %bb.5: # %switch.test
+; CHECK-NEXT: # in Loop: Header=BB0_4 Depth=2
+; CHECK-NEXT: beq t0, a3, .LBB0_1
+; CHECK-NEXT: # %bb.6: # %switch.test
+; CHECK-NEXT: # in Loop: Header=BB0_4 Depth=2
+; CHECK-NEXT: beq t0, a4, .LBB0_1
+; CHECK-NEXT: # %bb.7: # %for.inc
+; CHECK-NEXT: # in Loop: Header=BB0_4 Depth=2
+; CHECK-NEXT: bne a5, a1, .LBB0_4
+; CHECK-NEXT: .LBB0_8: # %ret0
+; CHECK-NEXT: li a0, 0
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB0_9: # %ret1
+; CHECK-NEXT: li a0, 1
+; CHECK-NEXT: ret
+ br label %for.cond
+
+for.cond:
+ %i = phi i64 [ 0, %0 ], [ %add, %for.end ]
+ %cmp = icmp ult i64 %i, %len
+ br i1 %cmp, label %for.body, label %ret1
+
+for.body:
+ %arrayidx = getelementptr inbounds i8, ptr %p, i64 %i
+ %load = load i8, ptr %arrayidx, align 1
+ %freeze = freeze i8 %load
+ %cmp.lo = icmp ugt i8 %freeze, 31
+ br i1 %cmp.lo, label %switch.test, label %for.end
+
+switch.test:
+ switch i8 %freeze, label %for.inc [
+ i8 92, label %for.end
+ i8 34, label %for.end
+ ]
+
+for.inc:
+ %inc = add nuw i64 %i, 1
+ %exitcond = icmp eq i64 %inc, %len
+ br i1 %exitcond, label %ret0, label %for.body
+
+for.end:
+ %cmp.end = icmp eq i64 %i, %len
+ %add = add i64 %i, 1
+ br i1 %cmp.end, label %ret0, label %for.cond
+
+ret0:
+ ret i32 0
+
+ret1:
+ ret i32 1
+}
+
+define i32 @freeze_i8_load_loop(ptr %p, i32 %n) {
+; CHECK-LABEL: freeze_i8_load_loop:
+; CHECK: # %bb.0:
+; CHECK-NEXT: mv a2, a0
+; CHECK-NEXT: li a0, 0
+; CHECK-NEXT: li a3, 0
+; CHECK-NEXT: lbu a2, 0(a2)
+; CHECK-NEXT: sext.w a1, a1
+; CHECK-NEXT: .LBB1_1: # %loop
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: addiw a3, a3, 1
+; CHECK-NEXT: addw a0, a0, a2
+; CHECK-NEXT: blt a3, a1, .LBB1_1
+; CHECK-NEXT: # %bb.2: # %exit
+; CHECK-NEXT: ret
+ %load = load i8, ptr %p
+ %freeze = freeze i8 %load
+ %zext = zext i8 %freeze to i32
+ br label %loop
+
+loop:
+ %acc = phi i32 [ 0, %0 ], [ %sum, %loop ]
+ %i = phi i32 [ 0, %0 ], [ %inc, %loop ]
+ %sum = add i32 %acc, %zext
+ %inc = add i32 %i, 1
+ %cmp = icmp slt i32 %inc, %n
+ br i1 %cmp, label %loop, label %exit
+
+exit:
+ ret i32 %sum
+}
+
+define i32 @freeze_i16_load_cross_bb(ptr %p, i1 %cond) {
+; CHECK-LABEL: freeze_i16_load_cross_bb:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: beqz a1, .LBB2_2
+; CHECK-NEXT: # %bb.1: # %then
+; CHECK-NEXT: lhu a0, 0(a0)
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB2_2: # %else
+; CHECK-NEXT: li a0, 0
+; CHECK-NEXT: ret
+ %load = load i16, ptr %p
+ %freeze = freeze i16 %load
+ br i1 %cond, label %then, label %else
+
+then:
+ %zext = zext i16 %freeze to i32
+ ret i32 %zext
+
+else:
+ ret i32 0
+}
+
+define i32 @freeze_non_load_cross_bb(i8 %val, i1 %cond) {
+; CHECK-LABEL: freeze_non_load_cross_bb:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: beqz a1, .LBB3_2
+; CHECK-NEXT: # %bb.1: # %then
+; CHECK-NEXT: zext.b a0, a0
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB3_2: # %else
+; CHECK-NEXT: li a0, 0
+; CHECK-NEXT: ret
+ %freeze = freeze i8 %val
+ br i1 %cond, label %then, label %else
+
+then:
+ %zext = zext i8 %freeze to i32
+ ret i32 %zext
+
+else:
+ ret i32 0
+}
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