[llvm] Multiplication swap (PR #195494)
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git-clang-format --diff origin/main HEAD --extensions h,cpp -- llvm/include/llvm/CodeGen/TargetInstrInfo.h llvm/lib/CodeGen/TargetInstrInfo.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.cpp llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/lib/Target/ARM/ARMBaseInstrInfo.h llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/lib/Target/ARM/ARMISelLowering.cpp llvm/lib/Target/ARM/ARMTargetMachine.cpp --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 324dd7190..9d9494d1a 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -669,7 +669,8 @@ static void armAppendConditionOperands(MachineInstrBuilder &MIB,
}
/// Copy predicate / optional cc operands from \p Root so the fused Thumb2 MI
-/// matches \p NewDesc (e.g. \p t2MLA has predicate only; \p t2ADDrr has cc_out).
+/// matches \p NewDesc (e.g. \p t2MLA has predicate only; \p t2ADDrr has
+/// cc_out).
static void thumb2AppendMatchingTailOperands(MachineInstrBuilder &MIB,
const MachineInstr &Root,
const MCInstrDesc &NewDesc) {
@@ -683,16 +684,15 @@ static void thumb2AppendMatchingTailOperands(MachineInstrBuilder &MIB,
MIB.add(Root.getOperand(RP + i));
}
-/// Emit t2MLA merging Thumb2 \p Root with ARM::t2MUL feeding operand \p IdxMulOpd.
-static MachineInstr *genThumb2GPRMLA(MachineFunction &MF,
- MachineRegisterInfo &MRI,
- const TargetInstrInfo *TII, MachineInstr &Root,
- SmallVectorImpl<MachineInstr *> &InsInstrs,
- unsigned IdxMulOpd,
- const TargetRegisterClass *RC) {
+/// Emit t2MLA merging Thumb2 \p Root with ARM::t2MUL feeding operand \p
+/// IdxMulOpd.
+static MachineInstr *
+genThumb2GPRMLA(MachineFunction &MF, MachineRegisterInfo &MRI,
+ const TargetInstrInfo *TII, MachineInstr &Root,
+ SmallVectorImpl<MachineInstr *> &InsInstrs, unsigned IdxMulOpd,
+ const TargetRegisterClass *RC) {
assert(IdxMulOpd == 1 || IdxMulOpd == 2);
- MachineInstr *Mul =
- MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg());
+ MachineInstr *Mul = MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg());
assert(Mul->getOpcode() == ARM::t2MUL && "Expected Thumb2 t2MUL");
Register Dst = Root.getOperand(0).getReg();
@@ -723,17 +723,16 @@ static MachineInstr *genThumb2GPRMLA(MachineFunction &MF,
return Mul;
}
-/// Emit t2MLS Rd = Ra - Rn*Rm for t2SUBrr where \p IdxMulOpd points at the product.
-static MachineInstr *genThumb2GPRMLS(MachineFunction &MF,
- MachineRegisterInfo &MRI,
- const TargetInstrInfo *TII, MachineInstr &Root,
- SmallVectorImpl<MachineInstr *> &InsInstrs,
- unsigned IdxMulOpd,
- const TargetRegisterClass *RC) {
+/// Emit t2MLS Rd = Ra - Rn*Rm for t2SUBrr where \p IdxMulOpd points at the
+/// product.
+static MachineInstr *
+genThumb2GPRMLS(MachineFunction &MF, MachineRegisterInfo &MRI,
+ const TargetInstrInfo *TII, MachineInstr &Root,
+ SmallVectorImpl<MachineInstr *> &InsInstrs, unsigned IdxMulOpd,
+ const TargetRegisterClass *RC) {
assert(IdxMulOpd == 2 &&
"MLS fusion only matches SUB when multiply uses subtract operand");
- MachineInstr *Mul =
- MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg());
+ MachineInstr *Mul = MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg());
assert(Mul->getOpcode() == ARM::t2MUL && "Expected Thumb2 t2MUL");
Register Dst = Root.getOperand(0).getReg();
@@ -764,12 +763,12 @@ static MachineInstr *genThumb2GPRMLS(MachineFunction &MF,
}
/// t2SUBrr with mul on operand 1: emit t2RSBri + t2MLA.
-static MachineInstr *genThumb2GPRMLASubMulOp1(
- MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII,
- MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs,
- DenseMap<Register, unsigned> &InstrIdxForVirtReg) {
- MachineInstr *Mul =
- MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
+static MachineInstr *
+genThumb2GPRMLASubMulOp1(MachineFunction &MF, MachineRegisterInfo &MRI,
+ const TargetInstrInfo *TII, MachineInstr &Root,
+ SmallVectorImpl<MachineInstr *> &InsInstrs,
+ DenseMap<Register, unsigned> &InstrIdxForVirtReg) {
+ MachineInstr *Mul = MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
assert(Mul->getOpcode() == ARM::t2MUL && "Expected Thumb2 t2MUL");
Register Dst = Root.getOperand(0).getReg();
@@ -807,16 +806,16 @@ static MachineInstr *genThumb2GPRMLASubMulOp1(
return Mul;
}
-/// Emit MLA merging ARM-mode \p Root with ARM::MUL feeding operand \p IdxMulOpd.
-static MachineInstr *genArmGPRMLA(MachineFunction &MF,
- MachineRegisterInfo &MRI,
- const TargetInstrInfo *TII, MachineInstr &Root,
+/// Emit MLA merging ARM-mode \p Root with ARM::MUL feeding operand \p
+/// IdxMulOpd.
+static MachineInstr *genArmGPRMLA(MachineFunction &MF, MachineRegisterInfo &MRI,
+ const TargetInstrInfo *TII,
+ MachineInstr &Root,
SmallVectorImpl<MachineInstr *> &InsInstrs,
unsigned IdxMulOpd,
const TargetRegisterClass *RC) {
assert(IdxMulOpd == 1 || IdxMulOpd == 2);
- MachineInstr *Mul =
- MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg());
+ MachineInstr *Mul = MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg());
assert(Mul->getOpcode() == ARM::MUL && "Expected ARM-mode MUL");
Register Dst = Root.getOperand(0).getReg();
@@ -848,16 +847,15 @@ static MachineInstr *genArmGPRMLA(MachineFunction &MF,
}
/// Emit MLS Rd = Ra - Rn*Rm for SUBrr where \p IdxMulOpd points at the product.
-static MachineInstr *genArmGPRMLS(MachineFunction &MF,
- MachineRegisterInfo &MRI,
- const TargetInstrInfo *TII, MachineInstr &Root,
+static MachineInstr *genArmGPRMLS(MachineFunction &MF, MachineRegisterInfo &MRI,
+ const TargetInstrInfo *TII,
+ MachineInstr &Root,
SmallVectorImpl<MachineInstr *> &InsInstrs,
unsigned IdxMulOpd,
const TargetRegisterClass *RC) {
assert(IdxMulOpd == 2 &&
"MLS fusion only matches SUB when multiply uses subtract operand");
- MachineInstr *Mul =
- MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg());
+ MachineInstr *Mul = MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg());
assert(Mul->getOpcode() == ARM::MUL && "Expected ARM-mode MUL");
Register Dst = Root.getOperand(0).getReg();
@@ -888,12 +886,12 @@ static MachineInstr *genArmGPRMLS(MachineFunction &MF,
}
/// SUBrr with mul on operand 1: emit RSB + MLA like AArch64 SUB+0 + MADD.
-static MachineInstr *genArmGPRMLASubMulOp1(
- MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII,
- MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs,
- DenseMap<Register, unsigned> &InstrIdxForVirtReg) {
- MachineInstr *Mul =
- MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
+static MachineInstr *
+genArmGPRMLASubMulOp1(MachineFunction &MF, MachineRegisterInfo &MRI,
+ const TargetInstrInfo *TII, MachineInstr &Root,
+ SmallVectorImpl<MachineInstr *> &InsInstrs,
+ DenseMap<Register, unsigned> &InstrIdxForVirtReg) {
+ MachineInstr *Mul = MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
assert(Mul->getOpcode() == ARM::MUL && "Expected ARM-mode MUL");
Register Dst = Root.getOperand(0).getReg();
@@ -978,8 +976,9 @@ static bool getThumb2MaddPatterns(const ARMSubtarget &Subtarget,
}
/// Find instructions that can be turned into MLA / MLS (ARM-state GPR).
-static bool getARMMaddPatterns(const ARMSubtarget &Subtarget, MachineInstr &Root,
- SmallVectorImpl<unsigned> &Patterns) {
+static bool getARMMaddPatterns(const ARMSubtarget &Subtarget,
+ MachineInstr &Root,
+ SmallVectorImpl<unsigned> &Patterns) {
unsigned Opc = Root.getOpcode();
MachineBasicBlock &MBB = *Root.getParent();
bool Found = false;
@@ -989,7 +988,8 @@ static bool getARMMaddPatterns(const ARMSubtarget &Subtarget, MachineInstr &Root
// MLA/MLS do not provide ADD/SUB-with-S-bit flag semantics. Do not fuse when
// the root defines CPSR: conditional ARM instructions depend on flags without
- // necessarily listing an explicit CPSR use, so IsCPSRDead(&Root) is unreliable.
+ // necessarily listing an explicit CPSR use, so IsCPSRDead(&Root) is
+ // unreliable.
//
// Contrast AArch64 getMaddPatterns: ADDS/SUBS use separate opcodes and may be
// converted to non-flag ADD/SUB for fusion when an NZCV def operand exists.
@@ -1067,8 +1067,8 @@ void ARMBaseInstrInfo::genAlternativeCodeSequence(
MachineInstr *MulToDelete = nullptr;
typedef ARMMachineCombinerPattern MCP;
- const bool Thumb2GPRMLxRoot = Root.getOpcode() == ARM::t2ADDrr ||
- Root.getOpcode() == ARM::t2SUBrr;
+ const bool Thumb2GPRMLxRoot =
+ Root.getOpcode() == ARM::t2ADDrr || Root.getOpcode() == ARM::t2SUBrr;
switch (Pattern) {
default:
@@ -1090,19 +1090,18 @@ void ARMBaseInstrInfo::genAlternativeCodeSequence(
&ARM::GPRnopcRegClass);
break;
case MCP::MULSUB_OP1:
- MulToDelete =
- Thumb2GPRMLxRoot
- ? genThumb2GPRMLASubMulOp1(MF, MRI, TII, Root, InsInstrs,
- InstrIdxForVirtReg)
- : genArmGPRMLASubMulOp1(MF, MRI, TII, Root, InsInstrs,
- InstrIdxForVirtReg);
+ MulToDelete = Thumb2GPRMLxRoot
+ ? genThumb2GPRMLASubMulOp1(MF, MRI, TII, Root, InsInstrs,
+ InstrIdxForVirtReg)
+ : genArmGPRMLASubMulOp1(MF, MRI, TII, Root, InsInstrs,
+ InstrIdxForVirtReg);
break;
case MCP::MULSUB_OP2:
- MulToDelete = Thumb2GPRMLxRoot
- ? genThumb2GPRMLS(MF, MRI, TII, Root, InsInstrs, 2,
- &ARM::rGPRRegClass)
- : genArmGPRMLS(MF, MRI, TII, Root, InsInstrs, 2,
- &ARM::GPRRegClass);
+ MulToDelete =
+ Thumb2GPRMLxRoot
+ ? genThumb2GPRMLS(MF, MRI, TII, Root, InsInstrs, 2,
+ &ARM::rGPRRegClass)
+ : genArmGPRMLS(MF, MRI, TII, Root, InsInstrs, 2, &ARM::GPRRegClass);
break;
}
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index 7eb7fd0a3..27560d4e4 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -39,7 +39,6 @@ namespace llvm {
class ARMBaseRegisterInfo;
class ARMSubtarget;
-
// ARM MachineCombiner patterns
enum ARMMachineCombinerPattern : unsigned {
// These are patterns used to reduce the length of dependence chain.
``````````
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https://github.com/llvm/llvm-project/pull/195494
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