[llvm] [x86-64] `lzcnt64(x) + (x == 0)` => `lzcnt+adc` (PR #195487)

[via llvm-commits]

llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-x86

Author: Madhur Kumar (MadhurKumar004)

<details>
<summary>Changes</summary>

fix: https://github.com/llvm/llvm-project/issues/193178

---
Full diff: https://github.com/llvm/llvm-project/pull/195487.diff


2 Files Affected:

- (modified) llvm/lib/Target/X86/X86InstrInfo.cpp (+16) 
- (added) llvm/test/CodeGen/X86/lzcnt-adc.ll (+30) 


``````````diff
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 5d4db845c5030..ef368078ecb4a 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -4981,6 +4981,22 @@ bool X86InstrInfo::isRedundantFlagInstr(const MachineInstr &FlagI,
     }
     return FlagI.isIdenticalTo(OI);
   }
+  case X86::LZCNT64rr:
+  case X86::LZCNT32rr:
+  case X86::LZCNT16rr:
+  case X86::TZCNT64rr:
+  case X86::TZCNT32rr:
+  case X86::TZCNT16rr:
+    // LZCNT/TZCNT set CF=1 iff src==0, identical to what SUB src, 1
+    // produces in CF. If FlagI is SUB SrcReg, 1, reuse these flags.
+    if (ImmMask != 0 && ImmValue == 1 && SrcReg2 == 0 &&
+        OI.getNumOperands() > 1 && OI.getOperand(1).isReg() &&
+        OI.getOperand(1).getReg() == SrcReg) {
+      *ImmDelta = 0;
+      *IsSwapped = false;
+      return true;
+    }
+    return false;
   default:
     return false;
   }
diff --git a/llvm/test/CodeGen/X86/lzcnt-adc.ll b/llvm/test/CodeGen/X86/lzcnt-adc.ll
new file mode 100644
index 0000000000000..41afd24f6d7b4
--- /dev/null
+++ b/llvm/test/CodeGen/X86/lzcnt-adc.ll
@@ -0,0 +1,30 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver5 | FileCheck %s
+
+declare i64 @llvm.ctlz.i64(i64, i1 immarg)
+declare i64 @llvm.cttz.i64(i64, i1 immarg)
+
+define i64 @lzcnt64_add_iszero(i64 %x) {
+; CHECK-LABEL: lzcnt64_add_iszero:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lzcntq %rdi, %rax
+; CHECK-NEXT:    adcq $0, %rax
+; CHECK-NEXT:    retq
+  %lzcnt = tail call i64 @llvm.ctlz.i64(i64 %x, i1 false)
+  %cmp = icmp eq i64 %x, 0
+  %ext = zext i1 %cmp to i64
+  %add = add i64 %lzcnt, %ext
+  ret i64 %add
+}
+define i64 @tzcnt64_add_iszero(i64 %x) {
+; CHECK-LABEL: tzcnt64_add_iszero:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    tzcntq %rdi, %rax
+; CHECK-NEXT:    adcq $0, %rax
+; CHECK-NEXT:    retq
+  %tzcnt = tail call i64 @llvm.cttz.i64(i64 %x, i1 false)
+  %cmp = icmp eq i64 %x, 0
+  %ext = zext i1 %cmp to i64
+  %add = add i64 %tzcnt, %ext
+  ret i64 %add
+}

``````````

</details>


https://github.com/llvm/llvm-project/pull/195487