[llvm] [AMDGPU] Post-RA Peephole for latency-hiding and hazard-avoidance bet… (PR #191319)

[Zeng Wu via llvm-commits]

zwu-2025 wrote:

After the investigation, the problem can be simplified into:
```
Loop_Top:
  1. BUFFER_LOAD (Data for N+1)
  2. S_WAITCNT / S_BARRIER     <--- Scheduler cannot move load past this
  3. DS_WRITE (Data for N+1 to LDS)
  4. S_WAITCNT / S_BARRIER     <--- Scheduler cannot move MFMA above this
  5. DS_READ (Data for N from LDS)
  6. V_MFMA (Compute N)
  7. Branch Loop_Top
 ```

The `s_barrier` makes `buffer_load` into the separate schedule region from a list of mfma, so that the buffer_load latency is not overlapped by `mfma`. Actually, it is typical limit of machine scheduler pass, for this cross-iteration dependency detection and it should not be handled in machine scheduler itself and right place might be where the barrier is created in llvm-ir generation. So close it now and thanks for all the reviewer's time and comment.

https://github.com/llvm/llvm-project/pull/191319