[llvm] [AMDGPU] Optimize DPP for fmin/fmax functions (PR #195282)

[Joseph Huber via llvm-commits]

================
@@ -93,6 +93,90 @@ define amdgpu_kernel void @dpp_fadd_f16(ptr addrspace(1) %arg) {
   ret void
 }
 
+; GCN-LABEL: {{^}}dpp_fmin_f32:
+; GCN: v_min{{(_num)?}}_f32_dpp v0, v0, v0 row_shr:1 row_mask:0xf bank_mask:0xf{{$}}
+; GCN: v_min{{(_num)?}}_f32_dpp v0, v0, v0 row_shr:2 row_mask:0xf bank_mask:0xf{{$}}
+; GCN: v_min{{(_num)?}}_f32_dpp v0, v0, v0 row_shr:4 row_mask:0xf bank_mask:0xf{{$}}
+; GCN: v_min{{(_num)?}}_f32_dpp v0, v0, v0 row_shr:8 row_mask:0xf bank_mask:0xf{{$}}
+define nofpclass(nan) float @dpp_fmin_f32(float nofpclass(nan) %x) {
+entry:
+  %dpp.shr1 = tail call float @llvm.amdgcn.update.dpp.f32(float 0x7FF0000000000000, float %x, i32 273, i32 15, i32 15, i1 false)
+  %min1 = tail call nnan float @llvm.minnum.f32(float %x, float %dpp.shr1)
----------------
jhuber6 wrote:

Was generated that way from my original C input, removing them makes them no longer combine because of the SNaN checks.

https://github.com/llvm/llvm-project/pull/195282