[llvm] [DAG] SimplifyDemandedVectorElts - add basic integer MIN/MAX handling (PR #195275)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri May 1 08:52:37 PDT 2026
https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/195275
>From d1588123d7e60f1db6499f692738d3c34c364d72 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Fri, 1 May 2026 16:17:09 +0100
Subject: [PATCH] [DAG] SimplifyDemandedVectorElts - add basic integer MIN/MAX
handling
---
llvm/include/llvm/CodeGen/SelectionDAGNodes.h | 6 ++
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 58 +++++++++++--------
.../CodeGen/SelectionDAG/TargetLowering.cpp | 33 ++++++++++-
.../CodeGen/LoongArch/lsx/vec-reduce-smax.ll | 5 +-
.../CodeGen/LoongArch/lsx/vec-reduce-smin.ll | 5 +-
.../CodeGen/LoongArch/lsx/vec-reduce-umax.ll | 5 +-
.../CodeGen/LoongArch/lsx/vec-reduce-umin.ll | 5 +-
.../CodeGen/X86/combine-mask-with-shuffle.ll | 32 ++++++----
llvm/test/CodeGen/X86/known-never-zero.ll | 9 ++-
.../CodeGen/X86/urem-seteq-vec-nonzero.ll | 2 +-
.../X86/urem-seteq-vec-tautological.ll | 10 ++--
11 files changed, 114 insertions(+), 56 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
index 2d5e92381ef64..2f4c7d70c781f 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -1949,6 +1949,12 @@ LLVM_ABI bool isOneConstant(SDValue V);
/// Returns true if \p V is a constant min signed integer value.
LLVM_ABI bool isMinSignedConstant(SDValue V);
+/// Returns true if \p C is a neutral integer element of Opc.
+/// When OperandNo is 0, it checks that C is a left identity. Otherwise, it
+/// checks that C is a right identity.
+LLVM_ABI bool isNeutralConstant(unsigned Opc, const APInt &C,
+ unsigned OperandNo);
+
/// Returns true if \p V is a neutral element of Opc with Flags.
/// When OperandNo is 0, it checks that V is a left identity. Otherwise, it
/// checks that V is a right identity.
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index f91f0bb63cebc..af0549453759e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -13500,6 +13500,35 @@ bool llvm::isMinSignedConstant(SDValue V) {
return Const != nullptr && Const->isMinSignedValue();
}
+bool llvm::isNeutralConstant(unsigned Opcode, const APInt &C,
+ unsigned OperandNo) {
+ switch (Opcode) {
+ case ISD::ADD:
+ case ISD::OR:
+ case ISD::XOR:
+ case ISD::UMAX:
+ return C.isZero();
+ case ISD::MUL:
+ return C.isOne();
+ case ISD::AND:
+ case ISD::UMIN:
+ return C.isAllOnes();
+ case ISD::SMAX:
+ return C.isMinSignedValue();
+ case ISD::SMIN:
+ return C.isMaxSignedValue();
+ case ISD::SUB:
+ case ISD::SHL:
+ case ISD::SRA:
+ case ISD::SRL:
+ return OperandNo == 1 && C.isZero();
+ case ISD::UDIV:
+ case ISD::SDIV:
+ return OperandNo == 1 && C.isOne();
+ }
+ return false;
+}
+
bool llvm::isNeutralConstant(unsigned Opcode, SDNodeFlags Flags, SDValue V,
unsigned OperandNo) {
// NOTE: The cases should match with IR's ConstantExpr::getBinOpIdentity().
@@ -13507,31 +13536,10 @@ bool llvm::isNeutralConstant(unsigned Opcode, SDNodeFlags Flags, SDValue V,
if (auto *ConstV = isConstOrConstSplat(V, /*AllowUndefs*/ false,
/*AllowTruncation*/ true)) {
APInt Const = ConstV->getAPIntValue().trunc(V.getScalarValueSizeInBits());
- switch (Opcode) {
- case ISD::ADD:
- case ISD::OR:
- case ISD::XOR:
- case ISD::UMAX:
- return Const.isZero();
- case ISD::MUL:
- return Const.isOne();
- case ISD::AND:
- case ISD::UMIN:
- return Const.isAllOnes();
- case ISD::SMAX:
- return Const.isMinSignedValue();
- case ISD::SMIN:
- return Const.isMaxSignedValue();
- case ISD::SUB:
- case ISD::SHL:
- case ISD::SRA:
- case ISD::SRL:
- return OperandNo == 1 && Const.isZero();
- case ISD::UDIV:
- case ISD::SDIV:
- return OperandNo == 1 && Const.isOne();
- }
- } else if (auto *ConstFP = isConstOrConstSplatFP(V)) {
+ return isNeutralConstant(Opcode, Const, OperandNo);
+ }
+
+ if (auto *ConstFP = isConstOrConstSplatFP(V)) {
switch (Opcode) {
case ISD::FADD:
return ConstFP->isZero() &&
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 22f43145303b6..fa1858a980162 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -821,13 +821,19 @@ SDValue TargetLowering::SimplifyMultipleUseDemandedBits(
return Op.getOperand(1);
break;
}
- case ISD::ADD: {
+ case ISD::ADD:
+ case ISD::SMAX:
+ case ISD::SMIN:
+ case ISD::UMAX:
+ case ISD::UMIN: {
RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
- if (RHSKnown.isZero())
+ if (RHSKnown.isConstant() &&
+ isNeutralConstant(Op.getOpcode(), RHSKnown.getConstant(), 1))
return Op.getOperand(0);
LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
- if (LHSKnown.isZero())
+ if (LHSKnown.isConstant() &&
+ isNeutralConstant(Op.getOpcode(), LHSKnown.getConstant(), 0))
return Op.getOperand(1);
break;
}
@@ -3856,6 +3862,27 @@ bool TargetLowering::SimplifyDemandedVectorElts(
return true;
break;
}
+ case ISD::SMAX:
+ case ISD::SMIN:
+ case ISD::UMAX:
+ case ISD::UMIN: {
+ SDValue Op0 = Op.getOperand(0);
+ SDValue Op1 = Op.getOperand(1);
+
+ APInt SrcUndef, SrcZero;
+ if (SimplifyDemandedVectorElts(Op1, DemandedElts, SrcUndef, SrcZero, TLO,
+ Depth + 1))
+ return true;
+ if (SimplifyDemandedVectorElts(Op0, DemandedElts, SrcUndef, SrcZero, TLO,
+ Depth + 1))
+ return true;
+
+ // Attempt to avoid multi-use ops if we don't need anything from them.
+ if (!DemandedElts.isAllOnes())
+ if (SimplifyDemandedVectorEltsBinOp(Op0, Op1))
+ return true;
+ break;
+ }
case ISD::TRUNCATE:
case ISD::SIGN_EXTEND:
case ISD::ZERO_EXTEND:
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smax.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smax.ll
index 2220df68cddfd..39a2251759c5a 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smax.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smax.ll
@@ -184,8 +184,9 @@ define void @vec_reduce_smax_v2i32(ptr %src, ptr %dst) nounwind {
; LA32-NEXT: ld.w $a2, $a0, 0
; LA32-NEXT: ld.w $a0, $a0, 4
; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
-; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
+; LA32-NEXT: vori.b $vr1, $vr0, 0
+; LA32-NEXT: vinsgr2vr.w $vr1, $a0, 1
+; LA32-NEXT: vbsrl.v $vr1, $vr1, 4
; LA32-NEXT: vmax.w $vr0, $vr1, $vr0
; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0
; LA32-NEXT: st.w $a0, $a1, 0
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smin.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smin.ll
index 50d76a3872e1e..f266dd4941e71 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smin.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smin.ll
@@ -184,8 +184,9 @@ define void @vec_reduce_smin_v2i32(ptr %src, ptr %dst) nounwind {
; LA32-NEXT: ld.w $a2, $a0, 0
; LA32-NEXT: ld.w $a0, $a0, 4
; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
-; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
+; LA32-NEXT: vori.b $vr1, $vr0, 0
+; LA32-NEXT: vinsgr2vr.w $vr1, $a0, 1
+; LA32-NEXT: vbsrl.v $vr1, $vr1, 4
; LA32-NEXT: vmin.w $vr0, $vr1, $vr0
; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0
; LA32-NEXT: st.w $a0, $a1, 0
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umax.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umax.ll
index 88146c78a969d..05555212c6bc8 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umax.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umax.ll
@@ -184,8 +184,9 @@ define void @vec_reduce_umax_v2i32(ptr %src, ptr %dst) nounwind {
; LA32-NEXT: ld.w $a2, $a0, 0
; LA32-NEXT: ld.w $a0, $a0, 4
; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
-; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
+; LA32-NEXT: vori.b $vr1, $vr0, 0
+; LA32-NEXT: vinsgr2vr.w $vr1, $a0, 1
+; LA32-NEXT: vbsrl.v $vr1, $vr1, 4
; LA32-NEXT: vmax.wu $vr0, $vr1, $vr0
; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0
; LA32-NEXT: st.w $a0, $a1, 0
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umin.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umin.ll
index e9d4b4aab6f91..d4c06b677aa1a 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umin.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umin.ll
@@ -184,8 +184,9 @@ define void @vec_reduce_umin_v2i32(ptr %src, ptr %dst) nounwind {
; LA32-NEXT: ld.w $a2, $a0, 0
; LA32-NEXT: ld.w $a0, $a0, 4
; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
-; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
+; LA32-NEXT: vori.b $vr1, $vr0, 0
+; LA32-NEXT: vinsgr2vr.w $vr1, $a0, 1
+; LA32-NEXT: vbsrl.v $vr1, $vr1, 4
; LA32-NEXT: vmin.wu $vr0, $vr1, $vr0
; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0
; LA32-NEXT: st.w $a0, $a1, 0
diff --git a/llvm/test/CodeGen/X86/combine-mask-with-shuffle.ll b/llvm/test/CodeGen/X86/combine-mask-with-shuffle.ll
index 7564e65a428b7..475a403c0786d 100644
--- a/llvm/test/CodeGen/X86/combine-mask-with-shuffle.ll
+++ b/llvm/test/CodeGen/X86/combine-mask-with-shuffle.ll
@@ -67,9 +67,11 @@ define <16 x i32> @combine_mask_with_abs(<16 x i32> %v0) {
define <16 x i32> @combine_mask_with_umin(<16 x i32> %v0) {
; CHECK-LABEL: combine_mask_with_umin:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
-; CHECK-NEXT: vpshufd {{.*#+}} zmm2 = zmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
-; CHECK-NEXT: vpminud %zmm1, %zmm2, %zmm1
+; CHECK-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
+; CHECK-NEXT: movw $2570, %ax # imm = 0xA0A
+; CHECK-NEXT: kmovw %eax, %k1
+; CHECK-NEXT: vpblendmd %zmm1, %zmm0, %zmm2 {%k1}
+; CHECK-NEXT: vpminud %zmm2, %zmm1, %zmm1
; CHECK-NEXT: movw $-3856, %ax # imm = 0xF0F0
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpopcntd %zmm0, %zmm1 {%k1}
@@ -86,9 +88,11 @@ define <16 x i32> @combine_mask_with_umin(<16 x i32> %v0) {
define <16 x i32> @combine_mask_with_umax(<16 x i32> %v0) {
; CHECK-LABEL: combine_mask_with_umax:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
-; CHECK-NEXT: vpshufd {{.*#+}} zmm2 = zmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
-; CHECK-NEXT: vpmaxud %zmm1, %zmm2, %zmm1
+; CHECK-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
+; CHECK-NEXT: movw $2570, %ax # imm = 0xA0A
+; CHECK-NEXT: kmovw %eax, %k1
+; CHECK-NEXT: vpblendmd %zmm1, %zmm0, %zmm2 {%k1}
+; CHECK-NEXT: vpmaxud %zmm2, %zmm1, %zmm1
; CHECK-NEXT: movw $-3856, %ax # imm = 0xF0F0
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpopcntd %zmm0, %zmm1 {%k1}
@@ -105,9 +109,11 @@ define <16 x i32> @combine_mask_with_umax(<16 x i32> %v0) {
define <16 x i32> @combine_mask_with_smin(<16 x i32> %v0) {
; CHECK-LABEL: combine_mask_with_smin:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
-; CHECK-NEXT: vpshufd {{.*#+}} zmm2 = zmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
-; CHECK-NEXT: vpminsd %zmm1, %zmm2, %zmm1
+; CHECK-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
+; CHECK-NEXT: movw $2570, %ax # imm = 0xA0A
+; CHECK-NEXT: kmovw %eax, %k1
+; CHECK-NEXT: vpblendmd %zmm1, %zmm0, %zmm2 {%k1}
+; CHECK-NEXT: vpminsd %zmm2, %zmm1, %zmm1
; CHECK-NEXT: movw $-3856, %ax # imm = 0xF0F0
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpopcntd %zmm0, %zmm1 {%k1}
@@ -124,9 +130,11 @@ define <16 x i32> @combine_mask_with_smin(<16 x i32> %v0) {
define <16 x i32> @combine_mask_with_smax(<16 x i32> %v0) {
; CHECK-LABEL: combine_mask_with_smax:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
-; CHECK-NEXT: vpshufd {{.*#+}} zmm2 = zmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
-; CHECK-NEXT: vpmaxsd %zmm1, %zmm2, %zmm1
+; CHECK-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14]
+; CHECK-NEXT: movw $2570, %ax # imm = 0xA0A
+; CHECK-NEXT: kmovw %eax, %k1
+; CHECK-NEXT: vpblendmd %zmm1, %zmm0, %zmm2 {%k1}
+; CHECK-NEXT: vpmaxsd %zmm2, %zmm1, %zmm1
; CHECK-NEXT: movw $-3856, %ax # imm = 0xF0F0
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vpopcntd %zmm0, %zmm1 {%k1}
diff --git a/llvm/test/CodeGen/X86/known-never-zero.ll b/llvm/test/CodeGen/X86/known-never-zero.ll
index 910f1375ed1ca..93bcbd93e945f 100644
--- a/llvm/test/CodeGen/X86/known-never-zero.ll
+++ b/llvm/test/CodeGen/X86/known-never-zero.ll
@@ -813,7 +813,7 @@ define i32 @smin_maybe_zero(i32 %x, i32 %y) {
define i32 @smin_known_never_zero_vec_element(<4 x i32> %x) {
; X86-LABEL: smin_known_never_zero_vec_element:
; X86: # %bb.0:
-; X86-NEXT: movdqa {{.*#+}} xmm1 = [54,4294967273,12,1]
+; X86-NEXT: movdqa {{.*#+}} xmm1 = [u,4294967273,u,u]
; X86-NEXT: movdqa %xmm1, %xmm2
; X86-NEXT: pcmpgtd %xmm0, %xmm2
; X86-NEXT: pand %xmm2, %xmm0
@@ -951,7 +951,8 @@ define i32 @smax_known_zero(i32 %x, i32 %y) {
define i32 @smax_known_never_zero_vec_element(<4 x i32> %x) {
; X86-LABEL: smax_known_never_zero_vec_element:
; X86: # %bb.0:
-; X86-NEXT: movdqa {{.*#+}} xmm1 = [54,4294967273,4294967284,4294967295]
+; X86-NEXT: movl $54, %eax
+; X86-NEXT: movd %eax, %xmm1
; X86-NEXT: movdqa %xmm0, %xmm2
; X86-NEXT: pcmpgtd %xmm1, %xmm2
; X86-NEXT: pand %xmm2, %xmm0
@@ -963,7 +964,9 @@ define i32 @smax_known_never_zero_vec_element(<4 x i32> %x) {
;
; X64-LABEL: smax_known_never_zero_vec_element:
; X64: # %bb.0:
-; X64-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-NEXT: movl $54, %eax
+; X64-NEXT: vmovd %eax, %xmm1
+; X64-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
; X64-NEXT: vmovd %xmm0, %eax
; X64-NEXT: rep bsfl %eax, %eax
; X64-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/urem-seteq-vec-nonzero.ll b/llvm/test/CodeGen/X86/urem-seteq-vec-nonzero.ll
index 8042103dc08d0..fbc455ad44ab0 100644
--- a/llvm/test/CodeGen/X86/urem-seteq-vec-nonzero.ll
+++ b/llvm/test/CodeGen/X86/urem-seteq-vec-nonzero.ll
@@ -276,7 +276,7 @@ define <4 x i1> @t32_tautological(<4 x i32> %X) nounwind {
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [2863311531,2863311531,2863311531,2863311531]
-; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [4294967295,4294967295,4294967295,1431655764]
+; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [4294967295,u,u,1431655764]
; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1
diff --git a/llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll b/llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll
index e5b19a5efe6f2..4eb38b0358cf9 100644
--- a/llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll
+++ b/llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll
@@ -34,7 +34,7 @@ define <4 x i1> @t1_all_odd_eq(<4 x i32> %X) nounwind {
; CHECK-SSE41-LABEL: t1_all_odd_eq:
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [2863311531,2863311531,2863311531,2863311531]
-; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1431655765,4294967295,4294967295,4294967295]
+; CHECK-SSE41-NEXT: pmovzxdq {{.*#+}} xmm1 = [1431655765,4294967295]
; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1
@@ -85,7 +85,7 @@ define <4 x i1> @t1_all_odd_ne(<4 x i32> %X) nounwind {
; CHECK-SSE41-LABEL: t1_all_odd_ne:
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [2863311531,2863311531,2863311531,2863311531]
-; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1431655765,4294967295,4294967295,4294967295]
+; CHECK-SSE41-NEXT: pmovzxdq {{.*#+}} xmm1 = [1431655765,4294967295]
; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm1
@@ -140,7 +140,7 @@ define <8 x i1> @t2_narrow(<8 x i16> %X) nounwind {
; CHECK-SSE41-LABEL: t2_narrow:
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [43691,43691,43691,43691,43691,43691,43691,43691]
-; CHECK-SSE41-NEXT: pmovsxdq {{.*#+}} xmm1 = [18446744073709507925,18446744073709507925]
+; CHECK-SSE41-NEXT: pmovzxdq {{.*#+}} xmm1 = [4294923605,4294923605]
; CHECK-SSE41-NEXT: pminuw %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqw %xmm1, %xmm0
; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1
@@ -278,7 +278,9 @@ define <2 x i1> @t3_wide(<2 x i64> %X) nounwind {
; CHECK-AVX512VL-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsllq $32, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpaddq %xmm0, %xmm2, %xmm0
-; CHECK-AVX512VL-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; CHECK-AVX512VL-NEXT: movabsq $6148914691236517205, %rax # imm = 0x5555555555555555
+; CHECK-AVX512VL-NEXT: vmovq %rax, %xmm1
+; CHECK-AVX512VL-NEXT: vpminuq %xmm1, %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
; CHECK-AVX512VL-NEXT: retq
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