[llvm] [DAG] SimplifyDemandedVectorElts - add basic integer MIN/MAX handling (PR #195275)

[Simon Pilgrim via llvm-commits]

https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/195275

None

>From a96b1c6817a3f6e659fd6582bd4580a3372ecf34 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Fri, 1 May 2026 16:17:09 +0100
Subject: [PATCH] [DAG] SimplifyDemandedVectorElts - add basic integer MIN/MAX
 handling

---
 .../CodeGen/SelectionDAG/TargetLowering.cpp   | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 22f43145303b6..d2df8149312f3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -3856,6 +3856,27 @@ bool TargetLowering::SimplifyDemandedVectorElts(
         return true;
     break;
   }
+  case ISD::SMAX:
+  case ISD::SMIN:
+  case ISD::UMAX:
+  case ISD::UMIN: {
+    SDValue Op0 = Op.getOperand(0);
+    SDValue Op1 = Op.getOperand(1);
+
+    APInt SrcUndef, SrcZero;
+    if (SimplifyDemandedVectorElts(Op1, DemandedElts, SrcUndef, SrcZero, TLO,
+                                   Depth + 1))
+      return true;
+    if (SimplifyDemandedVectorElts(Op0, DemandedElts, SrcUndef, SrcZero, TLO,
+                                   Depth + 1))
+      return true;
+
+    // Attempt to avoid multi-use ops if we don't need anything from them.
+    if (!DemandedElts.isAllOnes())
+      if (SimplifyDemandedVectorEltsBinOp(Op0, Op1))
+        return true;
+    break;
+  }
   case ISD::TRUNCATE:
   case ISD::SIGN_EXTEND:
   case ISD::ZERO_EXTEND: