[llvm] [AArch64] SME definitions for C1-Ultra scheduling model (PR #194850)

[Asher Dobrescu via llvm-commits]

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Asher8118 wrote:

I think this test should also contain a `Load predicate` instruction. Additionally, the SWOG shows that load predicate instructions should have a latency of 5 when in streaming SVE mode.

https://github.com/llvm/llvm-project/pull/194850