[lldb] [llvm] [AArch64][llvm] Tighten SYSP parsing; don't disassemble invalid encodings (PR #182410)

[Jonathan Thackray via llvm-commits]

================
@@ -13,150 +13,154 @@
 // registers with 128-bit formats (op0, op1, Cn, Cm, op2)
 // For sysp, op0 is 0
 
-sysp #0, c2, c0, #0, x0, x1// TTBR0_EL1     3  0  2  0  0
-// CHECK-INST: sysp #0, c2, c0, #0, x0, x1
-// CHECK-ENCODING: encoding: [0x00,0x20,0x48,0xd5]
+sysp #0, c8, c0, #0, x0, x1
----------------
jthackray wrote:

Sure, I've added:
```
+sysp #0, c8, c7, #1, x8, x9
+// CHECK-INST: tlbip vae1, x8, x9
+// CHECK-ENCODING: encoding: [0x28,0x87,0x48,0xd5]
+// CHECK-UNKNOWN: d5488728 sysp #0, c8, c7, #1, x8, x9
```
(don't need the "instruction requires:" since it's a `SYSP` and therefore will always assemble)

https://github.com/llvm/llvm-project/pull/182410