[llvm] [CodeGen] Precompute untyped getMinimalPhysRegClass (PR #193438)

[Sander de Smalen via llvm-commits]

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@@ -1263,6 +1263,10 @@ void RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, raw_ostream &MainOS,
     OS << "  const TargetRegisterClass *getPhysRegBaseClass(MCRegister Reg) "
           "const override;\n";
   }
+  if (!RegisterClasses.empty()) {
+    OS << "  const TargetRegisterClass *getDefaultMinimalPhysRegClass("
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sdesmalen-arm wrote:

The downside for AMDGPU is that it now has two very similar maps. Can we fuse the two? i.e. if `BaseClassOrder` is set on the register classes then it will prioritise it based on that order, otherwise it will prioritise the minimal reg class using `hasSubClass`

https://github.com/llvm/llvm-project/pull/193438