[llvm] [X86] combineMinMaxReduction - match any minmax reduction to a legal scalar (PR #195261)
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Fri May 1 06:07:45 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: Simon Pilgrim (RKSimon)
<details>
<summary>Changes</summary>
Further relaxation of the VECREDUCE minmax folds - recognise any >=128-bit vector that reduces to a legal scalar.
Adds custom ops for more VECREDUCE types (inc vXi32/vXi64 types)
Remaining issues are sub-128-bit vector reductions (unnecessary padding with neutral elements) and handling of i64 types on 32-bit targets - I'm working on fixes for both of these.
---
Patch is 291.40 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/195261.diff
11 Files Affected:
- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+19-2)
- (modified) llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll (+12-12)
- (modified) llvm/test/CodeGen/X86/horizontal-reduce-smax.ll (+83-131)
- (modified) llvm/test/CodeGen/X86/horizontal-reduce-smin.ll (+82-130)
- (modified) llvm/test/CodeGen/X86/horizontal-reduce-umax.ll (+243-308)
- (modified) llvm/test/CodeGen/X86/horizontal-reduce-umin.ll (+244-310)
- (modified) llvm/test/CodeGen/X86/vector-extract-last-active.ll (+7-7)
- (modified) llvm/test/CodeGen/X86/vector-reduce-smax.ll (+325-381)
- (modified) llvm/test/CodeGen/X86/vector-reduce-smin.ll (+330-388)
- (modified) llvm/test/CodeGen/X86/vector-reduce-umax.ll (+511-578)
- (modified) llvm/test/CodeGen/X86/vector-reduce-umin.ll (+522-592)
``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 39e229fcedbbe..45c37e9c97584 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -1423,6 +1423,15 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Legal);
}
+ // Allow v4i32/v2i64 minmax reductions with SSE41 vector comparison,
+ // select and minmax handling.
+ for (auto VT : { MVT::v4i32, MVT::v2i64 }) {
+ setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom);
+ setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
+ setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom);
+ setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom);
+ }
+
// SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
setLoadExtAction(LoadExtOp, MVT::v8i16, MVT::v8i8, Legal);
@@ -1558,6 +1567,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
+ setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom);
+ setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
+ setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom);
+ setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom);
if (VT == MVT::v4i64) continue;
setOperationAction(ISD::ROTL, VT, Custom);
setOperationAction(ISD::ROTR, VT, Custom);
@@ -2030,6 +2043,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
+ setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom);
+ setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
+ setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom);
+ setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom);
// The condition codes aren't legal in SSE/AVX and under AVX512 we use
// setcc all the way to isel and prefer SETGT in some isel patterns.
@@ -47088,7 +47105,7 @@ static SDValue createPSADBW(SelectionDAG &DAG, SDValue N0, SDValue N1,
static SDValue combineMinMaxReduction(SDNode *Extract, SelectionDAG &DAG,
const X86Subtarget &Subtarget) {
EVT ExtractVT = Extract->getValueType(0);
- if (ExtractVT != MVT::i16 && ExtractVT != MVT::i8)
+ if (!DAG.getTargetLoweringInfo().isTypeLegal(ExtractVT))
return SDValue();
// Check for SMAX/SMIN/UMAX/UMIN horizontal reduction patterns.
@@ -47100,7 +47117,7 @@ static SDValue combineMinMaxReduction(SDNode *Extract, SelectionDAG &DAG,
EVT SrcVT = Src.getValueType();
EVT SrcSVT = SrcVT.getScalarType();
- if (SrcSVT != ExtractVT || (SrcVT.getSizeInBits() % 128) != 0)
+ if ((SrcVT.getSizeInBits() % 128) != 0)
return SDValue();
ISD::NodeType RdxOp;
diff --git a/llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
index 95ceb5fd56765..25632378cf23c 100644
--- a/llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
+++ b/llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
@@ -7939,7 +7939,7 @@ define i32 @test_mm512_reduce_max_epi32(<8 x i64> %__W) {
; CHECK-LABEL: test_mm512_reduce_max_epi32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; CHECK-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0
+; CHECK-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm1
; CHECK-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -7959,7 +7959,7 @@ define i32 @test_mm512_reduce_max_epu32(<8 x i64> %__W) {
; CHECK-LABEL: test_mm512_reduce_max_epu32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; CHECK-NEXT: vpmaxud %zmm1, %zmm0, %zmm0
+; CHECK-NEXT: vpmaxud %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm1
; CHECK-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -8016,7 +8016,7 @@ define i32 @test_mm512_reduce_min_epi32(<8 x i64> %__W) {
; CHECK-LABEL: test_mm512_reduce_min_epi32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; CHECK-NEXT: vpminsd %zmm1, %zmm0, %zmm0
+; CHECK-NEXT: vpminsd %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm1
; CHECK-NEXT: vpminsd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -8036,7 +8036,7 @@ define i32 @test_mm512_reduce_min_epu32(<8 x i64> %__W) {
; CHECK-LABEL: test_mm512_reduce_min_epu32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; CHECK-NEXT: vpminud %zmm1, %zmm0, %zmm0
+; CHECK-NEXT: vpminud %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm1
; CHECK-NEXT: vpminud %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -8097,7 +8097,7 @@ define i32 @test_mm512_mask_reduce_max_epi32(i16 zeroext %__M, <8 x i64> %__W) {
; X86-NEXT: vpbroadcastd {{.*#+}} zmm1 = [2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648]
; X86-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1}
; X86-NEXT: vextracti64x4 $1, %zmm1, %ymm0
-; X86-NEXT: vpmaxsd %zmm0, %zmm1, %zmm0
+; X86-NEXT: vpmaxsd %ymm0, %ymm1, %ymm0
; X86-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
; X86-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -8114,7 +8114,7 @@ define i32 @test_mm512_mask_reduce_max_epi32(i16 zeroext %__M, <8 x i64> %__W) {
; X64-NEXT: vpbroadcastd {{.*#+}} zmm1 = [2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648]
; X64-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1}
; X64-NEXT: vextracti64x4 $1, %zmm1, %ymm0
-; X64-NEXT: vpmaxsd %zmm0, %zmm1, %zmm0
+; X64-NEXT: vpmaxsd %ymm0, %ymm1, %ymm0
; X64-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -8139,7 +8139,7 @@ define i32 @test_mm512_mask_reduce_max_epu32(i16 zeroext %__M, <8 x i64> %__W) {
; X86-NEXT: kmovw %eax, %k1
; X86-NEXT: vmovdqa32 %zmm0, %zmm0 {%k1} {z}
; X86-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; X86-NEXT: vpmaxud %zmm1, %zmm0, %zmm0
+; X86-NEXT: vpmaxud %ymm1, %ymm0, %ymm0
; X86-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
; X86-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -8155,7 +8155,7 @@ define i32 @test_mm512_mask_reduce_max_epu32(i16 zeroext %__M, <8 x i64> %__W) {
; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vmovdqa32 %zmm0, %zmm0 {%k1} {z}
; X64-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; X64-NEXT: vpmaxud %zmm1, %zmm0, %zmm0
+; X64-NEXT: vpmaxud %ymm1, %ymm0, %ymm0
; X64-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -8227,7 +8227,7 @@ define i32 @test_mm512_mask_reduce_min_epi32(i16 zeroext %__M, <8 x i64> %__W) {
; X86-NEXT: vpbroadcastd {{.*#+}} zmm1 = [2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647]
; X86-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1}
; X86-NEXT: vextracti64x4 $1, %zmm1, %ymm0
-; X86-NEXT: vpminsd %zmm0, %zmm1, %zmm0
+; X86-NEXT: vpminsd %ymm0, %ymm1, %ymm0
; X86-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-NEXT: vpminsd %xmm1, %xmm0, %xmm0
; X86-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -8244,7 +8244,7 @@ define i32 @test_mm512_mask_reduce_min_epi32(i16 zeroext %__M, <8 x i64> %__W) {
; X64-NEXT: vpbroadcastd {{.*#+}} zmm1 = [2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647]
; X64-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1}
; X64-NEXT: vextracti64x4 $1, %zmm1, %ymm0
-; X64-NEXT: vpminsd %zmm0, %zmm1, %zmm0
+; X64-NEXT: vpminsd %ymm0, %ymm1, %ymm0
; X64-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-NEXT: vpminsd %xmm1, %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -8270,7 +8270,7 @@ define i32 @test_mm512_mask_reduce_min_epu32(i16 zeroext %__M, <8 x i64> %__W) {
; X86-NEXT: vpternlogd {{.*#+}} zmm1 = -1
; X86-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1}
; X86-NEXT: vextracti64x4 $1, %zmm1, %ymm0
-; X86-NEXT: vpminud %zmm0, %zmm1, %zmm0
+; X86-NEXT: vpminud %ymm0, %ymm1, %ymm0
; X86-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-NEXT: vpminud %xmm1, %xmm0, %xmm0
; X86-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -8287,7 +8287,7 @@ define i32 @test_mm512_mask_reduce_min_epu32(i16 zeroext %__M, <8 x i64> %__W) {
; X64-NEXT: vpternlogd {{.*#+}} zmm1 = -1
; X64-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1}
; X64-NEXT: vextracti64x4 $1, %zmm1, %ymm0
-; X64-NEXT: vpminud %zmm0, %zmm1, %zmm0
+; X64-NEXT: vpminud %ymm0, %ymm1, %ymm0
; X64-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-NEXT: vpminud %xmm1, %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
diff --git a/llvm/test/CodeGen/X86/horizontal-reduce-smax.ll b/llvm/test/CodeGen/X86/horizontal-reduce-smax.ll
index 93049f9987a5e..ebb5bc9069890 100644
--- a/llvm/test/CodeGen/X86/horizontal-reduce-smax.ll
+++ b/llvm/test/CodeGen/X86/horizontal-reduce-smax.ll
@@ -58,23 +58,11 @@ define i64 @test_reduce_v2i64(<2 x i64> %a0) {
;
; X64-SSE2-LABEL: test_reduce_v2i64:
; X64-SSE2: ## %bb.0:
-; X64-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X64-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
-; X64-SSE2-NEXT: movdqa %xmm0, %xmm3
-; X64-SSE2-NEXT: pxor %xmm2, %xmm3
-; X64-SSE2-NEXT: pxor %xmm1, %xmm2
-; X64-SSE2-NEXT: movdqa %xmm3, %xmm4
-; X64-SSE2-NEXT: pcmpgtd %xmm2, %xmm4
-; X64-SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
-; X64-SSE2-NEXT: pcmpeqd %xmm3, %xmm2
-; X64-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
-; X64-SSE2-NEXT: pand %xmm5, %xmm2
-; X64-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
-; X64-SSE2-NEXT: por %xmm2, %xmm3
-; X64-SSE2-NEXT: pand %xmm3, %xmm0
-; X64-SSE2-NEXT: pandn %xmm1, %xmm3
-; X64-SSE2-NEXT: por %xmm0, %xmm3
-; X64-SSE2-NEXT: movq %xmm3, %rax
+; X64-SSE2-NEXT: movq %xmm0, %rcx
+; X64-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
+; X64-SSE2-NEXT: movq %xmm0, %rax
+; X64-SSE2-NEXT: cmpq %rax, %rcx
+; X64-SSE2-NEXT: cmovgq %rcx, %rax
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v2i64:
@@ -116,13 +104,11 @@ define i32 @test_reduce_v4i32(<4 x i32> %a0) {
; X86-SSE2-NEXT: pand %xmm2, %xmm0
; X86-SSE2-NEXT: pandn %xmm1, %xmm2
; X86-SSE2-NEXT: por %xmm0, %xmm2
+; X86-SSE2-NEXT: movd %xmm2, %ecx
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,1,1]
-; X86-SSE2-NEXT: movdqa %xmm2, %xmm1
-; X86-SSE2-NEXT: pcmpgtd %xmm0, %xmm1
-; X86-SSE2-NEXT: pand %xmm1, %xmm2
-; X86-SSE2-NEXT: pandn %xmm0, %xmm1
-; X86-SSE2-NEXT: por %xmm2, %xmm1
-; X86-SSE2-NEXT: movd %xmm1, %eax
+; X86-SSE2-NEXT: movd %xmm0, %eax
+; X86-SSE2-NEXT: cmpl %eax, %ecx
+; X86-SSE2-NEXT: cmovgl %ecx, %eax
; X86-SSE2-NEXT: retl
;
; X86-SSE42-LABEL: test_reduce_v4i32:
@@ -151,13 +137,11 @@ define i32 @test_reduce_v4i32(<4 x i32> %a0) {
; X64-SSE2-NEXT: pand %xmm2, %xmm0
; X64-SSE2-NEXT: pandn %xmm1, %xmm2
; X64-SSE2-NEXT: por %xmm0, %xmm2
+; X64-SSE2-NEXT: movd %xmm2, %ecx
; X64-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,1,1]
-; X64-SSE2-NEXT: movdqa %xmm2, %xmm1
-; X64-SSE2-NEXT: pcmpgtd %xmm0, %xmm1
-; X64-SSE2-NEXT: pand %xmm1, %xmm2
-; X64-SSE2-NEXT: pandn %xmm0, %xmm1
-; X64-SSE2-NEXT: por %xmm2, %xmm1
-; X64-SSE2-NEXT: movd %xmm1, %eax
+; X64-SSE2-NEXT: movd %xmm0, %eax
+; X64-SSE2-NEXT: cmpl %eax, %ecx
+; X64-SSE2-NEXT: cmovgl %ecx, %eax
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v4i32:
@@ -495,35 +479,23 @@ define i64 @test_reduce_v4i64(<4 x i64> %a0) {
; X64-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
; X64-SSE2-NEXT: movdqa %xmm1, %xmm3
; X64-SSE2-NEXT: pxor %xmm2, %xmm3
-; X64-SSE2-NEXT: movdqa %xmm0, %xmm4
-; X64-SSE2-NEXT: pxor %xmm2, %xmm4
-; X64-SSE2-NEXT: movdqa %xmm4, %xmm5
-; X64-SSE2-NEXT: pcmpgtd %xmm3, %xmm5
-; X64-SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2]
-; X64-SSE2-NEXT: pcmpeqd %xmm3, %xmm4
-; X64-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
-; X64-SSE2-NEXT: pand %xmm6, %xmm3
-; X64-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3]
-; X64-SSE2-NEXT: por %xmm3, %xmm4
-; X64-SSE2-NEXT: pand %xmm4, %xmm0
-; X64-SSE2-NEXT: pandn %xmm1, %xmm4
-; X64-SSE2-NEXT: por %xmm0, %xmm4
-; X64-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm4[2,3,2,3]
-; X64-SSE2-NEXT: movdqa %xmm4, %xmm1
-; X64-SSE2-NEXT: pxor %xmm2, %xmm1
; X64-SSE2-NEXT: pxor %xmm0, %xmm2
-; X64-SSE2-NEXT: movdqa %xmm1, %xmm3
-; X64-SSE2-NEXT: pcmpgtd %xmm2, %xmm3
-; X64-SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm3[0,0,2,2]
-; X64-SSE2-NEXT: pcmpeqd %xmm1, %xmm2
-; X64-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
-; X64-SSE2-NEXT: pand %xmm5, %xmm1
-; X64-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,1,3,3]
-; X64-SSE2-NEXT: por %xmm1, %xmm2
-; X64-SSE2-NEXT: pand %xmm2, %xmm4
-; X64-SSE2-NEXT: pandn %xmm0, %xmm2
-; X64-SSE2-NEXT: por %xmm4, %xmm2
-; X64-SSE2-NEXT: movq %xmm2, %rax
+; X64-SSE2-NEXT: movdqa %xmm2, %xmm4
+; X64-SSE2-NEXT: pcmpgtd %xmm3, %xmm4
+; X64-SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
+; X64-SSE2-NEXT: pcmpeqd %xmm3, %xmm2
+; X64-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
+; X64-SSE2-NEXT: pand %xmm5, %xmm2
+; X64-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
+; X64-SSE2-NEXT: por %xmm2, %xmm3
+; X64-SSE2-NEXT: pand %xmm3, %xmm0
+; X64-SSE2-NEXT: pandn %xmm1, %xmm3
+; X64-SSE2-NEXT: por %xmm0, %xmm3
+; X64-SSE2-NEXT: movq %xmm3, %rcx
+; X64-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[2,3,2,3]
+; X64-SSE2-NEXT: movq %xmm0, %rax
+; X64-SSE2-NEXT: cmpq %rax, %rcx
+; X64-SSE2-NEXT: cmovgq %rcx, %rax
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v4i64:
@@ -595,13 +567,11 @@ define i32 @test_reduce_v8i32(<8 x i32> %a0) {
; X86-SSE2-NEXT: pand %xmm1, %xmm2
; X86-SSE2-NEXT: pandn %xmm0, %xmm1
; X86-SSE2-NEXT: por %xmm2, %xmm1
+; X86-SSE2-NEXT: movd %xmm1, %ecx
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
-; X86-SSE2-NEXT: movdqa %xmm1, %xmm2
-; X86-SSE2-NEXT: pcmpgtd %xmm0, %xmm2
-; X86-SSE2-NEXT: pand %xmm2, %xmm1
-; X86-SSE2-NEXT: pandn %xmm0, %xmm2
-; X86-SSE2-NEXT: por %xmm1, %xmm2
-; X86-SSE2-NEXT: movd %xmm2, %eax
+; X86-SSE2-NEXT: movd %xmm0, %eax
+; X86-SSE2-NEXT: cmpl %eax, %ecx
+; X86-SSE2-NEXT: cmovgl %ecx, %eax
; X86-SSE2-NEXT: retl
;
; X86-SSE42-LABEL: test_reduce_v8i32:
@@ -651,13 +621,11 @@ define i32 @test_reduce_v8i32(<8 x i32> %a0) {
; X64-SSE2-NEXT: pand %xmm1, %xmm2
; X64-SSE2-NEXT: pandn %xmm0, %xmm1
; X64-SSE2-NEXT: por %xmm2, %xmm1
+; X64-SSE2-NEXT: movd %xmm1, %ecx
; X64-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
-; X64-SSE2-NEXT: movdqa %xmm1, %xmm2
-; X64-SSE2-NEXT: pcmpgtd %xmm0, %xmm2
-; X64-SSE2-NEXT: pand %xmm2, %xmm1
-; X64-SSE2-NEXT: pandn %xmm0, %xmm2
-; X64-SSE2-NEXT: por %xmm1, %xmm2
-; X64-SSE2-NEXT: movd %xmm2, %eax
+; X64-SSE2-NEXT: movd %xmm0, %eax
+; X64-SSE2-NEXT: cmpl %eax, %ecx
+; X64-SSE2-NEXT: cmovgl %ecx, %eax
; X64-SSE2-NEXT: retq
;
; X64-SSE42-LABEL: test_reduce_v8i32:
@@ -1160,9 +1128,9 @@ define i64 @test_reduce_v8i64(<8 x i64> %a0) {
; X64-SSE2-LABEL: test_reduce_v8i64:
; X64-SSE2: ## %bb.0:
; X64-SSE2-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648]
-; X64-SSE2-NEXT: movdqa %xmm2, %xmm5
+; X64-SSE2-NEXT: movdqa %xmm3, %xmm5
; X64-SSE2-NEXT: pxor %xmm4, %xmm5
-; X64-SSE2-NEXT: movdqa %xmm0, %xmm6
+; X64-SSE2-NEXT: movdqa %xmm1, %xmm6
; X64-SSE2-NEXT: pxor %xmm4, %xmm6
; X64-SSE2-NEXT: movdqa %xmm6, %xmm7
; X64-SSE2-NEXT: pcmpgtd %xmm5, %xmm7
@@ -1172,55 +1140,43 @@ define i64 @test_reduce_v8i64(<8 x i64> %a0) {
; X64-SSE2-NEXT: pand %xmm8, %xmm6
; X64-SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm7[1,1,3,3]
; X64-SSE2-NEXT: por %xmm6, %xmm5
-; X64-SSE2-NEXT: pand %xmm5, %xmm0
-; X64-SSE2-NEXT: pandn %xmm2, %xmm5
-; X64-SSE2-NEXT: por %xmm0, %xmm5
-; X64-SSE2-NEXT: movdqa %xmm3, %xmm0
-; X64-SSE2-NEXT: pxor %xmm4, %xmm0
-; X64-SSE2-NEXT: movdqa %xmm1, %xmm2
-; X64-SSE2-NEXT: pxor %xmm4, %xmm2
-; X64-SSE2-NEXT: movdqa %xmm2, %xmm6
-; X64-SSE2-NEXT: pcmpgtd %xmm0, %xmm6
-; X64-SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
-; X64-SSE2-NEXT: pcmpeqd %xmm0, %xmm2
-; X64-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3]
-; X64-SSE2-NEXT: pand %xmm7, %xmm0
-; X64-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm6[1,1,3,3]
-; X64-SSE2-NEXT: por %xmm0, %xmm2
-; X64-SSE2-NEXT: pand %xmm2, %xmm1
-; X64-SSE2-NEXT: pandn %xmm3, %xmm2
-; X64-SSE2-NEXT: por %xmm1, %xmm2
-; X64-SSE2-NEXT: movdqa %xmm2, %xmm0
-; X64-SSE2-NEXT: pxor %xmm4, %xmm0
+; X64-SSE2-NEXT: pand %xmm5, %xmm1
+; X64-SSE2-NEXT: pandn %xmm3, %xmm5
+; X64-SSE2-NEXT: por %xmm1, %xmm5
; X64-SSE2-NEXT: movdqa %xmm5, %xmm1
; X64-SSE2-NEXT: pxor %xmm4, %xmm1
-; X64-SSE2-NEXT: movdqa %xmm1, %xmm3
-; X64-SSE2-NEXT: pcmpgtd %xmm0, %xmm3
-; X64-SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm3[0,0,2,2]
-; X64-SSE2-NEXT: pcmpeqd %xmm0, %xmm1
-; X64-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3]
-; X64-SSE2-NEXT: pand %xmm6, %xmm0
-; X64-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,1,3,3]
-; X64-SSE2-NEXT: por %xmm0, %xmm1
-; X64-SSE2-NEXT: pand %xmm1, %xmm5
-; X64-SSE2-NEXT: pandn %xmm2, %xmm1
-; X64-SSE2-NEXT: por %xmm5, %xmm1
-; X64-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
-; X64-SSE2-NEXT: movdqa %xmm1, %xmm2
-; X64-SSE2-NEXT: pxor %xmm4, %xmm2
-; X64-SSE2-NEXT: pxor %xmm0, %xmm4
; X64-SSE2-NEXT: movdqa %xmm2, %xmm3
-; X64-SSE2-NEXT: pcmpgtd %xmm4, %xmm3
-; X64-SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm3[0,0,2,2]
-; X64-SSE2-NEXT: pcmpeqd %xmm2, %xmm4
-; X64-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,1,3,3]
-; X64-SSE2-NEXT: pand %xmm5, %xmm2
-; X64-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
-; X64-SSE2-NEXT: por %xmm2, %xmm3
-; X64-SSE2-NEXT: pand %xmm3, %xmm1
-; X64-SSE2-NEXT: pandn %xmm0, %xmm3
-; X64-SSE2-NEXT: por %xmm1, %xmm3
-; X64-SSE2-NEXT: movq %xmm3, %rax
+; X64-SSE2-NEXT: pxor %xmm4, %xmm3
+; X64-SSE2-NEXT: movdqa %xmm0, %xmm6
+; X64-SSE2-NEXT: pxor %xmm4, %xmm6
+; X64-SSE2-NEXT: movdqa %xmm6, %xmm7
+; X64-SSE2-NEXT: pcmpgtd %xmm3, %xmm7
+; X64-SSE2-NEXT: pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2]
+; X64-SSE2-NEXT: pcmpeqd %xmm3, %xmm6
+; X64-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm6[1,1,3,3]
+; X64-SSE2-NEXT: pand %xmm8, %xmm3
+; X64-SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm7[1,1,3,3]
+; X64-SSE2-NEXT: por %xmm3, %xmm6
+; X64-SSE2-NEXT: pand %xmm6, %xmm0
+; X64-SSE2-NEXT: pandn %xmm2, %xmm6
+; X64-SSE2-NEXT: por %xmm0, %xmm6
+; X64-SSE2-NEXT: pxor %xmm6, %xmm4
+; X64-SSE2-NEXT: movdqa %xmm4, %xmm0
+; X64-SSE2-NEXT: pcmpgtd %xmm1, %xmm0
+; X64-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,0,2,2]
+; X64-SSE2-NEXT: pcmpeqd %xmm1, %xmm4
+; X64-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm4[1,1,3,3]
+; X64-SSE2-NEXT: pand %xmm2, %xmm1
+; X64-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; X64-SSE2-NEXT: por %xmm1, %xmm0
+; X64-SSE2-NEXT: pand %xmm0, %xmm6
+; X64-SSE2-NEXT: pandn %xmm5, %xmm0
+; X64-SSE2-NEXT: por %xmm6, %xmm0
+; X64-SSE2-NEXT: movq %xmm0, %rcx
+; X64-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/195261
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