[llvm] [AMDGPU] Implement getAddrSpaceCastPreservedPtrMask (PR #182658)
via llvm-commits
llvm-commits at lists.llvm.org
Fri May 1 07:11:55 PDT 2026
https://github.com/addmisol updated https://github.com/llvm/llvm-project/pull/182658
>From 4d6d66cdca969e30332247f5cfb6c647f710f434 Mon Sep 17 00:00:00 2001
From: addmisol <addmsolution at gmail.com>
Date: Sat, 21 Feb 2026 12:13:56 +0530
Subject: [PATCH 01/13] [AMDGPU] Implement getAddrSpaceCastPreservedPtrMask
---
.../Target/AMDGPU/AMDGPUTargetTransformInfo.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
index 3ec157aacd0aa..3710b53c551cf 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
@@ -205,6 +205,24 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
return AMDGPUAS::FLAT_ADDRESS;
}
+ APInt getAddrSpaceCastPreservedPtrMask(unsigned SrcAS,
+ unsigned DstAS) const override {
+ // Only handle casts from flat (generic) address space.
+ if (SrcAS != AMDGPUAS::FLAT_ADDRESS)
+ return BaseT::getAddrSpaceCastPreservedPtrMask(SrcAS, DstAS);
+
+ // Handle casts to local or global address spaces.
+ if (DstAS != AMDGPUAS::LOCAL_ADDRESS && DstAS != AMDGPUAS::GLOBAL_ADDRESS)
+ return BaseT::getAddrSpaceCastPreservedPtrMask(SrcAS, DstAS);
+
+ // The aperture for local memory is 2^32 bytes in size and aligned to 2^32.
+ // Address changes within the lower 32 bits do not change the address space
+ // aperture, so it's safe to cast back to the original address space.
+ // For global, addresses in flat and global address spaces are the same.
+ unsigned FlatPtrSize = DL.getPointerSizeInBits(AMDGPUAS::FLAT_ADDRESS);
+ return APInt::getLowBitsSet(FlatPtrSize, 32);
+ }
+
bool collectFlatAddressOperands(SmallVectorImpl<int> &OpIndexes,
Intrinsic::ID IID) const override;
>From 5d6df4eacc4a4870e0fae06f07313a3e3c6977b5 Mon Sep 17 00:00:00 2001
From: addmisol <addmsolution at gmail.com>
Date: Sat, 21 Feb 2026 12:16:00 +0530
Subject: [PATCH 02/13] Create int2ptr.ll
---
.../InferAddressSpaces/AMDGPU/int2ptr.ll | 243 ++++++++++++++++++
1 file changed, 243 insertions(+)
create mode 100644 llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll
diff --git a/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll
new file mode 100644
index 0000000000000..5bd2503994756
--- /dev/null
+++ b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll
@@ -0,0 +1,243 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=infer-address-spaces %s | FileCheck %s
+
+; Test that address space inference works correctly for inttoptr/ptrtoint
+; patterns when the pointer manipulation is within the preserved mask.
+; AMDGPU uses 2^32-aligned apertures for local memory, so modifications
+; to the lower 32 bits are safe.
+
+; Local (shared) memory tests - addrspace(3)
+
+define void @test_xor_local(ptr addrspace(3) %sp) {
+; CHECK-LABEL: define void @test_xor_local(
+; CHECK-SAME: ptr addrspace(3) [[SP:%.*]]) {
+; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(3) [[SP]] to ptr
+; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
+; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], 4095
+; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
+; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(3)
+; CHECK-NEXT: store i16 0, ptr addrspace(3) [[TMP1]], align 2
+; CHECK-NEXT: ret void
+;
+ %gp = addrspacecast ptr addrspace(3) %sp to ptr
+ %a = ptrtoint ptr %gp to i64
+ %b = xor i64 %a, 4095
+ %gp2 = inttoptr i64 %b to ptr
+ store i16 0, ptr %gp2, align 2
+ ret void
+}
+
+define void @test_xor_local_max32bit(ptr addrspace(3) %sp) {
+; CHECK-LABEL: define void @test_xor_local_max32bit(
+; CHECK-SAME: ptr addrspace(3) [[SP:%.*]]) {
+; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(3) [[SP]] to ptr
+; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
+; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], 4294967295
+; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
+; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(3)
+; CHECK-NEXT: store i16 0, ptr addrspace(3) [[TMP1]], align 2
+; CHECK-NEXT: ret void
+;
+ %gp = addrspacecast ptr addrspace(3) %sp to ptr
+ %a = ptrtoint ptr %gp to i64
+ ; 0xFFFFFFFF - maximum 32-bit value, should still be optimized
+ %b = xor i64 %a, 4294967295
+ %gp2 = inttoptr i64 %b to ptr
+ store i16 0, ptr %gp2, align 2
+ ret void
+}
+
+define void @test_xor_local_fail_bit33(ptr addrspace(3) %sp) {
+; CHECK-LABEL: define void @test_xor_local_fail_bit33(
+; CHECK-SAME: ptr addrspace(3) [[SP:%.*]]) {
+; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(3) [[SP]] to ptr
+; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
+; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], 4294967296
+; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
+; CHECK-NEXT: store i16 0, ptr [[GP2]], align 2
+; CHECK-NEXT: ret void
+;
+ %gp = addrspacecast ptr addrspace(3) %sp to ptr
+ %a = ptrtoint ptr %gp to i64
+ ; 0x100000000 - bit 32 set, should NOT be optimized
+ %b = xor i64 %a, 4294967296
+ %gp2 = inttoptr i64 %b to ptr
+ store i16 0, ptr %gp2, align 2
+ ret void
+}
+
+define void @test_or_local(ptr addrspace(3) %sp) {
+; CHECK-LABEL: define void @test_or_local(
+; CHECK-SAME: ptr addrspace(3) [[SP:%.*]]) {
+; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(3) [[SP]] to ptr
+; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
+; CHECK-NEXT: [[B:%.*]] = or i64 [[A]], 255
+; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
+; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(3)
+; CHECK-NEXT: store i16 0, ptr addrspace(3) [[TMP1]], align 2
+; CHECK-NEXT: ret void
+;
+ %gp = addrspacecast ptr addrspace(3) %sp to ptr
+ %a = ptrtoint ptr %gp to i64
+ %b = or i64 %a, 255
+ %gp2 = inttoptr i64 %b to ptr
+ store i16 0, ptr %gp2, align 2
+ ret void
+}
+
+define void @test_and_local(ptr addrspace(3) %sp) {
+; CHECK-LABEL: define void @test_and_local(
+; CHECK-SAME: ptr addrspace(3) [[SP:%.*]]) {
+; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(3) [[SP]] to ptr
+; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
+; CHECK-NEXT: [[B:%.*]] = and i64 [[A]], -4096
+; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
+; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(3)
+; CHECK-NEXT: store i16 0, ptr addrspace(3) [[TMP1]], align 2
+; CHECK-NEXT: ret void
+;
+ %gp = addrspacecast ptr addrspace(3) %sp to ptr
+ %a = ptrtoint ptr %gp to i64
+ ; -4096 = 0xFFFFFFFFFFFFF000 - clears low 12 bits, should be optimized
+ %b = and i64 %a, -4096
+ %gp2 = inttoptr i64 %b to ptr
+ store i16 0, ptr %gp2, align 2
+ ret void
+}
+
+define void @test_and_local_fail(ptr addrspace(3) %sp) {
+; CHECK-LABEL: define void @test_and_local_fail(
+; CHECK-SAME: ptr addrspace(3) [[SP:%.*]]) {
+; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(3) [[SP]] to ptr
+; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
+; CHECK-NEXT: [[B:%.*]] = and i64 [[A]], -4294967297
+; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
+; CHECK-NEXT: store i16 0, ptr [[GP2]], align 2
+; CHECK-NEXT: ret void
+;
+ %gp = addrspacecast ptr addrspace(3) %sp to ptr
+ %a = ptrtoint ptr %gp to i64
+ ; -4294967297 = 0xFFFFFFFEFFFFFFFF - clears bit 32, should NOT be optimized
+ %b = and i64 %a, -4294967297
+ %gp2 = inttoptr i64 %b to ptr
+ store i16 0, ptr %gp2, align 2
+ ret void
+}
+
+; Global memory tests - addrspace(1)
+
+define void @test_xor_global(ptr addrspace(1) %sp) {
+; CHECK-LABEL: define void @test_xor_global(
+; CHECK-SAME: ptr addrspace(1) [[SP:%.*]]) {
+; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(1) [[SP]] to ptr
+; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
+; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], 7
+; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
+; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(1)
+; CHECK-NEXT: store i16 0, ptr addrspace(1) [[TMP1]], align 2
+; CHECK-NEXT: ret void
+;
+ %gp = addrspacecast ptr addrspace(1) %sp to ptr
+ %a = ptrtoint ptr %gp to i64
+ %b = xor i64 %a, 7
+ %gp2 = inttoptr i64 %b to ptr
+ store i16 0, ptr %gp2, align 2
+ ret void
+}
+
+define void @test_xor_global_max32bit(ptr addrspace(1) %sp) {
+; CHECK-LABEL: define void @test_xor_global_max32bit(
+; CHECK-SAME: ptr addrspace(1) [[SP:%.*]]) {
+; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(1) [[SP]] to ptr
+; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
+; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], 4294967295
+; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
+; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(1)
+; CHECK-NEXT: store i16 0, ptr addrspace(1) [[TMP1]], align 2
+; CHECK-NEXT: ret void
+;
+ %gp = addrspacecast ptr addrspace(1) %sp to ptr
+ %a = ptrtoint ptr %gp to i64
+ ; 0xFFFFFFFF - maximum 32-bit value, should still be optimized
+ %b = xor i64 %a, 4294967295
+ %gp2 = inttoptr i64 %b to ptr
+ store i16 0, ptr %gp2, align 2
+ ret void
+}
+
+define void @test_xor_global_fail_bit33(ptr addrspace(1) %sp) {
+; CHECK-LABEL: define void @test_xor_global_fail_bit33(
+; CHECK-SAME: ptr addrspace(1) [[SP:%.*]]) {
+; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(1) [[SP]] to ptr
+; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
+; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], 4294967296
+; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
+; CHECK-NEXT: store i16 0, ptr [[GP2]], align 2
+; CHECK-NEXT: ret void
+;
+ %gp = addrspacecast ptr addrspace(1) %sp to ptr
+ %a = ptrtoint ptr %gp to i64
+ ; 0x100000000 - bit 32 set, should NOT be optimized
+ %b = xor i64 %a, 4294967296
+ %gp2 = inttoptr i64 %b to ptr
+ store i16 0, ptr %gp2, align 2
+ ret void
+}
+
+; Private memory tests - addrspace(5)
+; Private address space is NOT handled, so these should NOT be optimized
+
+define void @test_xor_private(ptr addrspace(5) %sp) {
+; CHECK-LABEL: define void @test_xor_private(
+; CHECK-SAME: ptr addrspace(5) [[SP:%.*]]) {
+; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(5) [[SP]] to ptr
+; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
+; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], 7
+; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
+; CHECK-NEXT: store i16 0, ptr [[GP2]], align 2
+; CHECK-NEXT: ret void
+;
+ %gp = addrspacecast ptr addrspace(5) %sp to ptr
+ %a = ptrtoint ptr %gp to i64
+ %b = xor i64 %a, 7
+ %gp2 = inttoptr i64 %b to ptr
+ store i16 0, ptr %gp2, align 2
+ ret void
+}
+
+; Complex swizzling pattern - similar to NVPTX test3
+
+define void @test_swizzle_local(ptr addrspace(3) %sp) {
+; CHECK-LABEL: define void @test_swizzle_local(
+; CHECK-SAME: ptr addrspace(3) [[SP:%.*]]) {
+; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(3) [[SP]] to ptr
+; CHECK-NEXT: [[T1:%.*]] = ptrtoint ptr [[GP]] to i64
+; CHECK-NEXT: [[AND:%.*]] = lshr i64 [[T1]], 8
+; CHECK-NEXT: [[SHR:%.*]] = and i64 [[AND]], 8
+; CHECK-NEXT: [[AND1:%.*]] = lshr i64 [[T1]], 10
+; CHECK-NEXT: [[SHR2:%.*]] = and i64 [[AND1]], 4
+; CHECK-NEXT: [[OR:%.*]] = or i64 [[SHR]], [[SHR2]]
+; CHECK-NEXT: [[AND3:%.*]] = lshr i64 [[T1]], 4
+; CHECK-NEXT: [[SHR4:%.*]] = and i64 [[AND3]], 112
+; CHECK-NEXT: [[OR5:%.*]] = or i64 [[OR]], [[SHR4]]
+; CHECK-NEXT: [[XOR:%.*]] = xor i64 [[OR5]], [[T1]]
+; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[XOR]] to ptr
+; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(3)
+; CHECK-NEXT: store i16 0, ptr addrspace(3) [[TMP1]], align 2
+; CHECK-NEXT: ret void
+;
+ %gp = addrspacecast ptr addrspace(3) %sp to ptr
+ %t1 = ptrtoint ptr %gp to i64
+ %and = lshr i64 %t1, 8
+ %shr = and i64 %and, 8
+ %and1 = lshr i64 %t1, 10
+ %shr2 = and i64 %and1, 4
+ %or = or i64 %shr, %shr2
+ %and3 = lshr i64 %t1, 4
+ %shr4 = and i64 %and3, 112
+ %or5 = or i64 %or, %shr4
+ %xor = xor i64 %or5, %t1
+ %gp2 = inttoptr i64 %xor to ptr
+ store i16 0, ptr %gp2, align 2
+ ret void
+}
>From e35a5f29e425c931a343e865f0a240995b330761 Mon Sep 17 00:00:00 2001
From: addmisol <218448340+addmisol at users.noreply.github.com>
Date: Mon, 23 Feb 2026 10:30:26 +0530
Subject: [PATCH 03/13] Correction for global address space
Correction for global address space
---
.../Target/AMDGPU/AMDGPUTargetTransformInfo.h | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
index 3710b53c551cf..ec1ef0889e9a3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
@@ -211,16 +211,20 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
if (SrcAS != AMDGPUAS::FLAT_ADDRESS)
return BaseT::getAddrSpaceCastPreservedPtrMask(SrcAS, DstAS);
- // Handle casts to local or global address spaces.
- if (DstAS != AMDGPUAS::LOCAL_ADDRESS && DstAS != AMDGPUAS::GLOBAL_ADDRESS)
- return BaseT::getAddrSpaceCastPreservedPtrMask(SrcAS, DstAS);
+ unsigned FlatPtrSize = DL.getPointerSizeInBits(AMDGPUAS::FLAT_ADDRESS);
+
+ // For global, addresses in flat and global address spaces are the same.
+ // All 64 bits are preserved.
+ if (DstAS == AMDGPUAS::GLOBAL_ADDRESS)
+ return APInt::getAllOnes(FlatPtrSize);
// The aperture for local memory is 2^32 bytes in size and aligned to 2^32.
// Address changes within the lower 32 bits do not change the address space
// aperture, so it's safe to cast back to the original address space.
- // For global, addresses in flat and global address spaces are the same.
- unsigned FlatPtrSize = DL.getPointerSizeInBits(AMDGPUAS::FLAT_ADDRESS);
- return APInt::getLowBitsSet(FlatPtrSize, 32);
+ if (DstAS == AMDGPUAS::LOCAL_ADDRESS)
+ return APInt::getLowBitsSet(FlatPtrSize, 32);
+
+ return BaseT::getAddrSpaceCastPreservedPtrMask(SrcAS, DstAS);
}
bool collectFlatAddressOperands(SmallVectorImpl<int> &OpIndexes,
>From 77b8720d3f66f11d54247bc653149a2bf7ae88d4 Mon Sep 17 00:00:00 2001
From: addmisol <218448340+addmisol at users.noreply.github.com>
Date: Mon, 23 Feb 2026 10:32:43 +0530
Subject: [PATCH 04/13] Update int2ptr.ll
---
.../InferAddressSpaces/AMDGPU/int2ptr.ll | 35 +++++++++++++++----
1 file changed, 29 insertions(+), 6 deletions(-)
diff --git a/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll
index 5bd2503994756..efeb0965ad471 100644
--- a/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll
+++ b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll
@@ -3,8 +3,10 @@
; Test that address space inference works correctly for inttoptr/ptrtoint
; patterns when the pointer manipulation is within the preserved mask.
-; AMDGPU uses 2^32-aligned apertures for local memory, so modifications
-; to the lower 32 bits are safe.
+; For local memory, AMDGPU uses 2^32-aligned apertures, so only the lower
+; 32 bits are safe to modify.
+; For global memory, flat and global addresses are identical, so all 64
+; bits are preserved.
; Local (shared) memory tests - addrspace(3)
@@ -165,25 +167,46 @@ define void @test_xor_global_max32bit(ptr addrspace(1) %sp) {
ret void
}
-define void @test_xor_global_fail_bit33(ptr addrspace(1) %sp) {
-; CHECK-LABEL: define void @test_xor_global_fail_bit33(
+define void @test_xor_global_bit33(ptr addrspace(1) %sp) {
+; CHECK-LABEL: define void @test_xor_global_bit33(
; CHECK-SAME: ptr addrspace(1) [[SP:%.*]]) {
; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(1) [[SP]] to ptr
; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], 4294967296
; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
-; CHECK-NEXT: store i16 0, ptr [[GP2]], align 2
+; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(1)
+; CHECK-NEXT: store i16 0, ptr addrspace(1) [[TMP1]], align 2
; CHECK-NEXT: ret void
;
%gp = addrspacecast ptr addrspace(1) %sp to ptr
%a = ptrtoint ptr %gp to i64
- ; 0x100000000 - bit 32 set, should NOT be optimized
+ ; 0x100000000 - bit 32 set, should be optimized for global (all 64 bits preserved)
%b = xor i64 %a, 4294967296
%gp2 = inttoptr i64 %b to ptr
store i16 0, ptr %gp2, align 2
ret void
}
+define void @test_xor_global_high_bits(ptr addrspace(1) %sp) {
+; CHECK-LABEL: define void @test_xor_global_high_bits(
+; CHECK-SAME: ptr addrspace(1) [[SP:%.*]]) {
+; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(1) [[SP]] to ptr
+; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
+; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], -9223372036854775808
+; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
+; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(1)
+; CHECK-NEXT: store i16 0, ptr addrspace(1) [[TMP1]], align 2
+; CHECK-NEXT: ret void
+;
+ %gp = addrspacecast ptr addrspace(1) %sp to ptr
+ %a = ptrtoint ptr %gp to i64
+ ; 0x8000000000000000 - bit 63 set, should be optimized for global
+ %b = xor i64 %a, -9223372036854775808
+ %gp2 = inttoptr i64 %b to ptr
+ store i16 0, ptr %gp2, align 2
+ ret void
+}
+
; Private memory tests - addrspace(5)
; Private address space is NOT handled, so these should NOT be optimized
>From e66b6c8deeaa9851f889d9cad5903504c1132c5f Mon Sep 17 00:00:00 2001
From: Addmisol <addmisol9 at gmail.com>
Date: Sun, 26 Apr 2026 01:53:42 +0530
Subject: [PATCH 05/13] Update AMDGPUTargetTransformInfo.h
---
llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
index 040e25016a043..4f3765535ed0e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
@@ -215,8 +215,10 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
unsigned FlatPtrSize = DL.getPointerSizeInBits(AMDGPUAS::FLAT_ADDRESS);
- // For global, addresses in flat and global address spaces are the same.
- // All 64 bits are preserved.
+ // For global, addresses in flat and global address spaces are the same -
+ // no conversion is needed. Global memory regions are architecturally
+ // separate from the private/local aperture regions (which are 2^32-aligned
+ // and use specific high-address ranges), so all 64 bits are preserved.
if (DstAS == AMDGPUAS::GLOBAL_ADDRESS)
return APInt::getAllOnes(FlatPtrSize);
>From 483b0df47f2ae5c5379fe6a8e59f2848e3cc351b Mon Sep 17 00:00:00 2001
From: Addmisol <addmisol9 at gmail.com>
Date: Sun, 26 Apr 2026 01:54:17 +0530
Subject: [PATCH 06/13] Update int2ptr.ll
---
.../InferAddressSpaces/AMDGPU/int2ptr.ll | 159 +++++++++++++++++-
1 file changed, 155 insertions(+), 4 deletions(-)
diff --git a/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll
index efeb0965ad471..b228a43854582 100644
--- a/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll
+++ b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll
@@ -49,8 +49,9 @@ define void @test_xor_local_max32bit(ptr addrspace(3) %sp) {
ret void
}
-define void @test_xor_local_fail_bit33(ptr addrspace(3) %sp) {
-; CHECK-LABEL: define void @test_xor_local_fail_bit33(
+; 0x100000000 tests bit 32 (0-indexed), not bit 33
+define void @test_xor_local_fail_bit32(ptr addrspace(3) %sp) {
+; CHECK-LABEL: define void @test_xor_local_fail_bit32(
; CHECK-SAME: ptr addrspace(3) [[SP:%.*]]) {
; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(3) [[SP]] to ptr
; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
@@ -167,8 +168,13 @@ define void @test_xor_global_max32bit(ptr addrspace(1) %sp) {
ret void
}
-define void @test_xor_global_bit33(ptr addrspace(1) %sp) {
-; CHECK-LABEL: define void @test_xor_global_bit33(
+; For global address space, all 64 bits are preserved because global addresses
+; are bit-identical in both global and flat address spaces. Global memory regions
+; are architecturally separate from the private/local aperture regions, which use
+; specific high-address ranges that don't overlap with valid global addresses.
+; 0x100000000 tests bit 32 (0-indexed), not bit 33
+define void @test_xor_global_bit32(ptr addrspace(1) %sp) {
+; CHECK-LABEL: define void @test_xor_global_bit32(
; CHECK-SAME: ptr addrspace(1) [[SP:%.*]]) {
; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(1) [[SP]] to ptr
; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
@@ -207,6 +213,68 @@ define void @test_xor_global_high_bits(ptr addrspace(1) %sp) {
ret void
}
+; Test OR on global (all 64 bits preserved)
+define void @test_or_global(ptr addrspace(1) %sp) {
+; CHECK-LABEL: define void @test_or_global(
+; CHECK-SAME: ptr addrspace(1) [[SP:%.*]]) {
+; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(1) [[SP]] to ptr
+; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
+; CHECK-NEXT: [[B:%.*]] = or i64 [[A]], 255
+; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
+; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(1)
+; CHECK-NEXT: store i16 0, ptr addrspace(1) [[TMP1]], align 2
+; CHECK-NEXT: ret void
+;
+ %gp = addrspacecast ptr addrspace(1) %sp to ptr
+ %a = ptrtoint ptr %gp to i64
+ %b = or i64 %a, 255
+ %gp2 = inttoptr i64 %b to ptr
+ store i16 0, ptr %gp2, align 2
+ ret void
+}
+
+; Test AND on global (all 64 bits preserved, even when clearing high bits)
+define void @test_and_global(ptr addrspace(1) %sp) {
+; CHECK-LABEL: define void @test_and_global(
+; CHECK-SAME: ptr addrspace(1) [[SP:%.*]]) {
+; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(1) [[SP]] to ptr
+; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
+; CHECK-NEXT: [[B:%.*]] = and i64 [[A]], 281474976710655
+; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
+; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(1)
+; CHECK-NEXT: store i16 0, ptr addrspace(1) [[TMP1]], align 2
+; CHECK-NEXT: ret void
+;
+ %gp = addrspacecast ptr addrspace(1) %sp to ptr
+ %a = ptrtoint ptr %gp to i64
+ ; 0x0000FFFFFFFFFFFF - clears upper 16 bits, should still optimize for global
+ %b = and i64 %a, 281474976710655
+ %gp2 = inttoptr i64 %b to ptr
+ store i16 0, ptr %gp2, align 2
+ ret void
+}
+
+; Test ADD on global - ADD is not currently tracked by InferAddressSpaces
+; so this will NOT be optimized (even though it could be safe for global)
+define void @test_add_global(ptr addrspace(1) %sp) {
+; CHECK-LABEL: define void @test_add_global(
+; CHECK-SAME: ptr addrspace(1) [[SP:%.*]]) {
+; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(1) [[SP]] to ptr
+; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
+; CHECK-NEXT: [[B:%.*]] = add i64 [[A]], 4294967296
+; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
+; CHECK-NEXT: store i16 0, ptr [[GP2]], align 2
+; CHECK-NEXT: ret void
+;
+ %gp = addrspacecast ptr addrspace(1) %sp to ptr
+ %a = ptrtoint ptr %gp to i64
+ ; ADD is not tracked - this will NOT be optimized
+ %b = add i64 %a, 4294967296
+ %gp2 = inttoptr i64 %b to ptr
+ store i16 0, ptr %gp2, align 2
+ ret void
+}
+
; Private memory tests - addrspace(5)
; Private address space is NOT handled, so these should NOT be optimized
@@ -228,6 +296,89 @@ define void @test_xor_private(ptr addrspace(5) %sp) {
ret void
}
+; Region memory tests - addrspace(2)
+; Region address space is NOT handled, so these should NOT be optimized
+
+define void @test_xor_region(ptr addrspace(2) %sp) {
+; CHECK-LABEL: define void @test_xor_region(
+; CHECK-SAME: ptr addrspace(2) [[SP:%.*]]) {
+; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(2) [[SP]] to ptr
+; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
+; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], 7
+; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
+; CHECK-NEXT: store i16 0, ptr [[GP2]], align 2
+; CHECK-NEXT: ret void
+;
+ %gp = addrspacecast ptr addrspace(2) %sp to ptr
+ %a = ptrtoint ptr %gp to i64
+ %b = xor i64 %a, 7
+ %gp2 = inttoptr i64 %b to ptr
+ store i16 0, ptr %gp2, align 2
+ ret void
+}
+
+; Constant memory tests - addrspace(4)
+; Constant address space is NOT handled, so these should NOT be optimized
+
+define void @test_xor_constant(ptr addrspace(4) %sp) {
+; CHECK-LABEL: define void @test_xor_constant(
+; CHECK-SAME: ptr addrspace(4) [[SP:%.*]]) {
+; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(4) [[SP]] to ptr
+; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
+; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], 7
+; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
+; CHECK-NEXT: [[VAL:%.*]] = load i16, ptr [[GP2]], align 2
+; CHECK-NEXT: ret void
+;
+ %gp = addrspacecast ptr addrspace(4) %sp to ptr
+ %a = ptrtoint ptr %gp to i64
+ %b = xor i64 %a, 7
+ %gp2 = inttoptr i64 %b to ptr
+ %val = load i16, ptr %gp2, align 2
+ ret void
+}
+
+; Test ADD operation on local - ADD is not currently tracked by InferAddressSpaces
+; so this will NOT be optimized (limitation of the pass, not the mask)
+define void @test_add_local(ptr addrspace(3) %sp) {
+; CHECK-LABEL: define void @test_add_local(
+; CHECK-SAME: ptr addrspace(3) [[SP:%.*]]) {
+; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(3) [[SP]] to ptr
+; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
+; CHECK-NEXT: [[B:%.*]] = add i64 [[A]], 64
+; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
+; CHECK-NEXT: store i16 0, ptr [[GP2]], align 2
+; CHECK-NEXT: ret void
+;
+ %gp = addrspacecast ptr addrspace(3) %sp to ptr
+ %a = ptrtoint ptr %gp to i64
+ ; ADD is not tracked - this will NOT be optimized
+ %b = add i64 %a, 64
+ %gp2 = inttoptr i64 %b to ptr
+ store i16 0, ptr %gp2, align 2
+ ret void
+}
+
+; Test SUB operation on local - SUB is not currently tracked by InferAddressSpaces
+define void @test_sub_local(ptr addrspace(3) %sp) {
+; CHECK-LABEL: define void @test_sub_local(
+; CHECK-SAME: ptr addrspace(3) [[SP:%.*]]) {
+; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(3) [[SP]] to ptr
+; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
+; CHECK-NEXT: [[B:%.*]] = sub i64 [[A]], 128
+; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
+; CHECK-NEXT: store i16 0, ptr [[GP2]], align 2
+; CHECK-NEXT: ret void
+;
+ %gp = addrspacecast ptr addrspace(3) %sp to ptr
+ %a = ptrtoint ptr %gp to i64
+ ; SUB is not tracked - this will NOT be optimized
+ %b = sub i64 %a, 128
+ %gp2 = inttoptr i64 %b to ptr
+ store i16 0, ptr %gp2, align 2
+ ret void
+}
+
; Complex swizzling pattern - similar to NVPTX test3
define void @test_swizzle_local(ptr addrspace(3) %sp) {
>From fb573b35806772f3027a50a12795300fc5f4821d Mon Sep 17 00:00:00 2001
From: Addmisol <addmisol9 at gmail.com>
Date: Tue, 28 Apr 2026 23:07:19 +0530
Subject: [PATCH 07/13] Update AMDGPUTargetTransformInfo.h
---
.../Target/AMDGPU/AMDGPUTargetTransformInfo.h | 27 ++++++++++++-------
1 file changed, 18 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
index 4f3765535ed0e..b3cfc3a5f2659 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
@@ -215,17 +215,26 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
unsigned FlatPtrSize = DL.getPointerSizeInBits(AMDGPUAS::FLAT_ADDRESS);
- // For global, addresses in flat and global address spaces are the same -
- // no conversion is needed. Global memory regions are architecturally
- // separate from the private/local aperture regions (which are 2^32-aligned
- // and use specific high-address ranges), so all 64 bits are preserved.
- if (DstAS == AMDGPUAS::GLOBAL_ADDRESS)
+ // For global and constant, addresses in flat and global/constant address
+ // spaces are the same - no conversion is needed. Global memory regions are
+ // architecturally separate from the private/local aperture regions (which
+ // are 2^32-aligned and use specific high-address ranges), so all 64 bits
+ // are preserved.
+ if (DstAS == AMDGPUAS::GLOBAL_ADDRESS ||
+ DstAS == AMDGPUAS::CONSTANT_ADDRESS)
return APInt::getAllOnes(FlatPtrSize);
- // The aperture for local memory is 2^32 bytes in size and aligned to 2^32.
- // Address changes within the lower 32 bits do not change the address space
- // aperture, so it's safe to cast back to the original address space.
- if (DstAS == AMDGPUAS::LOCAL_ADDRESS)
+ // The apertures for local and private memory are 2^32 bytes in size and
+ // aligned to 2^32. Address changes within the lower 32 bits do not change
+ // the address space aperture, so it's safe to cast back to the original
+ // address space.
+ if (DstAS == AMDGPUAS::LOCAL_ADDRESS ||
+ DstAS == AMDGPUAS::PRIVATE_ADDRESS)
+ return APInt::getLowBitsSet(FlatPtrSize, 32);
+
+ // Constant 32-bit address space uses 32-bit pointers, but mask must match
+ // the flat pointer size for the pass to work correctly.
+ if (DstAS == AMDGPUAS::CONSTANT_ADDRESS_32BIT)
return APInt::getLowBitsSet(FlatPtrSize, 32);
return BaseT::getAddrSpaceCastPreservedPtrMask(SrcAS, DstAS);
>From 9edd921ebe4b54569c1b285cd984535541c8a82f Mon Sep 17 00:00:00 2001
From: Addmisol <addmisol9 at gmail.com>
Date: Tue, 28 Apr 2026 23:08:43 +0530
Subject: [PATCH 08/13] Update int2ptr.ll
---
.../InferAddressSpaces/AMDGPU/int2ptr.ll | 154 +++++++++++++++++-
1 file changed, 150 insertions(+), 4 deletions(-)
diff --git a/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll
index b228a43854582..565b80043ab9d 100644
--- a/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll
+++ b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll
@@ -276,7 +276,7 @@ define void @test_add_global(ptr addrspace(1) %sp) {
}
; Private memory tests - addrspace(5)
-; Private address space is NOT handled, so these should NOT be optimized
+; Private aperture is 2^32-aligned, lower 32 bits are safe to modify
define void @test_xor_private(ptr addrspace(5) %sp) {
; CHECK-LABEL: define void @test_xor_private(
@@ -285,7 +285,8 @@ define void @test_xor_private(ptr addrspace(5) %sp) {
; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], 7
; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
-; CHECK-NEXT: store i16 0, ptr [[GP2]], align 2
+; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(5)
+; CHECK-NEXT: store i16 0, ptr addrspace(5) [[TMP1]], align 2
; CHECK-NEXT: ret void
;
%gp = addrspacecast ptr addrspace(5) %sp to ptr
@@ -296,6 +297,45 @@ define void @test_xor_private(ptr addrspace(5) %sp) {
ret void
}
+define void @test_xor_private_max32bit(ptr addrspace(5) %sp) {
+; CHECK-LABEL: define void @test_xor_private_max32bit(
+; CHECK-SAME: ptr addrspace(5) [[SP:%.*]]) {
+; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(5) [[SP]] to ptr
+; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
+; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], 4294967295
+; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
+; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(5)
+; CHECK-NEXT: store i16 0, ptr addrspace(5) [[TMP1]], align 2
+; CHECK-NEXT: ret void
+;
+ %gp = addrspacecast ptr addrspace(5) %sp to ptr
+ %a = ptrtoint ptr %gp to i64
+ ; 0xFFFFFFFF - maximum 32-bit value, should still be optimized
+ %b = xor i64 %a, 4294967295
+ %gp2 = inttoptr i64 %b to ptr
+ store i16 0, ptr %gp2, align 2
+ ret void
+}
+
+define void @test_xor_private_fail_bit32(ptr addrspace(5) %sp) {
+; CHECK-LABEL: define void @test_xor_private_fail_bit32(
+; CHECK-SAME: ptr addrspace(5) [[SP:%.*]]) {
+; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(5) [[SP]] to ptr
+; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
+; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], 4294967296
+; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
+; CHECK-NEXT: store i16 0, ptr [[GP2]], align 2
+; CHECK-NEXT: ret void
+;
+ %gp = addrspacecast ptr addrspace(5) %sp to ptr
+ %a = ptrtoint ptr %gp to i64
+ ; 0x100000000 - bit 32 set, should NOT be optimized
+ %b = xor i64 %a, 4294967296
+ %gp2 = inttoptr i64 %b to ptr
+ store i16 0, ptr %gp2, align 2
+ ret void
+}
+
; Region memory tests - addrspace(2)
; Region address space is NOT handled, so these should NOT be optimized
@@ -318,7 +358,7 @@ define void @test_xor_region(ptr addrspace(2) %sp) {
}
; Constant memory tests - addrspace(4)
-; Constant address space is NOT handled, so these should NOT be optimized
+; Constant address space uses same addresses as global, all 64 bits preserved
define void @test_xor_constant(ptr addrspace(4) %sp) {
; CHECK-LABEL: define void @test_xor_constant(
@@ -327,7 +367,8 @@ define void @test_xor_constant(ptr addrspace(4) %sp) {
; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], 7
; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
-; CHECK-NEXT: [[VAL:%.*]] = load i16, ptr [[GP2]], align 2
+; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(4)
+; CHECK-NEXT: [[VAL:%.*]] = load i16, ptr addrspace(4) [[TMP1]], align 2
; CHECK-NEXT: ret void
;
%gp = addrspacecast ptr addrspace(4) %sp to ptr
@@ -338,6 +379,26 @@ define void @test_xor_constant(ptr addrspace(4) %sp) {
ret void
}
+define void @test_xor_constant_high_bits(ptr addrspace(4) %sp) {
+; CHECK-LABEL: define void @test_xor_constant_high_bits(
+; CHECK-SAME: ptr addrspace(4) [[SP:%.*]]) {
+; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(4) [[SP]] to ptr
+; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
+; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], -9223372036854775808
+; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
+; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(4)
+; CHECK-NEXT: [[VAL:%.*]] = load i16, ptr addrspace(4) [[TMP1]], align 2
+; CHECK-NEXT: ret void
+;
+ %gp = addrspacecast ptr addrspace(4) %sp to ptr
+ %a = ptrtoint ptr %gp to i64
+ ; 0x8000000000000000 - bit 63 set, should be optimized for constant
+ %b = xor i64 %a, -9223372036854775808
+ %gp2 = inttoptr i64 %b to ptr
+ %val = load i16, ptr %gp2, align 2
+ ret void
+}
+
; Test ADD operation on local - ADD is not currently tracked by InferAddressSpaces
; so this will NOT be optimized (limitation of the pass, not the mask)
define void @test_add_local(ptr addrspace(3) %sp) {
@@ -415,3 +476,88 @@ define void @test_swizzle_local(ptr addrspace(3) %sp) {
store i16 0, ptr %gp2, align 2
ret void
}
+
+; Constant 32-bit memory tests - addrspace(6)
+; Uses 32-bit pointers, all 32 bits preserved
+
+define void @test_xor_constant_32bit(ptr addrspace(6) %sp) {
+; CHECK-LABEL: define void @test_xor_constant_32bit(
+; CHECK-SAME: ptr addrspace(6) [[SP:%.*]]) {
+; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(6) [[SP]] to ptr
+; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
+; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], 7
+; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
+; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(6)
+; CHECK-NEXT: [[VAL:%.*]] = load i16, ptr addrspace(6) [[TMP1]], align 2
+; CHECK-NEXT: ret void
+;
+ %gp = addrspacecast ptr addrspace(6) %sp to ptr
+ %a = ptrtoint ptr %gp to i64
+ %b = xor i64 %a, 7
+ %gp2 = inttoptr i64 %b to ptr
+ %val = load i16, ptr %gp2, align 2
+ ret void
+}
+
+; Vector pointer tests - vectors are NOT currently optimized by InferAddressSpaces
+
+define void @test_xor_local_vector(<2 x ptr addrspace(3)> %sp) {
+; CHECK-LABEL: define void @test_xor_local_vector(
+; CHECK-SAME: <2 x ptr addrspace(3)> [[SP:%.*]]) {
+; CHECK-NEXT: [[GP:%.*]] = addrspacecast <2 x ptr addrspace(3)> [[SP]] to <2 x ptr>
+; CHECK-NEXT: [[A:%.*]] = ptrtoint <2 x ptr> [[GP]] to <2 x i64>
+; CHECK-NEXT: [[B:%.*]] = xor <2 x i64> [[A]], splat (i64 4095)
+; CHECK-NEXT: [[GP2:%.*]] = inttoptr <2 x i64> [[B]] to <2 x ptr>
+; CHECK-NEXT: [[EL0:%.*]] = extractelement <2 x ptr> [[GP2]], i32 0
+; CHECK-NEXT: store i16 0, ptr [[EL0]], align 2
+; CHECK-NEXT: ret void
+;
+ %gp = addrspacecast <2 x ptr addrspace(3)> %sp to <2 x ptr>
+ %a = ptrtoint <2 x ptr> %gp to <2 x i64>
+ %b = xor <2 x i64> %a, splat (i64 4095)
+ %gp2 = inttoptr <2 x i64> %b to <2 x ptr>
+ %el0 = extractelement <2 x ptr> %gp2, i32 0
+ store i16 0, ptr %el0, align 2
+ ret void
+}
+
+define void @test_xor_global_vector(<2 x ptr addrspace(1)> %sp) {
+; CHECK-LABEL: define void @test_xor_global_vector(
+; CHECK-SAME: <2 x ptr addrspace(1)> [[SP:%.*]]) {
+; CHECK-NEXT: [[GP:%.*]] = addrspacecast <2 x ptr addrspace(1)> [[SP]] to <2 x ptr>
+; CHECK-NEXT: [[A:%.*]] = ptrtoint <2 x ptr> [[GP]] to <2 x i64>
+; CHECK-NEXT: [[B:%.*]] = xor <2 x i64> [[A]], splat (i64 4294967296)
+; CHECK-NEXT: [[GP2:%.*]] = inttoptr <2 x i64> [[B]] to <2 x ptr>
+; CHECK-NEXT: [[EL0:%.*]] = extractelement <2 x ptr> [[GP2]], i32 0
+; CHECK-NEXT: store i16 0, ptr [[EL0]], align 2
+; CHECK-NEXT: ret void
+;
+ %gp = addrspacecast <2 x ptr addrspace(1)> %sp to <2 x ptr>
+ %a = ptrtoint <2 x ptr> %gp to <2 x i64>
+ ; Vector case - not currently optimized by InferAddressSpaces
+ %b = xor <2 x i64> %a, splat (i64 4294967296)
+ %gp2 = inttoptr <2 x i64> %b to <2 x ptr>
+ %el0 = extractelement <2 x ptr> %gp2, i32 0
+ store i16 0, ptr %el0, align 2
+ ret void
+}
+
+define void @test_xor_private_vector(<2 x ptr addrspace(5)> %sp) {
+; CHECK-LABEL: define void @test_xor_private_vector(
+; CHECK-SAME: <2 x ptr addrspace(5)> [[SP:%.*]]) {
+; CHECK-NEXT: [[GP:%.*]] = addrspacecast <2 x ptr addrspace(5)> [[SP]] to <2 x ptr>
+; CHECK-NEXT: [[A:%.*]] = ptrtoint <2 x ptr> [[GP]] to <2 x i64>
+; CHECK-NEXT: [[B:%.*]] = xor <2 x i64> [[A]], splat (i64 255)
+; CHECK-NEXT: [[GP2:%.*]] = inttoptr <2 x i64> [[B]] to <2 x ptr>
+; CHECK-NEXT: [[EL0:%.*]] = extractelement <2 x ptr> [[GP2]], i32 0
+; CHECK-NEXT: store i16 0, ptr [[EL0]], align 2
+; CHECK-NEXT: ret void
+;
+ %gp = addrspacecast <2 x ptr addrspace(5)> %sp to <2 x ptr>
+ %a = ptrtoint <2 x ptr> %gp to <2 x i64>
+ %b = xor <2 x i64> %a, splat (i64 255)
+ %gp2 = inttoptr <2 x i64> %b to <2 x ptr>
+ %el0 = extractelement <2 x ptr> %gp2, i32 0
+ store i16 0, ptr %el0, align 2
+ ret void
+}
>From 9f821abc01ebe87c10976833b67351b53a21bfbb Mon Sep 17 00:00:00 2001
From: Addmisol <addmisol9 at gmail.com>
Date: Fri, 1 May 2026 16:13:15 +0530
Subject: [PATCH 09/13] Update int2ptr.ll
---
.../InferAddressSpaces/AMDGPU/int2ptr.ll | 21 -------------------
1 file changed, 21 deletions(-)
diff --git a/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll
index 565b80043ab9d..0a487ed694147 100644
--- a/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll
+++ b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll
@@ -336,27 +336,6 @@ define void @test_xor_private_fail_bit32(ptr addrspace(5) %sp) {
ret void
}
-; Region memory tests - addrspace(2)
-; Region address space is NOT handled, so these should NOT be optimized
-
-define void @test_xor_region(ptr addrspace(2) %sp) {
-; CHECK-LABEL: define void @test_xor_region(
-; CHECK-SAME: ptr addrspace(2) [[SP:%.*]]) {
-; CHECK-NEXT: [[GP:%.*]] = addrspacecast ptr addrspace(2) [[SP]] to ptr
-; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
-; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], 7
-; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
-; CHECK-NEXT: store i16 0, ptr [[GP2]], align 2
-; CHECK-NEXT: ret void
-;
- %gp = addrspacecast ptr addrspace(2) %sp to ptr
- %a = ptrtoint ptr %gp to i64
- %b = xor i64 %a, 7
- %gp2 = inttoptr i64 %b to ptr
- store i16 0, ptr %gp2, align 2
- ret void
-}
-
; Constant memory tests - addrspace(4)
; Constant address space uses same addresses as global, all 64 bits preserved
>From 5bf9a6d263ffad03d3cd72af764d34e84b705743 Mon Sep 17 00:00:00 2001
From: Addmisol <addmisol9 at gmail.com>
Date: Fri, 1 May 2026 16:41:32 +0530
Subject: [PATCH 10/13] Update int2ptr.ll
---
llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll
index 0a487ed694147..09c00fae77b5f 100644
--- a/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll
+++ b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll
@@ -419,8 +419,7 @@ define void @test_sub_local(ptr addrspace(3) %sp) {
ret void
}
-; Complex swizzling pattern - similar to NVPTX test3
-
+; Complex swizzling pattern
define void @test_swizzle_local(ptr addrspace(3) %sp) {
; CHECK-LABEL: define void @test_swizzle_local(
; CHECK-SAME: ptr addrspace(3) [[SP:%.*]]) {
>From 608f8aaacac8981bef2afc1409861f554d2ef04b Mon Sep 17 00:00:00 2001
From: Addmisol <addmisol9 at gmail.com>
Date: Fri, 1 May 2026 18:50:45 +0530
Subject: [PATCH 11/13] Update AMDGPUTargetTransformInfo.h
---
llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
index b3cfc3a5f2659..ff3a14ccb5c3c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
@@ -228,8 +228,7 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
// aligned to 2^32. Address changes within the lower 32 bits do not change
// the address space aperture, so it's safe to cast back to the original
// address space.
- if (DstAS == AMDGPUAS::LOCAL_ADDRESS ||
- DstAS == AMDGPUAS::PRIVATE_ADDRESS)
+ if (DstAS == AMDGPUAS::LOCAL_ADDRESS || DstAS == AMDGPUAS::PRIVATE_ADDRESS)
return APInt::getLowBitsSet(FlatPtrSize, 32);
// Constant 32-bit address space uses 32-bit pointers, but mask must match
>From affd36ffe989868053b894942d8bf98bc497200b Mon Sep 17 00:00:00 2001
From: Addmisol <addmisol9 at gmail.com>
Date: Fri, 1 May 2026 19:40:55 +0530
Subject: [PATCH 12/13] Update AMDGPUTargetTransformInfo.h
---
.../Target/AMDGPU/AMDGPUTargetTransformInfo.h | 32 -------------------
1 file changed, 32 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
index ff3a14ccb5c3c..e49881dee57db 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
@@ -207,38 +207,6 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
return AMDGPUAS::FLAT_ADDRESS;
}
- APInt getAddrSpaceCastPreservedPtrMask(unsigned SrcAS,
- unsigned DstAS) const override {
- // Only handle casts from flat (generic) address space.
- if (SrcAS != AMDGPUAS::FLAT_ADDRESS)
- return BaseT::getAddrSpaceCastPreservedPtrMask(SrcAS, DstAS);
-
- unsigned FlatPtrSize = DL.getPointerSizeInBits(AMDGPUAS::FLAT_ADDRESS);
-
- // For global and constant, addresses in flat and global/constant address
- // spaces are the same - no conversion is needed. Global memory regions are
- // architecturally separate from the private/local aperture regions (which
- // are 2^32-aligned and use specific high-address ranges), so all 64 bits
- // are preserved.
- if (DstAS == AMDGPUAS::GLOBAL_ADDRESS ||
- DstAS == AMDGPUAS::CONSTANT_ADDRESS)
- return APInt::getAllOnes(FlatPtrSize);
-
- // The apertures for local and private memory are 2^32 bytes in size and
- // aligned to 2^32. Address changes within the lower 32 bits do not change
- // the address space aperture, so it's safe to cast back to the original
- // address space.
- if (DstAS == AMDGPUAS::LOCAL_ADDRESS || DstAS == AMDGPUAS::PRIVATE_ADDRESS)
- return APInt::getLowBitsSet(FlatPtrSize, 32);
-
- // Constant 32-bit address space uses 32-bit pointers, but mask must match
- // the flat pointer size for the pass to work correctly.
- if (DstAS == AMDGPUAS::CONSTANT_ADDRESS_32BIT)
- return APInt::getLowBitsSet(FlatPtrSize, 32);
-
- return BaseT::getAddrSpaceCastPreservedPtrMask(SrcAS, DstAS);
- }
-
bool collectFlatAddressOperands(SmallVectorImpl<int> &OpIndexes,
Intrinsic::ID IID) const override;
>From e8149d71a7601f4ee600e5922f35d8e358ef6296 Mon Sep 17 00:00:00 2001
From: Addmisol <addmisol9 at gmail.com>
Date: Fri, 1 May 2026 19:41:39 +0530
Subject: [PATCH 13/13] Update int2ptr.ll
---
.../InferAddressSpaces/AMDGPU/int2ptr.ll | 48 +++++++------------
1 file changed, 16 insertions(+), 32 deletions(-)
diff --git a/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll
index 09c00fae77b5f..6b6d8162b6e7b 100644
--- a/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll
+++ b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/int2ptr.ll
@@ -17,8 +17,7 @@ define void @test_xor_local(ptr addrspace(3) %sp) {
; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], 4095
; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
-; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(3)
-; CHECK-NEXT: store i16 0, ptr addrspace(3) [[TMP1]], align 2
+; CHECK-NEXT: store i16 0, ptr [[GP2]], align 2
; CHECK-NEXT: ret void
;
%gp = addrspacecast ptr addrspace(3) %sp to ptr
@@ -36,8 +35,7 @@ define void @test_xor_local_max32bit(ptr addrspace(3) %sp) {
; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], 4294967295
; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
-; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(3)
-; CHECK-NEXT: store i16 0, ptr addrspace(3) [[TMP1]], align 2
+; CHECK-NEXT: store i16 0, ptr [[GP2]], align 2
; CHECK-NEXT: ret void
;
%gp = addrspacecast ptr addrspace(3) %sp to ptr
@@ -76,8 +74,7 @@ define void @test_or_local(ptr addrspace(3) %sp) {
; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
; CHECK-NEXT: [[B:%.*]] = or i64 [[A]], 255
; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
-; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(3)
-; CHECK-NEXT: store i16 0, ptr addrspace(3) [[TMP1]], align 2
+; CHECK-NEXT: store i16 0, ptr [[GP2]], align 2
; CHECK-NEXT: ret void
;
%gp = addrspacecast ptr addrspace(3) %sp to ptr
@@ -95,8 +92,7 @@ define void @test_and_local(ptr addrspace(3) %sp) {
; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
; CHECK-NEXT: [[B:%.*]] = and i64 [[A]], -4096
; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
-; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(3)
-; CHECK-NEXT: store i16 0, ptr addrspace(3) [[TMP1]], align 2
+; CHECK-NEXT: store i16 0, ptr [[GP2]], align 2
; CHECK-NEXT: ret void
;
%gp = addrspacecast ptr addrspace(3) %sp to ptr
@@ -136,8 +132,7 @@ define void @test_xor_global(ptr addrspace(1) %sp) {
; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], 7
; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
-; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(1)
-; CHECK-NEXT: store i16 0, ptr addrspace(1) [[TMP1]], align 2
+; CHECK-NEXT: store i16 0, ptr [[GP2]], align 2
; CHECK-NEXT: ret void
;
%gp = addrspacecast ptr addrspace(1) %sp to ptr
@@ -155,8 +150,7 @@ define void @test_xor_global_max32bit(ptr addrspace(1) %sp) {
; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], 4294967295
; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
-; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(1)
-; CHECK-NEXT: store i16 0, ptr addrspace(1) [[TMP1]], align 2
+; CHECK-NEXT: store i16 0, ptr [[GP2]], align 2
; CHECK-NEXT: ret void
;
%gp = addrspacecast ptr addrspace(1) %sp to ptr
@@ -180,8 +174,7 @@ define void @test_xor_global_bit32(ptr addrspace(1) %sp) {
; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], 4294967296
; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
-; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(1)
-; CHECK-NEXT: store i16 0, ptr addrspace(1) [[TMP1]], align 2
+; CHECK-NEXT: store i16 0, ptr [[GP2]], align 2
; CHECK-NEXT: ret void
;
%gp = addrspacecast ptr addrspace(1) %sp to ptr
@@ -200,8 +193,7 @@ define void @test_xor_global_high_bits(ptr addrspace(1) %sp) {
; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], -9223372036854775808
; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
-; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(1)
-; CHECK-NEXT: store i16 0, ptr addrspace(1) [[TMP1]], align 2
+; CHECK-NEXT: store i16 0, ptr [[GP2]], align 2
; CHECK-NEXT: ret void
;
%gp = addrspacecast ptr addrspace(1) %sp to ptr
@@ -221,8 +213,7 @@ define void @test_or_global(ptr addrspace(1) %sp) {
; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
; CHECK-NEXT: [[B:%.*]] = or i64 [[A]], 255
; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
-; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(1)
-; CHECK-NEXT: store i16 0, ptr addrspace(1) [[TMP1]], align 2
+; CHECK-NEXT: store i16 0, ptr [[GP2]], align 2
; CHECK-NEXT: ret void
;
%gp = addrspacecast ptr addrspace(1) %sp to ptr
@@ -241,8 +232,7 @@ define void @test_and_global(ptr addrspace(1) %sp) {
; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
; CHECK-NEXT: [[B:%.*]] = and i64 [[A]], 281474976710655
; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
-; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(1)
-; CHECK-NEXT: store i16 0, ptr addrspace(1) [[TMP1]], align 2
+; CHECK-NEXT: store i16 0, ptr [[GP2]], align 2
; CHECK-NEXT: ret void
;
%gp = addrspacecast ptr addrspace(1) %sp to ptr
@@ -285,8 +275,7 @@ define void @test_xor_private(ptr addrspace(5) %sp) {
; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], 7
; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
-; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(5)
-; CHECK-NEXT: store i16 0, ptr addrspace(5) [[TMP1]], align 2
+; CHECK-NEXT: store i16 0, ptr [[GP2]], align 2
; CHECK-NEXT: ret void
;
%gp = addrspacecast ptr addrspace(5) %sp to ptr
@@ -304,8 +293,7 @@ define void @test_xor_private_max32bit(ptr addrspace(5) %sp) {
; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], 4294967295
; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
-; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(5)
-; CHECK-NEXT: store i16 0, ptr addrspace(5) [[TMP1]], align 2
+; CHECK-NEXT: store i16 0, ptr [[GP2]], align 2
; CHECK-NEXT: ret void
;
%gp = addrspacecast ptr addrspace(5) %sp to ptr
@@ -346,8 +334,7 @@ define void @test_xor_constant(ptr addrspace(4) %sp) {
; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], 7
; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
-; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(4)
-; CHECK-NEXT: [[VAL:%.*]] = load i16, ptr addrspace(4) [[TMP1]], align 2
+; CHECK-NEXT: [[VAL:%.*]] = load i16, ptr [[GP2]], align 2
; CHECK-NEXT: ret void
;
%gp = addrspacecast ptr addrspace(4) %sp to ptr
@@ -365,8 +352,7 @@ define void @test_xor_constant_high_bits(ptr addrspace(4) %sp) {
; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], -9223372036854775808
; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
-; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(4)
-; CHECK-NEXT: [[VAL:%.*]] = load i16, ptr addrspace(4) [[TMP1]], align 2
+; CHECK-NEXT: [[VAL:%.*]] = load i16, ptr [[GP2]], align 2
; CHECK-NEXT: ret void
;
%gp = addrspacecast ptr addrspace(4) %sp to ptr
@@ -435,8 +421,7 @@ define void @test_swizzle_local(ptr addrspace(3) %sp) {
; CHECK-NEXT: [[OR5:%.*]] = or i64 [[OR]], [[SHR4]]
; CHECK-NEXT: [[XOR:%.*]] = xor i64 [[OR5]], [[T1]]
; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[XOR]] to ptr
-; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(3)
-; CHECK-NEXT: store i16 0, ptr addrspace(3) [[TMP1]], align 2
+; CHECK-NEXT: store i16 0, ptr [[GP2]], align 2
; CHECK-NEXT: ret void
;
%gp = addrspacecast ptr addrspace(3) %sp to ptr
@@ -465,8 +450,7 @@ define void @test_xor_constant_32bit(ptr addrspace(6) %sp) {
; CHECK-NEXT: [[A:%.*]] = ptrtoint ptr [[GP]] to i64
; CHECK-NEXT: [[B:%.*]] = xor i64 [[A]], 7
; CHECK-NEXT: [[GP2:%.*]] = inttoptr i64 [[B]] to ptr
-; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[GP2]] to ptr addrspace(6)
-; CHECK-NEXT: [[VAL:%.*]] = load i16, ptr addrspace(6) [[TMP1]], align 2
+; CHECK-NEXT: [[VAL:%.*]] = load i16, ptr [[GP2]], align 2
; CHECK-NEXT: ret void
;
%gp = addrspacecast ptr addrspace(6) %sp to ptr
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