[llvm] [X86] combineMinMaxReduction - match any minmax reduction to a legal scalar (PR #195261)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/X86/X86ISelLowering.cpp --diff_from_common_commit
``````````

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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 45c37e9c9..744d5654f 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -1425,7 +1425,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
 
     // Allow v4i32/v2i64 minmax reductions with SSE41 vector comparison,
     // select and minmax handling.
-    for (auto VT : { MVT::v4i32, MVT::v2i64 }) {
+    for (auto VT : {MVT::v4i32, MVT::v2i64}) {
       setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom);
       setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
       setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom);
@@ -1567,10 +1567,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
       setOperationAction(ISD::VECREDUCE_AND,   VT, Custom);
       setOperationAction(ISD::VECREDUCE_OR,    VT, Custom);
       setOperationAction(ISD::VECREDUCE_XOR,   VT, Custom);
-      setOperationAction(ISD::VECREDUCE_SMAX,  VT, Custom);
-      setOperationAction(ISD::VECREDUCE_SMIN,  VT, Custom);
-      setOperationAction(ISD::VECREDUCE_UMAX,  VT, Custom);
-      setOperationAction(ISD::VECREDUCE_UMIN,  VT, Custom);
+      setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom);
+      setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
+      setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom);
+      setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom);
       if (VT == MVT::v4i64) continue;
       setOperationAction(ISD::ROTL,            VT, Custom);
       setOperationAction(ISD::ROTR,            VT, Custom);
@@ -2043,10 +2043,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
       setOperationAction(ISD::VECREDUCE_AND,    VT, Custom);
       setOperationAction(ISD::VECREDUCE_OR,     VT, Custom);
       setOperationAction(ISD::VECREDUCE_XOR,    VT, Custom);
-      setOperationAction(ISD::VECREDUCE_SMAX,   VT, Custom);
-      setOperationAction(ISD::VECREDUCE_SMIN,   VT, Custom);
-      setOperationAction(ISD::VECREDUCE_UMAX,   VT, Custom);
-      setOperationAction(ISD::VECREDUCE_UMIN,   VT, Custom);
+      setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom);
+      setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
+      setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom);
+      setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom);
 
       // The condition codes aren't legal in SSE/AVX and under AVX512 we use
       // setcc all the way to isel and prefer SETGT in some isel patterns.

``````````

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https://github.com/llvm/llvm-project/pull/195261