[llvm] [AArch64] Use add_like for SABD and UABA (PR #194421)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Fri May 1 06:37:02 PDT 2026
https://github.com/davemgreen updated https://github.com/llvm/llvm-project/pull/194421
>From d339a616a47bb68bc287ba7c50227e839aa5ec46 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Mon, 27 Apr 2026 18:36:20 +0100
Subject: [PATCH] [AArch64] Use add_like for SABD and UABA
Similar to the other patches that have made use of add_like recent, this adds
add_like to the SABA and UABA patterns.
---
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 26 ++++-----
.../CodeGen/AArch64/arm64-neon-aba-abd.ll | 36 ++++--------
llvm/test/CodeGen/AArch64/neon-saba.ll | 57 ++++++++-----------
3 files changed, 49 insertions(+), 70 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 59f6b1c9d1bfb..315821ea65f2d 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -6176,7 +6176,7 @@ defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
let isCommutable = 1 in
defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", clmul>;
defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
- TriOpFrag<(add node:$LHS, (abds node:$MHS, node:$RHS))> >;
+ TriOpFrag<(add_like node:$LHS, (abds node:$MHS, node:$RHS))> >;
defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", abds>;
defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", avgfloors>;
defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>;
@@ -6195,7 +6195,7 @@ defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>;
defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>;
defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
- TriOpFrag<(add node:$LHS, (abdu node:$MHS, node:$RHS))> >;
+ TriOpFrag<(add_like node:$LHS, (abdu node:$MHS, node:$RHS))> >;
defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", abdu>;
defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", avgflooru>;
defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>;
@@ -7399,7 +7399,7 @@ defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubh
let isCommutable = 1 in
defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull", AArch64pmull>;
defm SABAL : SIMDLongThreeVectorTiedBHS<0,0b0101,"sabal",
- TriOpFrag<(add node:$LHS, (zext (abds node:$MHS, node:$RHS)))>>;
+ TriOpFrag<(add_like node:$LHS, (zext (abds node:$MHS, node:$RHS)))>>;
defm SABDL : SIMDLongThreeVectorBHS<0, 0b0111, "sabdl",
BinOpFrag<(zext (abds node:$LHS, node:$RHS))>>;
defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
@@ -7420,7 +7420,7 @@ defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
defm UABAL : SIMDLongThreeVectorTiedBHS<1, 0b0101, "uabal",
- TriOpFrag<(add node:$LHS, (zext (abdu node:$MHS, node:$RHS)))>>;
+ TriOpFrag<(add_like node:$LHS, (zext (abdu node:$MHS, node:$RHS)))>>;
defm UABDL : SIMDLongThreeVectorBHS<1, 0b0111, "uabdl",
BinOpFrag<(zext (abdu node:$LHS, node:$RHS))>>;
defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
@@ -8874,25 +8874,25 @@ def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
}
// SABA patterns for add(x, abs(y)) -> saba(x, y, 0)
-def : Pat<(v8i8 (add V64:$Vn, (abs V64:$Vm))),
+def : Pat<(v8i8 (add_like V64:$Vn, (abs V64:$Vm))),
(SABAv8i8 V64:$Vn, V64:$Vm, (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub))>;
-def : Pat<(v4i16 (add V64:$Vn, (abs V64:$Vm))),
+def : Pat<(v4i16 (add_like V64:$Vn, (abs V64:$Vm))),
(SABAv4i16 V64:$Vn, V64:$Vm, (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub))>;
-def : Pat<(v2i32 (add V64:$Vn, (abs V64:$Vm))),
+def : Pat<(v2i32 (add_like V64:$Vn, (abs V64:$Vm))),
(SABAv2i32 V64:$Vn, V64:$Vm, (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub))>;
-def : Pat<(v16i8 (add V128:$Vn, (abs V128:$Vm))),
+def : Pat<(v16i8 (add_like V128:$Vn, (abs V128:$Vm))),
(SABAv16i8 V128:$Vn, V128:$Vm, (MOVIv2d_ns (i32 0)))>;
-def : Pat<(v8i16 (add V128:$Vn, (abs V128:$Vm))),
+def : Pat<(v8i16 (add_like V128:$Vn, (abs V128:$Vm))),
(SABAv8i16 V128:$Vn, V128:$Vm, (MOVIv2d_ns (i32 0)))>;
-def : Pat<(v4i32 (add V128:$Vn, (abs V128:$Vm))),
+def : Pat<(v4i32 (add_like V128:$Vn, (abs V128:$Vm))),
(SABAv4i32 V128:$Vn, V128:$Vm, (MOVIv2d_ns (i32 0)))>;
// SABAL patterns for add(x, zext(abs(y))) -> sabal(x, y, 0)
-def : Pat<(v8i16 (add V128:$Vn, (zext (abs (v8i8 V64:$Vm))))),
+def : Pat<(v8i16 (add_like V128:$Vn, (zext (abs (v8i8 V64:$Vm))))),
(SABALv8i8_v8i16 V128:$Vn, V64:$Vm, (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub))>;
-def : Pat<(v4i32 (add V128:$Vn, (zext (abs (v4i16 V64:$Vm))))),
+def : Pat<(v4i32 (add_like V128:$Vn, (zext (abs (v4i16 V64:$Vm))))),
(SABALv4i16_v4i32 V128:$Vn, V64:$Vm, (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub))>;
-def : Pat<(v2i64 (add V128:$Vn, (zext (abs (v2i32 V64:$Vm))))),
+def : Pat<(v2i64 (add_like V128:$Vn, (zext (abs (v2i32 V64:$Vm))))),
(SABALv2i32_v2i64 V128:$Vn, V64:$Vm, (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub))>;
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll b/llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll
index e72bba25c94be..9ffda5b9b0af9 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll
@@ -24,8 +24,7 @@ define <8 x i8> @test_uaba_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
define <8 x i8> @test_uaba_or_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
; CHECK-LABEL: test_uaba_or_v8i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: uabd v1.8b, v0.8b, v1.8b
-; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: uaba v0.8b, v0.8b, v1.8b
; CHECK-NEXT: ret
%abd = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
%aba = or disjoint <8 x i8> %lhs, %abd
@@ -54,8 +53,7 @@ define <8 x i8> @test_saba_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
define <8 x i8> @test_saba_or_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
; CHECK-LABEL: test_saba_or_v8i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: sabd v1.8b, v0.8b, v1.8b
-; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: saba v0.8b, v0.8b, v1.8b
; CHECK-NEXT: ret
%abd = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
%aba = or disjoint <8 x i8> %lhs, %abd
@@ -84,8 +82,7 @@ define <16 x i8> @test_uaba_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
define <16 x i8> @test_uaba_or_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
; CHECK-LABEL: test_uaba_or_v16i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: uabd v1.16b, v0.16b, v1.16b
-; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: uaba v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret
%abd = call <16 x i8> @llvm.aarch64.neon.uabd.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
%aba = or disjoint <16 x i8> %lhs, %abd
@@ -114,8 +111,7 @@ define <16 x i8> @test_saba_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
define <16 x i8> @test_saba_or_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
; CHECK-LABEL: test_saba_or_v16i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: sabd v1.16b, v0.16b, v1.16b
-; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: saba v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret
%abd = call <16 x i8> @llvm.aarch64.neon.sabd.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
%aba = or disjoint <16 x i8> %lhs, %abd
@@ -144,8 +140,7 @@ define <4 x i16> @test_uaba_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
define <4 x i16> @test_uaba_or_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; CHECK-LABEL: test_uaba_or_v4i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: uabd v1.4h, v0.4h, v1.4h
-; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: uaba v0.4h, v0.4h, v1.4h
; CHECK-NEXT: ret
%abd = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
%aba = or disjoint <4 x i16> %lhs, %abd
@@ -174,8 +169,7 @@ define <4 x i16> @test_saba_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
define <4 x i16> @test_saba_or_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; CHECK-LABEL: test_saba_or_v4i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: sabd v1.4h, v0.4h, v1.4h
-; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: saba v0.4h, v0.4h, v1.4h
; CHECK-NEXT: ret
%abd = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
%aba = or disjoint <4 x i16> %lhs, %abd
@@ -204,8 +198,7 @@ define <8 x i16> @test_uaba_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
define <8 x i16> @test_uaba_or_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
; CHECK-LABEL: test_uaba_or_v8i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: uabd v1.8h, v0.8h, v1.8h
-; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: uaba v0.8h, v0.8h, v1.8h
; CHECK-NEXT: ret
%abd = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
%aba = or disjoint <8 x i16> %lhs, %abd
@@ -234,8 +227,7 @@ define <8 x i16> @test_saba_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
define <8 x i16> @test_saba_or_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
; CHECK-LABEL: test_saba_or_v8i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: sabd v1.8h, v0.8h, v1.8h
-; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: saba v0.8h, v0.8h, v1.8h
; CHECK-NEXT: ret
%abd = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
%aba = or disjoint <8 x i16> %lhs, %abd
@@ -264,8 +256,7 @@ define <2 x i32> @test_uaba_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
define <2 x i32> @test_uaba_or_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
; CHECK-LABEL: test_uaba_or_v2i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: uabd v1.2s, v0.2s, v1.2s
-; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: uaba v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ret
%abd = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
%aba = or disjoint <2 x i32> %lhs, %abd
@@ -294,8 +285,7 @@ define <2 x i32> @test_saba_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
define <2 x i32> @test_saba_or_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
; CHECK-LABEL: test_saba_or_v2i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: sabd v1.2s, v0.2s, v1.2s
-; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: saba v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ret
%abd = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
%aba = or disjoint <2 x i32> %lhs, %abd
@@ -345,8 +335,7 @@ define <4 x i32> @test_uaba_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
define <4 x i32> @test_uaba_or_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; CHECK-LABEL: test_uaba_or_v4i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: uabd v1.4s, v0.4s, v1.4s
-; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: uaba v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret
%abd = call <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
%aba = or disjoint <4 x i32> %lhs, %abd
@@ -375,8 +364,7 @@ define <4 x i32> @test_saba_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
define <4 x i32> @test_saba_or_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; CHECK-LABEL: test_saba_or_v4i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: sabd v1.4s, v0.4s, v1.4s
-; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: saba v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret
%abd = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
%aba = or disjoint <4 x i32> %lhs, %abd
diff --git a/llvm/test/CodeGen/AArch64/neon-saba.ll b/llvm/test/CodeGen/AArch64/neon-saba.ll
index f33c04e462780..5c385978d9e5a 100644
--- a/llvm/test/CodeGen/AArch64/neon-saba.ll
+++ b/llvm/test/CodeGen/AArch64/neon-saba.ll
@@ -387,8 +387,7 @@ define <8 x i16> @sabal_abs_zeros_8b(<8 x i16> %a, <8 x i8> %b) #0 {
define <4 x i32> @saba_or_sabd_4s(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) #0 {
; CHECK-LABEL: saba_or_sabd_4s:
; CHECK: // %bb.0:
-; CHECK-NEXT: sabd v1.4s, v1.4s, v2.4s
-; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
+; CHECK-NEXT: saba v0.4s, v1.4s, v2.4s
; CHECK-NEXT: ret
%sabd = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %b, <4 x i32> %c)
%add = or disjoint <4 x i32> %sabd, %a
@@ -398,8 +397,7 @@ define <4 x i32> @saba_or_sabd_4s(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) #0 {
define <2 x i32> @saba_or_sabd_2s(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) #0 {
; CHECK-LABEL: saba_or_sabd_2s:
; CHECK: // %bb.0:
-; CHECK-NEXT: sabd v1.2s, v1.2s, v2.2s
-; CHECK-NEXT: orr v0.8b, v1.8b, v0.8b
+; CHECK-NEXT: saba v0.2s, v1.2s, v2.2s
; CHECK-NEXT: ret
%sabd = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %b, <2 x i32> %c)
%add = or disjoint <2 x i32> %sabd, %a
@@ -409,8 +407,7 @@ define <2 x i32> @saba_or_sabd_2s(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) #0 {
define <8 x i16> @saba_or_sabd_8h(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) #0 {
; CHECK-LABEL: saba_or_sabd_8h:
; CHECK: // %bb.0:
-; CHECK-NEXT: sabd v1.8h, v1.8h, v2.8h
-; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
+; CHECK-NEXT: saba v0.8h, v1.8h, v2.8h
; CHECK-NEXT: ret
%sabd = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> %b, <8 x i16> %c)
%add = or disjoint <8 x i16> %sabd, %a
@@ -420,8 +417,7 @@ define <8 x i16> @saba_or_sabd_8h(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) #0 {
define <4 x i16> @saba_or_sabd_4h(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) #0 {
; CHECK-LABEL: saba_or_sabd_4h:
; CHECK: // %bb.0:
-; CHECK-NEXT: sabd v1.4h, v1.4h, v2.4h
-; CHECK-NEXT: orr v0.8b, v1.8b, v0.8b
+; CHECK-NEXT: saba v0.4h, v1.4h, v2.4h
; CHECK-NEXT: ret
%sabd = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %b, <4 x i16> %c)
%add = or disjoint <4 x i16> %sabd, %a
@@ -431,8 +427,7 @@ define <4 x i16> @saba_or_sabd_4h(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) #0 {
define <16 x i8> @saba_or_sabd_16b(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) #0 {
; CHECK-LABEL: saba_or_sabd_16b:
; CHECK: // %bb.0:
-; CHECK-NEXT: sabd v1.16b, v1.16b, v2.16b
-; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
+; CHECK-NEXT: saba v0.16b, v1.16b, v2.16b
; CHECK-NEXT: ret
%sabd = call <16 x i8> @llvm.aarch64.neon.sabd.v16i8(<16 x i8> %b, <16 x i8> %c)
%add = or disjoint <16 x i8> %sabd, %a
@@ -442,8 +437,7 @@ define <16 x i8> @saba_or_sabd_16b(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) #0
define <8 x i8> @saba_or_sabd_8b(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) #0 {
; CHECK-LABEL: saba_or_sabd_8b:
; CHECK: // %bb.0:
-; CHECK-NEXT: sabd v1.8b, v1.8b, v2.8b
-; CHECK-NEXT: orr v0.8b, v1.8b, v0.8b
+; CHECK-NEXT: saba v0.8b, v1.8b, v2.8b
; CHECK-NEXT: ret
%sabd = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %b, <8 x i8> %c)
%add = or disjoint <8 x i8> %sabd, %a
@@ -455,8 +449,8 @@ define <8 x i8> @saba_or_sabd_8b(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) #0 {
define <4 x i32> @saba_or_abs_zeros_4s(<4 x i32> %a, <4 x i32> %b) #0 {
; CHECK-LABEL: saba_or_abs_zeros_4s:
; CHECK: // %bb.0:
-; CHECK-NEXT: abs v1.4s, v1.4s
-; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: movi v2.2d, #0000000000000000
+; CHECK-NEXT: saba v0.4s, v1.4s, v2.4s
; CHECK-NEXT: ret
%abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %b, i1 true)
%add = or disjoint <4 x i32> %a, %abs
@@ -466,8 +460,8 @@ define <4 x i32> @saba_or_abs_zeros_4s(<4 x i32> %a, <4 x i32> %b) #0 {
define <2 x i32> @saba_or_abs_zeros_2s(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-LABEL: saba_or_abs_zeros_2s:
; CHECK: // %bb.0:
-; CHECK-NEXT: abs v1.2s, v1.2s
-; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: movi v2.2d, #0000000000000000
+; CHECK-NEXT: saba v0.2s, v1.2s, v2.2s
; CHECK-NEXT: ret
%abs = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %b, i1 true)
%add = or disjoint <2 x i32> %a, %abs
@@ -477,8 +471,8 @@ define <2 x i32> @saba_or_abs_zeros_2s(<2 x i32> %a, <2 x i32> %b) #0 {
define <8 x i16> @saba_or_abs_zeros_8h(<8 x i16> %a, <8 x i16> %b) #0 {
; CHECK-LABEL: saba_or_abs_zeros_8h:
; CHECK: // %bb.0:
-; CHECK-NEXT: abs v1.8h, v1.8h
-; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: movi v2.2d, #0000000000000000
+; CHECK-NEXT: saba v0.8h, v1.8h, v2.8h
; CHECK-NEXT: ret
%abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %b, i1 true)
%add = or disjoint <8 x i16> %a, %abs
@@ -488,8 +482,8 @@ define <8 x i16> @saba_or_abs_zeros_8h(<8 x i16> %a, <8 x i16> %b) #0 {
define <4 x i16> @saba_or_abs_zeros_4h(<4 x i16> %a, <4 x i16> %b) #0 {
; CHECK-LABEL: saba_or_abs_zeros_4h:
; CHECK: // %bb.0:
-; CHECK-NEXT: abs v1.4h, v1.4h
-; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: movi v2.2d, #0000000000000000
+; CHECK-NEXT: saba v0.4h, v1.4h, v2.4h
; CHECK-NEXT: ret
%abs = call <4 x i16> @llvm.abs.v4i16(<4 x i16> %b, i1 true)
%add = or disjoint <4 x i16> %a, %abs
@@ -499,8 +493,8 @@ define <4 x i16> @saba_or_abs_zeros_4h(<4 x i16> %a, <4 x i16> %b) #0 {
define <16 x i8> @saba_or_abs_zeros_16b(<16 x i8> %a, <16 x i8> %b) #0 {
; CHECK-LABEL: saba_or_abs_zeros_16b:
; CHECK: // %bb.0:
-; CHECK-NEXT: abs v1.16b, v1.16b
-; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: movi v2.2d, #0000000000000000
+; CHECK-NEXT: saba v0.16b, v1.16b, v2.16b
; CHECK-NEXT: ret
%abs = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %b, i1 true)
%add = or disjoint <16 x i8> %a, %abs
@@ -510,8 +504,8 @@ define <16 x i8> @saba_or_abs_zeros_16b(<16 x i8> %a, <16 x i8> %b) #0 {
define <8 x i8> @saba_or_abs_zeros_8b(<8 x i8> %a, <8 x i8> %b) #0 {
; CHECK-LABEL: saba_or_abs_zeros_8b:
; CHECK: // %bb.0:
-; CHECK-NEXT: abs v1.8b, v1.8b
-; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: movi v2.2d, #0000000000000000
+; CHECK-NEXT: saba v0.8b, v1.8b, v2.8b
; CHECK-NEXT: ret
%abs = call <8 x i8> @llvm.abs.v8i8(<8 x i8> %b, i1 true)
%add = or disjoint <8 x i8> %a, %abs
@@ -523,9 +517,8 @@ define <8 x i8> @saba_or_abs_zeros_8b(<8 x i8> %a, <8 x i8> %b) #0 {
define <2 x i64> @sabal_or_abs_zeros_2s(<2 x i64> %a, <2 x i32> %b) #0 {
; CHECK-LABEL: sabal_or_abs_zeros_2s:
; CHECK: // %bb.0:
-; CHECK-NEXT: abs v1.2s, v1.2s
-; CHECK-NEXT: ushll v1.2d, v1.2s, #0
-; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: movi v2.2d, #0000000000000000
+; CHECK-NEXT: sabal v0.2d, v1.2s, v2.2s
; CHECK-NEXT: ret
%abs = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %b, i1 true)
%abs.zext = zext <2 x i32> %abs to <2 x i64>
@@ -536,9 +529,8 @@ define <2 x i64> @sabal_or_abs_zeros_2s(<2 x i64> %a, <2 x i32> %b) #0 {
define <4 x i32> @sabal_or_abs_zeros_4h(<4 x i32> %a, <4 x i16> %b) #0 {
; CHECK-LABEL: sabal_or_abs_zeros_4h:
; CHECK: // %bb.0:
-; CHECK-NEXT: abs v1.4h, v1.4h
-; CHECK-NEXT: ushll v1.4s, v1.4h, #0
-; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: movi v2.2d, #0000000000000000
+; CHECK-NEXT: sabal v0.4s, v1.4h, v2.4h
; CHECK-NEXT: ret
%abs = call <4 x i16> @llvm.abs.v4i16(<4 x i16> %b, i1 true)
%abs.zext = zext <4 x i16> %abs to <4 x i32>
@@ -549,9 +541,8 @@ define <4 x i32> @sabal_or_abs_zeros_4h(<4 x i32> %a, <4 x i16> %b) #0 {
define <8 x i16> @sabal_or_abs_zeros_8b(<8 x i16> %a, <8 x i8> %b) #0 {
; CHECK-LABEL: sabal_or_abs_zeros_8b:
; CHECK: // %bb.0:
-; CHECK-NEXT: abs v1.8b, v1.8b
-; CHECK-NEXT: ushll v1.8h, v1.8b, #0
-; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: movi v2.2d, #0000000000000000
+; CHECK-NEXT: sabal v0.8h, v1.8b, v2.8b
; CHECK-NEXT: ret
%abs = call <8 x i8> @llvm.abs.v8i8(<8 x i8> %b, i1 true)
%abs.zext = zext <8 x i8> %abs to <8 x i16>
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