[llvm] [AArch64][DAGcombine] Combine (zext i8 * 0x010101...) to NEON dup (PR #194246)

[Matt Arsenault via llvm-commits]

================
@@ -20346,6 +20346,52 @@ static SDValue performVectorExtCombine(SDNode *N, SelectionDAG &DAG) {
   return SDValue();
 }
 
+// Combine (zext i8 to iN) * 0x010101... into a NEON byte broadcast using dup.
+static SDValue performMulBroadcastCombine(SDNode *N, SelectionDAG &DAG,
+                                          const AArch64Subtarget *Subtarget) {
+  EVT MulVT = N->getValueType(0);
+  if (!MulVT.isInteger() || MulVT.isVector() || !Subtarget->hasNEON())
+    return SDValue();
+
+  SDValue N0 = N->getOperand(0);
+  SDValue N1 = N->getOperand(1);
+
+  ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1);
+  if (!C)
+    return SDValue();
+
+  const APInt &ConstValue = C->getAPIntValue();
+  unsigned BitWidth = ConstValue.getBitWidth();
+
+  if (N0->getOpcode() != ISD::ZERO_EXTEND ||
+      N0->getOperand(0).getValueType() != MVT::i8)
+    return SDValue();
+
+  // Check if the constant is a byte broadcast pattern: 0x01010101...
+  if (!ConstValue.isSplat(8) || ConstValue.extractBits(8, 0) != 0x01)
+    return SDValue();
+
+  if (BitWidth != 32 && BitWidth != 64)
+    return SDValue();
+
+  if (!DAG.getTargetLoweringInfo().isTypeLegal(MVT::v8i8))
+    return SDValue();
+
+  SDLoc DL(N);
+
+  MVT VecVT;
+  if (BitWidth == 32)
+    VecVT = MVT::v4i8; // type legalizer will handle v4i8
----------------
arsenm wrote:

This might need a guard that DCI.isBeforeLegalize() if you are introducing nonlegal types 

https://github.com/llvm/llvm-project/pull/194246