[llvm] [AArch64] Use dup (lane mov) over ext for high-half extract (PR #195010)
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llvm-commits at lists.llvm.org
Fri May 1 03:27:50 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: David Green (davemgreen)
<details>
<summary>Changes</summary>
This changes the instruction we use to extract the high half of a vector register from a `ext v0, v1, v1, 8` to a `dup d0, v1.d[1]`. This is apparently slightly quicker on certain cpus and is generally a simpler instruction. This matches the instruction that gisel already produces.
---
Patch is 287.62 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/195010.diff
85 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.td (+15-11)
- (modified) llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll (+12-12)
- (modified) llvm/test/CodeGen/AArch64/aarch64-mulv.ll (+14-23)
- (modified) llvm/test/CodeGen/AArch64/aarch64_be-shuffle-vector.ll (+2-2)
- (modified) llvm/test/CodeGen/AArch64/abd-combine.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/add-extract.ll (+2-2)
- (modified) llvm/test/CodeGen/AArch64/arm64-ext.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll (+7-14)
- (modified) llvm/test/CodeGen/AArch64/arm64-neon-copy.ll (+4-10)
- (modified) llvm/test/CodeGen/AArch64/arm64-neon-simd-vget.ll (+14-28)
- (modified) llvm/test/CodeGen/AArch64/bf16-shuffle.ll (+1-2)
- (modified) llvm/test/CodeGen/AArch64/bf16-vector-shuffle.ll (+1-2)
- (modified) llvm/test/CodeGen/AArch64/clmul-fixed.ll (+6-6)
- (modified) llvm/test/CodeGen/AArch64/combine-storetomstore.ll (+2-2)
- (modified) llvm/test/CodeGen/AArch64/complex-deinterleaving-mixed-cases.ll (+14-14)
- (modified) llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll (+10-10)
- (modified) llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll (+4-4)
- (modified) llvm/test/CodeGen/AArch64/concat-vector.ll (+5-11)
- (modified) llvm/test/CodeGen/AArch64/ctlz.ll (+1-2)
- (modified) llvm/test/CodeGen/AArch64/ctpop.ll (+1-2)
- (modified) llvm/test/CodeGen/AArch64/cttz.ll (+1-2)
- (modified) llvm/test/CodeGen/AArch64/double_reduct.ll (+15-15)
- (modified) llvm/test/CodeGen/AArch64/ext-narrow-index.ll (+16-40)
- (modified) llvm/test/CodeGen/AArch64/extract-subvec-combine.ll (+8-12)
- (modified) llvm/test/CodeGen/AArch64/extract-vector-elt.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/f16f32dot-fixed-length-fdot.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/fabs.ll (+1-2)
- (modified) llvm/test/CodeGen/AArch64/faddsub.ll (+2-4)
- (modified) llvm/test/CodeGen/AArch64/fcmp.ll (+3-5)
- (modified) llvm/test/CodeGen/AArch64/fcopysign.ll (+1-2)
- (modified) llvm/test/CodeGen/AArch64/fcvt.ll (+7-14)
- (modified) llvm/test/CodeGen/AArch64/fdiv.ll (+1-2)
- (modified) llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll (+7-11)
- (modified) llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll (+3-6)
- (modified) llvm/test/CodeGen/AArch64/fminimummaximum.ll (+2-4)
- (modified) llvm/test/CodeGen/AArch64/fminmax.ll (+2-4)
- (modified) llvm/test/CodeGen/AArch64/fmla.ll (+3-6)
- (modified) llvm/test/CodeGen/AArch64/fmul.ll (+1-2)
- (modified) llvm/test/CodeGen/AArch64/fneg.ll (+1-2)
- (modified) llvm/test/CodeGen/AArch64/fp-maximumnum-minimumnum.ll (+5-8)
- (modified) llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll (+1-2)
- (modified) llvm/test/CodeGen/AArch64/fpext.ll (+11-23)
- (modified) llvm/test/CodeGen/AArch64/fptoi.ll (+40-126)
- (modified) llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll (+17-17)
- (modified) llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll (+9-9)
- (modified) llvm/test/CodeGen/AArch64/freeze.ll (+2-4)
- (modified) llvm/test/CodeGen/AArch64/fsqrt.ll (+1-2)
- (modified) llvm/test/CodeGen/AArch64/highextractbitcast.ll (+33-54)
- (modified) llvm/test/CodeGen/AArch64/icmp.ll (+1-2)
- (modified) llvm/test/CodeGen/AArch64/insert-subvector.ll (+3-3)
- (modified) llvm/test/CodeGen/AArch64/insertextract.ll (+4-8)
- (modified) llvm/test/CodeGen/AArch64/itofp.ll (+100-332)
- (modified) llvm/test/CodeGen/AArch64/neon-abd.ll (+2-2)
- (modified) llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll (+35-35)
- (modified) llvm/test/CodeGen/AArch64/neon-scalar-copy.ll (+56-65)
- (modified) llvm/test/CodeGen/AArch64/nontemporal-load.ll (+4-8)
- (modified) llvm/test/CodeGen/AArch64/ptradd.ll (+3-5)
- (modified) llvm/test/CodeGen/AArch64/reduce-and.ll (+8-8)
- (modified) llvm/test/CodeGen/AArch64/reduce-or.ll (+8-8)
- (modified) llvm/test/CodeGen/AArch64/reduce-xor.ll (+8-8)
- (modified) llvm/test/CodeGen/AArch64/sext.ll (+4-8)
- (modified) llvm/test/CodeGen/AArch64/st1-lane.ll (+56-120)
- (modified) llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll (+7-14)
- (modified) llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll (+2-2)
- (modified) llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll (+6-6)
- (modified) llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll (+2-2)
- (modified) llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll (+24-24)
- (modified) llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll (+2-2)
- (modified) llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll (+12-12)
- (modified) llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll (+4-4)
- (modified) llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll (+107-107)
- (modified) llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll (+107-107)
- (modified) llvm/test/CodeGen/AArch64/vec_uaddo.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/vec_umulo.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll (+4-4)
- (modified) llvm/test/CodeGen/AArch64/vecreduce-bitext.ll (+36-36)
- (modified) llvm/test/CodeGen/AArch64/vecreduce-fmul.ll (+17-17)
- (modified) llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/vector-fcvt.ll (+6-6)
- (modified) llvm/test/CodeGen/AArch64/vector-llrint.ll (+50-50)
- (modified) llvm/test/CodeGen/AArch64/vector-lrint.ll (+57-57)
- (modified) llvm/test/CodeGen/AArch64/vselect-ext.ll (+4-4)
- (modified) llvm/test/CodeGen/AArch64/zext-shuffle.ll (+6-6)
- (modified) llvm/test/CodeGen/AArch64/zext-to-tbl.ll (+16-16)
- (modified) llvm/test/CodeGen/AArch64/zext.ll (+5-9)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index f20f978fe7e8a..17d2e0e5ee317 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -7559,10 +7559,6 @@ multiclass ExtPat<ValueType VT64, ValueType VT128, int N> {
(EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
def : Pat<(VT128 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
(EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
- // We use EXT to handle extract_subvector to copy the upper 64-bits of a
- // 128-bit vector.
- def : Pat<(VT64 (extract_subvector V128:$Rn, (i64 N))),
- (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
// A 64-bit EXT of two halves of the same 128-bit register can be done as a
// single 128-bit EXT.
def : Pat<(VT64 (AArch64ext (extract_subvector V128:$Rn, (i64 0)),
@@ -10951,14 +10947,22 @@ def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 0))),
def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 0))),
(EXTRACT_SUBREG V128:$Rn, dsub)>;
-def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
- (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
-def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
- (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
-def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
- (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
+def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 8))),
+ (DUPi64 FPR128:$Rn, 1)>;
+def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 4))),
+ (DUPi64 FPR128:$Rn, 1)>;
+def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 2))),
+ (DUPi64 FPR128:$Rn, 1)>;
def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
- (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
+ (DUPi64 FPR128:$Rn, 1)>;
+def : Pat<(v4bf16 (extract_subvector (v8bf16 FPR128:$Rn), (i64 4))),
+ (DUPi64 FPR128:$Rn, 1)>;
+def : Pat<(v4f16 (extract_subvector (v8f16 FPR128:$Rn), (i64 4))),
+ (DUPi64 FPR128:$Rn, 1)>;
+def : Pat<(v2f32 (extract_subvector (v4f32 FPR128:$Rn), (i64 2))),
+ (DUPi64 FPR128:$Rn, 1)>;
+def : Pat<(v1f64 (extract_subvector (v2f64 FPR128:$Rn), (i64 1))),
+ (DUPi64 FPR128:$Rn, 1)>;
// A 64-bit subvector insert to the first 128-bit vector position
// is a subregister copy that needs no instruction.
diff --git a/llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll b/llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll
index 2f0ec2b75bfc6..c5a8bba502e22 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll
@@ -604,7 +604,7 @@ entry:
define i64 @sminv_v2i64(<2 x i64> %a) {
; CHECK-SD-NOSVE-LABEL: sminv_v2i64:
; CHECK-SD-NOSVE: // %bb.0: // %entry
-; CHECK-SD-NOSVE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NOSVE-NEXT: mov d1, v0.d[1]
; CHECK-SD-NOSVE-NEXT: cmgt d2, d1, d0
; CHECK-SD-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; CHECK-SD-NOSVE-NEXT: fmov x0, d0
@@ -643,7 +643,7 @@ define i64 @sminv_v3i64(<3 x i64> %a) {
; CHECK-SD-NOSVE-NEXT: mov v2.d[1], x8
; CHECK-SD-NOSVE-NEXT: cmgt v1.2d, v2.2d, v0.2d
; CHECK-SD-NOSVE-NEXT: bif v0.16b, v2.16b, v1.16b
-; CHECK-SD-NOSVE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NOSVE-NEXT: mov d1, v0.d[1]
; CHECK-SD-NOSVE-NEXT: cmgt d2, d1, d0
; CHECK-SD-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; CHECK-SD-NOSVE-NEXT: fmov x0, d0
@@ -690,7 +690,7 @@ define i64 @sminv_v4i64(<4 x i64> %a) {
; CHECK-SD-NOSVE: // %bb.0: // %entry
; CHECK-SD-NOSVE-NEXT: cmgt v2.2d, v1.2d, v0.2d
; CHECK-SD-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-SD-NOSVE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NOSVE-NEXT: mov d1, v0.d[1]
; CHECK-SD-NOSVE-NEXT: cmgt d2, d1, d0
; CHECK-SD-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; CHECK-SD-NOSVE-NEXT: fmov x0, d0
@@ -996,7 +996,7 @@ entry:
define i64 @smaxv_v2i64(<2 x i64> %a) {
; CHECK-SD-NOSVE-LABEL: smaxv_v2i64:
; CHECK-SD-NOSVE: // %bb.0: // %entry
-; CHECK-SD-NOSVE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NOSVE-NEXT: mov d1, v0.d[1]
; CHECK-SD-NOSVE-NEXT: cmgt d2, d0, d1
; CHECK-SD-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; CHECK-SD-NOSVE-NEXT: fmov x0, d0
@@ -1035,7 +1035,7 @@ define i64 @smaxv_v3i64(<3 x i64> %a) {
; CHECK-SD-NOSVE-NEXT: mov v2.d[1], x8
; CHECK-SD-NOSVE-NEXT: cmgt v1.2d, v0.2d, v2.2d
; CHECK-SD-NOSVE-NEXT: bif v0.16b, v2.16b, v1.16b
-; CHECK-SD-NOSVE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NOSVE-NEXT: mov d1, v0.d[1]
; CHECK-SD-NOSVE-NEXT: cmgt d2, d0, d1
; CHECK-SD-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; CHECK-SD-NOSVE-NEXT: fmov x0, d0
@@ -1082,7 +1082,7 @@ define i64 @smaxv_v4i64(<4 x i64> %a) {
; CHECK-SD-NOSVE: // %bb.0: // %entry
; CHECK-SD-NOSVE-NEXT: cmgt v2.2d, v0.2d, v1.2d
; CHECK-SD-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-SD-NOSVE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NOSVE-NEXT: mov d1, v0.d[1]
; CHECK-SD-NOSVE-NEXT: cmgt d2, d0, d1
; CHECK-SD-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; CHECK-SD-NOSVE-NEXT: fmov x0, d0
@@ -1386,7 +1386,7 @@ entry:
define i64 @uminv_v2i64(<2 x i64> %a) {
; CHECK-SD-NOSVE-LABEL: uminv_v2i64:
; CHECK-SD-NOSVE: // %bb.0: // %entry
-; CHECK-SD-NOSVE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NOSVE-NEXT: mov d1, v0.d[1]
; CHECK-SD-NOSVE-NEXT: cmhi d2, d1, d0
; CHECK-SD-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; CHECK-SD-NOSVE-NEXT: fmov x0, d0
@@ -1425,7 +1425,7 @@ define i64 @uminv_v3i64(<3 x i64> %a) {
; CHECK-SD-NOSVE-NEXT: mov v2.d[1], x8
; CHECK-SD-NOSVE-NEXT: cmhi v1.2d, v2.2d, v0.2d
; CHECK-SD-NOSVE-NEXT: bif v0.16b, v2.16b, v1.16b
-; CHECK-SD-NOSVE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NOSVE-NEXT: mov d1, v0.d[1]
; CHECK-SD-NOSVE-NEXT: cmhi d2, d1, d0
; CHECK-SD-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; CHECK-SD-NOSVE-NEXT: fmov x0, d0
@@ -1472,7 +1472,7 @@ define i64 @uminv_v4i64(<4 x i64> %a) {
; CHECK-SD-NOSVE: // %bb.0: // %entry
; CHECK-SD-NOSVE-NEXT: cmhi v2.2d, v1.2d, v0.2d
; CHECK-SD-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-SD-NOSVE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NOSVE-NEXT: mov d1, v0.d[1]
; CHECK-SD-NOSVE-NEXT: cmhi d2, d1, d0
; CHECK-SD-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; CHECK-SD-NOSVE-NEXT: fmov x0, d0
@@ -1765,7 +1765,7 @@ entry:
define i64 @umaxv_v2i64(<2 x i64> %a) {
; CHECK-SD-NOSVE-LABEL: umaxv_v2i64:
; CHECK-SD-NOSVE: // %bb.0: // %entry
-; CHECK-SD-NOSVE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NOSVE-NEXT: mov d1, v0.d[1]
; CHECK-SD-NOSVE-NEXT: cmhi d2, d0, d1
; CHECK-SD-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; CHECK-SD-NOSVE-NEXT: fmov x0, d0
@@ -1803,7 +1803,7 @@ define i64 @umaxv_v3i64(<3 x i64> %a) {
; CHECK-SD-NOSVE-NEXT: mov v0.d[1], v1.d[0]
; CHECK-SD-NOSVE-NEXT: mov v3.d[1], xzr
; CHECK-SD-NOSVE-NEXT: cmhi v3.2d, v0.2d, v3.2d
-; CHECK-SD-NOSVE-NEXT: ext v4.16b, v3.16b, v3.16b, #8
+; CHECK-SD-NOSVE-NEXT: mov d4, v3.d[1]
; CHECK-SD-NOSVE-NEXT: bif v0.16b, v2.16b, v3.16b
; CHECK-SD-NOSVE-NEXT: and v1.8b, v1.8b, v4.8b
; CHECK-SD-NOSVE-NEXT: cmhi d2, d0, d1
@@ -1850,7 +1850,7 @@ define i64 @umaxv_v4i64(<4 x i64> %a) {
; CHECK-SD-NOSVE: // %bb.0: // %entry
; CHECK-SD-NOSVE-NEXT: cmhi v2.2d, v0.2d, v1.2d
; CHECK-SD-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-SD-NOSVE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NOSVE-NEXT: mov d1, v0.d[1]
; CHECK-SD-NOSVE-NEXT: cmhi d2, d0, d1
; CHECK-SD-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; CHECK-SD-NOSVE-NEXT: fmov x0, d0
diff --git a/llvm/test/CodeGen/AArch64/aarch64-mulv.ll b/llvm/test/CodeGen/AArch64/aarch64-mulv.ll
index fecc6554667fa..f200444cfa23f 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-mulv.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-mulv.ll
@@ -125,7 +125,7 @@ entry:
define i8 @mulv_v16i8(<16 x i8> %a) {
; CHECK-SD-LABEL: mulv_v16i8:
; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: mul v0.8b, v0.8b, v1.8b
; CHECK-SD-NEXT: umov w8, v0.b[1]
; CHECK-SD-NEXT: umov w9, v0.b[0]
@@ -173,7 +173,7 @@ define i8 @mulv_v32i8(<32 x i8> %a) {
; CHECK-SD-LABEL: mulv_v32i8:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: mul v0.16b, v0.16b, v1.16b
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: mul v0.8b, v0.8b, v1.8b
; CHECK-SD-NEXT: umov w8, v0.b[1]
; CHECK-SD-NEXT: umov w9, v0.b[0]
@@ -290,7 +290,7 @@ entry:
define i16 @mulv_v8i16(<8 x i16> %a) {
; CHECK-SD-LABEL: mulv_v8i16:
; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: mul v0.4h, v0.4h, v1.4h
; CHECK-SD-NEXT: umov w8, v0.h[1]
; CHECK-SD-NEXT: umov w9, v0.h[0]
@@ -322,7 +322,7 @@ define i16 @mulv_v16i16(<16 x i16> %a) {
; CHECK-SD-LABEL: mulv_v16i16:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: mul v0.8h, v0.8h, v1.8h
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: mul v0.4h, v0.4h, v1.4h
; CHECK-SD-NEXT: umov w8, v0.h[1]
; CHECK-SD-NEXT: umov w9, v0.h[0]
@@ -372,7 +372,7 @@ define i32 @mulv_v3i32(<3 x i32> %a) {
; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: mov v1.s[3], w8
-; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT: mov d1, v1.d[1]
; CHECK-NEXT: mul v0.2s, v0.2s, v1.2s
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0
@@ -384,23 +384,14 @@ entry:
}
define i32 @mulv_v4i32(<4 x i32> %a) {
-; CHECK-SD-LABEL: mulv_v4i32:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: mul v0.2s, v0.2s, v1.2s
-; CHECK-SD-NEXT: mov w8, v0.s[1]
-; CHECK-SD-NEXT: fmov w9, s0
-; CHECK-SD-NEXT: mul w0, w9, w8
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: mulv_v4i32:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: mul v0.2s, v0.2s, v1.2s
-; CHECK-GI-NEXT: mov w8, v0.s[1]
-; CHECK-GI-NEXT: fmov w9, s0
-; CHECK-GI-NEXT: mul w0, w9, w8
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: mulv_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov d1, v0.d[1]
+; CHECK-NEXT: mul v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: mov w8, v0.s[1]
+; CHECK-NEXT: fmov w9, s0
+; CHECK-NEXT: mul w0, w9, w8
+; CHECK-NEXT: ret
entry:
%arg1 = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> %a)
ret i32 %arg1
@@ -410,7 +401,7 @@ define i32 @mulv_v8i32(<8 x i32> %a) {
; CHECK-SD-LABEL: mulv_v8i32:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: mul v0.4s, v0.4s, v1.4s
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: mul v0.2s, v0.2s, v1.2s
; CHECK-SD-NEXT: mov w8, v0.s[1]
; CHECK-SD-NEXT: fmov w9, s0
diff --git a/llvm/test/CodeGen/AArch64/aarch64_be-shuffle-vector.ll b/llvm/test/CodeGen/AArch64/aarch64_be-shuffle-vector.ll
index 4e60d99dbed36..f88d88cf1661c 100644
--- a/llvm/test/CodeGen/AArch64/aarch64_be-shuffle-vector.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64_be-shuffle-vector.ll
@@ -6,7 +6,7 @@ define <4 x i16> @test_reconstructshuffle(<16 x i8> %a, <16 x i8> %b) nounwind {
; CHECKLE-LABEL: test_reconstructshuffle:
; CHECKLE: // %bb.0:
; CHECKLE-NEXT: mov b2, v0.b[3]
-; CHECKLE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECKLE-NEXT: mov d1, v1.d[1]
; CHECKLE-NEXT: mov v2.b[2], v0.b[2]
; CHECKLE-NEXT: mov v2.b[4], v0.b[1]
; CHECKLE-NEXT: mov v2.b[6], v0.b[0]
@@ -22,7 +22,7 @@ define <4 x i16> @test_reconstructshuffle(<16 x i8> %a, <16 x i8> %b) nounwind {
; CHECKBE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECKBE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECKBE-NEXT: mov b2, v0.b[3]
-; CHECKBE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECKBE-NEXT: mov d1, v1.d[1]
; CHECKBE-NEXT: mov v2.b[2], v0.b[2]
; CHECKBE-NEXT: mov v2.b[4], v0.b[1]
; CHECKBE-NEXT: mov v2.b[6], v0.b[0]
diff --git a/llvm/test/CodeGen/AArch64/abd-combine.ll b/llvm/test/CodeGen/AArch64/abd-combine.ll
index cdb40ceb46b1e..d632648bbcd11 100644
--- a/llvm/test/CodeGen/AArch64/abd-combine.ll
+++ b/llvm/test/CodeGen/AArch64/abd-combine.ll
@@ -340,7 +340,7 @@ define <8 x i16> @abds_const_lhs(<8 x i16> %src1) {
define <8 x i16> @abds_const_zero(<8 x i16> %src1) {
; CHECK-LABEL: abds_const_zero:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: abs v0.4h, v0.4h
; CHECK-NEXT: abs v1.4h, v1.4h
; CHECK-NEXT: mov v0.d[1], v1.d[0]
diff --git a/llvm/test/CodeGen/AArch64/add-extract.ll b/llvm/test/CodeGen/AArch64/add-extract.ll
index 923bf089f47ba..002b8e52f4199 100644
--- a/llvm/test/CodeGen/AArch64/add-extract.ll
+++ b/llvm/test/CodeGen/AArch64/add-extract.ll
@@ -120,7 +120,7 @@ define i32 @add_i32_ext_load(<1 x i32> %A, ptr %B) nounwind {
define i64 @add_i64_ext_ext_test1(<1 x i64> %A, <2 x i64> %B) nounwind {
; CHECK-SD-LABEL: add_i64_ext_ext_test1:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-SD-NEXT: mov d2, v1.d[1]
; CHECK-SD-NEXT: add d0, d0, d1
; CHECK-SD-NEXT: add d0, d0, d2
; CHECK-SD-NEXT: fmov x0, d0
@@ -145,7 +145,7 @@ define i64 @add_i64_ext_ext_test1(<1 x i64> %A, <2 x i64> %B) nounwind {
define i64 @sub_i64_ext_ext_test1(<1 x i64> %A, <2 x i64> %B) nounwind {
; CHECK-SD-LABEL: sub_i64_ext_ext_test1:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-SD-NEXT: mov d2, v1.d[1]
; CHECK-SD-NEXT: sub d0, d0, d1
; CHECK-SD-NEXT: sub d0, d0, d2
; CHECK-SD-NEXT: fmov x0, d0
diff --git a/llvm/test/CodeGen/AArch64/arm64-ext.ll b/llvm/test/CodeGen/AArch64/arm64-ext.ll
index c3670579c9148..3194fe1d9a9bc 100644
--- a/llvm/test/CodeGen/AArch64/arm64-ext.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-ext.ll
@@ -101,7 +101,7 @@ define <8 x i16> @test_vextRq_undef2(<8 x i16> %tmp1) nounwind {
define <4 x i16> @test_undef(<8 x i16> %tmp1, <8 x i16> %tmp2) {
; CHECK-SD-LABEL: test_undef:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d0, v0.d[1]
; CHECK-SD-NEXT: zip1 v0.4h, v0.4h, v1.4h
; CHECK-SD-NEXT: ret
;
diff --git a/llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll b/llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll
index f08ff2ccf693d..2647993e52de1 100644
--- a/llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll
@@ -7,8 +7,7 @@
define <8 x i8> @v8i8(<16 x i8> %a) nounwind {
; CHECK-SD-LABEL: v8i8:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext.16b v0, v0, v0, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: mov d0, v0[1]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v8i8:
@@ -22,8 +21,7 @@ define <8 x i8> @v8i8(<16 x i8> %a) nounwind {
define <4 x i16> @v4i16(<8 x i16> %a) nounwind {
; CHECK-SD-LABEL: v4i16:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext.16b v0, v0, v0, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: mov d0, v0[1]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v4i16:
@@ -37,8 +35,7 @@ define <4 x i16> @v4i16(<8 x i16> %a) nounwind {
define <2 x i32> @v2i32(<4 x i32> %a) nounwind {
; CHECK-SD-LABEL: v2i32:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext.16b v0, v0, v0, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: mov d0, v0[1]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2i32:
@@ -52,8 +49,7 @@ define <2 x i32> @v2i32(<4 x i32> %a) nounwind {
define <1 x i64> @v1i64(<2 x i64> %a) nounwind {
; CHECK-SD-LABEL: v1i64:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext.16b v0, v0, v0, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: mov d0, v0[1]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v1i64:
@@ -67,8 +63,7 @@ define <1 x i64> @v1i64(<2 x i64> %a) nounwind {
define <1 x ptr> @v1p0(<2 x ptr> %a) nounwind {
; CHECK-SD-LABEL: v1p0:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext.16b v0, v0, v0, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: mov d0, v0[1]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v1p0:
@@ -82,8 +77,7 @@ define <1 x ptr> @v1p0(<2 x ptr> %a) nounwind {
define <2 x float> @v2f32(<4 x float> %a) nounwind {
; CHECK-SD-LABEL: v2f32:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext.16b v0, v0, v0, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: mov d0, v0[1]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2f32:
@@ -97,8 +91,7 @@ define <2 x float> @v2f32(<4 x float> %a) nounwind {
define <1 x double> @v1f64(<2 x double> %a) nounwind {
; CHECK-SD-LABEL: v1f64:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext.16b v0, v0, v0, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: mov d0, v0[1]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v1f64:
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
index 4f3666c58d317..18d745939e478 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
@@ -284,16 +284,10 @@ define <2 x float> @ins4f2(<4 x float> %tmp1, <2 x float> %tmp2) {
}
define <1 x double> @ins2f1(<2 x double> %tmp1, <1 x double> %tmp2) {
-; CHECK-SD-LABEL: ins2f1:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: ins2f1:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d0, v0.d[1]
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: ins2f1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov d0, v0.d[1]
+; CHECK-NEXT: ret
%tmp3 = extractelement <2 x double> %tmp1, i32 1
%tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0
ret <1 x double> %tmp4
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-simd-vget.ll b/llvm/test/CodeGen/AArch64/arm64-neon-simd-vget.ll
index 96d5b5ef85415..dbf19b1d6fa57 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-simd-vget.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-simd-vget.ll
@@ -4,8 +4,7 @@
define <8 x i8> @test_vget_high_s8(<16 x i8> %a) {
; CHECK-LABEL: test_vget_high_s8:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -15,8 +14,7 @@ entry:
define <4 x i16> @test_vget_high_s16(<8 x i16> %a) {
; CHECK-LABEL: test_vget_high_s16:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -26,8 +24,7 @@ entry:
define <2 x i32> @test_vget_high_s32(<4 x i32> %a) {
; CHECK-LABEL: test_vget_high_s32:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -37,8 +34,7 @@ entry:
define <1 x i64> @test_vget_high_s64(<2 x i64> %a) {
; CHECK-LABEL: test_vget_high_s64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <2 x i64> %a, <2 x i64> undef, <1 x i32> <i32 1>
@@ -...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/195010
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