[llvm] [AArch64][GlobalISel] Match G_DUP with undef elements (PR #195237)
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llvm-commits at lists.llvm.org
Fri May 1 01:46:34 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: David Green (davemgreen)
<details>
<summary>Changes</summary>
This helps us match more vector splats that contain undef elements, matching build vectors that contain undef so long as they contain at least 2 duplicate entries.
---
Patch is 121.99 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/195237.diff
20 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64Combine.td (+3-3)
- (modified) llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp (+23-6)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir (+4-5)
- (modified) llvm/test/CodeGen/AArch64/arm64-vhadd.ll (+15-47)
- (modified) llvm/test/CodeGen/AArch64/cttz.ll (+16-25)
- (modified) llvm/test/CodeGen/AArch64/dup.ll (+9)
- (modified) llvm/test/CodeGen/AArch64/fadd-combines.ll (+2-7)
- (modified) llvm/test/CodeGen/AArch64/fcmp.ll (+82-154)
- (modified) llvm/test/CodeGen/AArch64/fcopysign.ll (+8-28)
- (modified) llvm/test/CodeGen/AArch64/fcvt_combine.ll (+8-58)
- (modified) llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll (+3-9)
- (modified) llvm/test/CodeGen/AArch64/fsh.ll (+303-530)
- (modified) llvm/test/CodeGen/AArch64/hadd-combine.ll (+5-8)
- (modified) llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll (+7-17)
- (modified) llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll (+13-32)
- (modified) llvm/test/CodeGen/AArch64/icmp.ll (+3-11)
- (modified) llvm/test/CodeGen/AArch64/rem-by-const.ll (+165-409)
- (modified) llvm/test/CodeGen/AArch64/select_cc.ll (+1-4)
- (modified) llvm/test/CodeGen/AArch64/shift.ll (+1-3)
- (modified) llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll (+15-19)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64Combine.td b/llvm/lib/Target/AArch64/AArch64Combine.td
index 6ca3946cff575..84489ab3d107b 100644
--- a/llvm/lib/Target/AArch64/AArch64Combine.td
+++ b/llvm/lib/Target/AArch64/AArch64Combine.td
@@ -258,10 +258,10 @@ def lower_mulv2s64 : GICombineRule<
>;
def build_vector_to_dup : GICombineRule<
- (defs root:$root),
+ (defs root:$root, register_matchinfo:$matchinfo),
(match (wip_match_opcode G_BUILD_VECTOR):$root,
- [{ return matchBuildVectorToDup(*${root}, MRI); }]),
- (apply [{ applyBuildVectorToDup(*${root}, MRI, B); }])
+ [{ return matchBuildVectorToDup(*${root}, ${matchinfo}, MRI); }]),
+ (apply [{ applyBuildVectorToDup(*${root}, ${matchinfo}, MRI, B); }])
>;
def build_vector_to_vector_insert : GICombineRule<
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index 58aa2cc37c9b2..433de41f997ec 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -846,7 +846,8 @@ void applyScalarizeVectorUnmerge(MachineInstr &MI, MachineRegisterInfo &MRI,
MI.eraseFromParent();
}
-bool matchBuildVectorToDup(MachineInstr &MI, MachineRegisterInfo &MRI) {
+bool matchBuildVectorToDup(MachineInstr &MI, Register &Src,
+ MachineRegisterInfo &MRI) {
assert(MI.getOpcode() == TargetOpcode::G_BUILD_VECTOR);
// Later, during selection, we'll try to match imported patterns using
@@ -855,14 +856,30 @@ bool matchBuildVectorToDup(MachineInstr &MI, MachineRegisterInfo &MRI) {
if (isBuildVectorAllZeros(MI, MRI) || isBuildVectorAllOnes(MI, MRI))
return false;
- return getAArch64VectorSplat(MI, MRI).has_value();
+ // Find buildvector which always uses the same register or undef. Return true
+ // so long as at least 2 registers were found (not all-undef or only 1
+ // non-undef entry).
+ Register Reg = 0;
+ unsigned NumNonUndef = 0;
+ for (const MachineOperand &Op : drop_begin(MI.operands())) {
+ if (getOpcodeDef<GImplicitDef>(Op.getReg(), MRI))
+ continue;
+
+ if (!Reg)
+ Reg = Op.getReg();
+ else if (Op.getReg() != Reg)
+ return false;
+ NumNonUndef++;
+ }
+
+ Src = Reg;
+ return Reg && NumNonUndef > 1;
}
-void applyBuildVectorToDup(MachineInstr &MI, MachineRegisterInfo &MRI,
- MachineIRBuilder &B) {
+void applyBuildVectorToDup(MachineInstr &MI, Register Src,
+ MachineRegisterInfo &MRI, MachineIRBuilder &B) {
B.setInstrAndDebugLoc(MI);
- B.buildInstr(AArch64::G_DUP, {MI.getOperand(0).getReg()},
- {MI.getOperand(1).getReg()});
+ B.buildInstr(AArch64::G_DUP, {MI.getOperand(0).getReg()}, {Src});
MI.eraseFromParent();
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir
index 2ee01b96f0d60..1fcbc7520ab5d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir
@@ -12,17 +12,16 @@ body: |
; LOWER-LABEL: name: same_reg
; LOWER: liveins: $d0
; LOWER-NEXT: {{ $}}
- ; LOWER-NEXT: %r:_(i8) = G_IMPLICIT_DEF
- ; LOWER-NEXT: %build_vector:_(<8 x i8>) = G_DUP %r(i8)
+ ; LOWER-NEXT: [[DEF:%[0-9]+]]:_(<8 x i8>) = G_IMPLICIT_DEF
+ ; LOWER-NEXT: %build_vector:_(<8 x i8>) = COPY [[DEF]](<8 x i8>)
; LOWER-NEXT: $d0 = COPY %build_vector(<8 x i8>)
; LOWER-NEXT: RET_ReallyLR implicit $d0
;
; SELECT-LABEL: name: same_reg
; SELECT: liveins: $d0
; SELECT-NEXT: {{ $}}
- ; SELECT-NEXT: %r:gpr32 = IMPLICIT_DEF
- ; SELECT-NEXT: %build_vector:fpr64 = DUPv8i8gpr %r
- ; SELECT-NEXT: $d0 = COPY %build_vector
+ ; SELECT-NEXT: [[DEF:%[0-9]+]]:fpr64 = IMPLICIT_DEF
+ ; SELECT-NEXT: $d0 = COPY [[DEF]]
; SELECT-NEXT: RET_ReallyLR implicit $d0
%r:_(i8) = G_IMPLICIT_DEF
%build_vector:_(<8 x i8>) = G_BUILD_VECTOR %r, %r, %r, %r, %r, %r, %r, %r
diff --git a/llvm/test/CodeGen/AArch64/arm64-vhadd.ll b/llvm/test/CodeGen/AArch64/arm64-vhadd.ll
index a1a6a08c5051a..8de97b01d5ae4 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vhadd.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vhadd.ll
@@ -2,9 +2,9 @@
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; CHECK-GI: warning: Instruction selection used fallback path for ext_via_i19
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for srhadd_v2i32_trunc
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for urhadd_v2i32_trunc
+; CHECK-GI: warning: Instruction selection used fallback path for ext_via_i19
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for srhadd_v2i32_trunc
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for urhadd_v2i32_trunc
define <8 x i8> @shadd8b(ptr nocapture readonly %A, ptr nocapture readonly %B) {
; CHECK-LABEL: shadd8b:
@@ -1197,15 +1197,11 @@ define <2 x i16> @hadd8x2_sext_asr(<2 x i8> %src1, <2 x i8> %src2) {
; CHECK-GI-LABEL: hadd8x2_sext_asr:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: shl.2s v1, v1, #24
-; CHECK-GI-NEXT: mov w8, #1 // =0x1
; CHECK-GI-NEXT: shl.2s v0, v0, #24
-; CHECK-GI-NEXT: fmov s2, w8
; CHECK-GI-NEXT: sshr.2s v1, v1, #24
-; CHECK-GI-NEXT: mov.h v2[1], w8
; CHECK-GI-NEXT: ssra.2s v1, v0, #24
; CHECK-GI-NEXT: uzp1.4h v0, v1, v0
-; CHECK-GI-NEXT: neg.4h v1, v2
-; CHECK-GI-NEXT: sshl.4h v0, v0, v1
+; CHECK-GI-NEXT: sshr.4h v0, v0, #1
; CHECK-GI-NEXT: ushll.4s v0, v0, #0
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
@@ -1228,15 +1224,11 @@ define <2 x i16> @hadd8x2_zext_asr(<2 x i8> %src1, <2 x i8> %src2) {
; CHECK-GI-LABEL: hadd8x2_zext_asr:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: movi d2, #0x0000ff000000ff
-; CHECK-GI-NEXT: mov w8, #1 // =0x1
; CHECK-GI-NEXT: and.8b v0, v0, v2
; CHECK-GI-NEXT: and.8b v1, v1, v2
-; CHECK-GI-NEXT: fmov s2, w8
; CHECK-GI-NEXT: add.2s v0, v0, v1
-; CHECK-GI-NEXT: mov.h v2[1], w8
; CHECK-GI-NEXT: uzp1.4h v0, v0, v0
-; CHECK-GI-NEXT: neg.4h v1, v2
-; CHECK-GI-NEXT: ushl.4h v0, v0, v1
+; CHECK-GI-NEXT: ushr.4h v0, v0, #1
; CHECK-GI-NEXT: ushll.4s v0, v0, #0
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
@@ -1262,15 +1254,11 @@ define <2 x i16> @hadd8x2_sext_lsr(<2 x i8> %src1, <2 x i8> %src2) {
; CHECK-GI-LABEL: hadd8x2_sext_lsr:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: shl.2s v1, v1, #24
-; CHECK-GI-NEXT: mov w8, #1 // =0x1
; CHECK-GI-NEXT: shl.2s v0, v0, #24
-; CHECK-GI-NEXT: fmov s2, w8
; CHECK-GI-NEXT: sshr.2s v1, v1, #24
-; CHECK-GI-NEXT: mov.h v2[1], w8
; CHECK-GI-NEXT: ssra.2s v1, v0, #24
; CHECK-GI-NEXT: uzp1.4h v0, v1, v0
-; CHECK-GI-NEXT: neg.4h v1, v2
-; CHECK-GI-NEXT: ushl.4h v0, v0, v1
+; CHECK-GI-NEXT: ushr.4h v0, v0, #1
; CHECK-GI-NEXT: ushll.4s v0, v0, #0
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
@@ -1293,15 +1281,11 @@ define <2 x i16> @hadd8x2_zext_lsr(<2 x i8> %src1, <2 x i8> %src2) {
; CHECK-GI-LABEL: hadd8x2_zext_lsr:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: movi d2, #0x0000ff000000ff
-; CHECK-GI-NEXT: mov w8, #1 // =0x1
; CHECK-GI-NEXT: and.8b v0, v0, v2
; CHECK-GI-NEXT: and.8b v1, v1, v2
-; CHECK-GI-NEXT: fmov s2, w8
; CHECK-GI-NEXT: add.2s v0, v0, v1
-; CHECK-GI-NEXT: mov.h v2[1], w8
; CHECK-GI-NEXT: uzp1.4h v0, v0, v0
-; CHECK-GI-NEXT: neg.4h v1, v2
-; CHECK-GI-NEXT: ushl.4h v0, v0, v1
+; CHECK-GI-NEXT: ushr.4h v0, v0, #1
; CHECK-GI-NEXT: ushll.4s v0, v0, #0
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
@@ -1436,16 +1420,12 @@ define <2 x i16> @rhadd8x2_sext_asr(<2 x i8> %src1, <2 x i8> %src2) {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: shl.2s v1, v1, #24
; CHECK-GI-NEXT: shl.2s v0, v0, #24
-; CHECK-GI-NEXT: mov w8, #1 // =0x1
; CHECK-GI-NEXT: movi.2s v2, #1
; CHECK-GI-NEXT: sshr.2s v1, v1, #24
; CHECK-GI-NEXT: ssra.2s v1, v0, #24
-; CHECK-GI-NEXT: fmov s0, w8
-; CHECK-GI-NEXT: mov.h v0[1], w8
-; CHECK-GI-NEXT: add.2s v1, v1, v2
-; CHECK-GI-NEXT: uzp1.4h v1, v1, v0
-; CHECK-GI-NEXT: neg.4h v0, v0
-; CHECK-GI-NEXT: sshl.4h v0, v1, v0
+; CHECK-GI-NEXT: add.2s v0, v1, v2
+; CHECK-GI-NEXT: uzp1.4h v0, v0, v0
+; CHECK-GI-NEXT: sshr.4h v0, v0, #1
; CHECK-GI-NEXT: ushll.4s v0, v0, #0
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
@@ -1469,17 +1449,13 @@ define <2 x i16> @rhadd8x2_zext_asr(<2 x i8> %src1, <2 x i8> %src2) {
; CHECK-GI-LABEL: rhadd8x2_zext_asr:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: movi d2, #0x0000ff000000ff
-; CHECK-GI-NEXT: mov w8, #1 // =0x1
; CHECK-GI-NEXT: and.8b v0, v0, v2
; CHECK-GI-NEXT: and.8b v1, v1, v2
; CHECK-GI-NEXT: movi.2s v2, #1
; CHECK-GI-NEXT: add.2s v0, v0, v1
-; CHECK-GI-NEXT: fmov s1, w8
; CHECK-GI-NEXT: add.2s v0, v0, v2
-; CHECK-GI-NEXT: mov.h v1[1], w8
; CHECK-GI-NEXT: uzp1.4h v0, v0, v0
-; CHECK-GI-NEXT: neg.4h v1, v1
-; CHECK-GI-NEXT: ushl.4h v0, v0, v1
+; CHECK-GI-NEXT: ushr.4h v0, v0, #1
; CHECK-GI-NEXT: ushll.4s v0, v0, #0
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
@@ -1509,16 +1485,12 @@ define <2 x i16> @rhadd8x2_sext_lsr(<2 x i8> %src1, <2 x i8> %src2) {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: shl.2s v1, v1, #24
; CHECK-GI-NEXT: shl.2s v0, v0, #24
-; CHECK-GI-NEXT: mov w8, #1 // =0x1
; CHECK-GI-NEXT: movi.2s v2, #1
; CHECK-GI-NEXT: sshr.2s v1, v1, #24
; CHECK-GI-NEXT: ssra.2s v1, v0, #24
-; CHECK-GI-NEXT: fmov s0, w8
-; CHECK-GI-NEXT: mov.h v0[1], w8
-; CHECK-GI-NEXT: add.2s v1, v1, v2
-; CHECK-GI-NEXT: uzp1.4h v1, v1, v0
-; CHECK-GI-NEXT: neg.4h v0, v0
-; CHECK-GI-NEXT: ushl.4h v0, v1, v0
+; CHECK-GI-NEXT: add.2s v0, v1, v2
+; CHECK-GI-NEXT: uzp1.4h v0, v0, v0
+; CHECK-GI-NEXT: ushr.4h v0, v0, #1
; CHECK-GI-NEXT: ushll.4s v0, v0, #0
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
@@ -1542,17 +1514,13 @@ define <2 x i16> @rhadd8x2_zext_lsr(<2 x i8> %src1, <2 x i8> %src2) {
; CHECK-GI-LABEL: rhadd8x2_zext_lsr:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: movi d2, #0x0000ff000000ff
-; CHECK-GI-NEXT: mov w8, #1 // =0x1
; CHECK-GI-NEXT: and.8b v0, v0, v2
; CHECK-GI-NEXT: and.8b v1, v1, v2
; CHECK-GI-NEXT: movi.2s v2, #1
; CHECK-GI-NEXT: add.2s v0, v0, v1
-; CHECK-GI-NEXT: fmov s1, w8
; CHECK-GI-NEXT: add.2s v0, v0, v2
-; CHECK-GI-NEXT: mov.h v1[1], w8
; CHECK-GI-NEXT: uzp1.4h v0, v0, v0
-; CHECK-GI-NEXT: neg.4h v1, v1
-; CHECK-GI-NEXT: ushl.4h v0, v0, v1
+; CHECK-GI-NEXT: ushr.4h v0, v0, #1
; CHECK-GI-NEXT: ushll.4s v0, v0, #0
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/cttz.ll b/llvm/test/CodeGen/AArch64/cttz.ll
index b04e8df455357..a72ebf8a9064a 100644
--- a/llvm/test/CodeGen/AArch64/cttz.ll
+++ b/llvm/test/CodeGen/AArch64/cttz.ll
@@ -61,23 +61,20 @@ define void @v3i8(ptr %p1) {
;
; CHECK-GI-LABEL: v3i8:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: ldr w9, [x0]
-; CHECK-GI-NEXT: mov w8, #65535 // =0xffff
-; CHECK-GI-NEXT: fmov s2, w8
-; CHECK-GI-NEXT: fmov s0, w9
-; CHECK-GI-NEXT: mov v2.h[1], w8
-; CHECK-GI-NEXT: mov b1, v0.b[1]
-; CHECK-GI-NEXT: mov v2.h[2], w8
-; CHECK-GI-NEXT: add x8, x0, #1
-; CHECK-GI-NEXT: fmov w9, s1
-; CHECK-GI-NEXT: mov b1, v0.b[2]
-; CHECK-GI-NEXT: mov v0.h[1], w9
-; CHECK-GI-NEXT: fmov w9, s1
-; CHECK-GI-NEXT: mov v0.h[2], w9
+; CHECK-GI-NEXT: ldr w8, [x0]
+; CHECK-GI-NEXT: movi d0, #0xffffffffffffffff
; CHECK-GI-NEXT: add x9, x0, #2
-; CHECK-GI-NEXT: eor v1.8b, v0.8b, v2.8b
-; CHECK-GI-NEXT: add v0.4h, v0.4h, v2.4h
-; CHECK-GI-NEXT: and v0.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT: fmov s1, w8
+; CHECK-GI-NEXT: mov b2, v1.b[1]
+; CHECK-GI-NEXT: fmov w8, s2
+; CHECK-GI-NEXT: mov b2, v1.b[2]
+; CHECK-GI-NEXT: mov v1.h[1], w8
+; CHECK-GI-NEXT: fmov w8, s2
+; CHECK-GI-NEXT: mov v1.h[2], w8
+; CHECK-GI-NEXT: add x8, x0, #1
+; CHECK-GI-NEXT: eor v2.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT: add v0.4h, v1.4h, v0.4h
+; CHECK-GI-NEXT: and v0.8b, v2.8b, v0.8b
; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
; CHECK-GI-NEXT: cnt v0.8b, v0.8b
; CHECK-GI-NEXT: st1 { v0.b }[0], [x0]
@@ -251,13 +248,10 @@ define void @v3i16(ptr %p1) {
;
; CHECK-GI-LABEL: v3i16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov w8, #65535 // =0xffff
+; CHECK-GI-NEXT: movi d0, #0xffffffffffffffff
; CHECK-GI-NEXT: ldr d1, [x0]
-; CHECK-GI-NEXT: add x9, x0, #4
-; CHECK-GI-NEXT: fmov s0, w8
-; CHECK-GI-NEXT: mov v0.h[1], w8
-; CHECK-GI-NEXT: mov v0.h[2], w8
; CHECK-GI-NEXT: add x8, x0, #2
+; CHECK-GI-NEXT: add x9, x0, #4
; CHECK-GI-NEXT: eor v2.8b, v1.8b, v0.8b
; CHECK-GI-NEXT: add v0.4h, v1.4h, v0.4h
; CHECK-GI-NEXT: and v0.8b, v2.8b, v0.8b
@@ -376,10 +370,7 @@ define <3 x i32> @v3i32(<3 x i32> %d) {
;
; CHECK-GI-LABEL: v3i32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov w8, #-1 // =0xffffffff
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: mov v1.s[1], w8
-; CHECK-GI-NEXT: mov v1.s[2], w8
+; CHECK-GI-NEXT: movi v1.2d, #0xffffffffffffffff
; CHECK-GI-NEXT: eor v2.16b, v0.16b, v1.16b
; CHECK-GI-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-GI-NEXT: and v0.16b, v2.16b, v0.16b
diff --git a/llvm/test/CodeGen/AArch64/dup.ll b/llvm/test/CodeGen/AArch64/dup.ll
index 8b8d4392461c8..d4da0e8038cd4 100644
--- a/llvm/test/CodeGen/AArch64/dup.ll
+++ b/llvm/test/CodeGen/AArch64/dup.ll
@@ -2731,3 +2731,12 @@ define <16 x i4> @v8i4_to_v16i8(<8 x i4> %a) {
%r = shufflevector <8 x i4> %a, <8 x i4> poison, <16 x i32> zeroinitializer
ret <16 x i4> %r
}
+
+define <4 x i16> @dup_zero_undef_first() {
+; CHECK-LABEL: dup_zero_undef_first:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: ret
+ %i = insertelement <4 x i16> zeroinitializer, i16 undef, i32 0
+ ret <4 x i16> %i
+}
diff --git a/llvm/test/CodeGen/AArch64/fadd-combines.ll b/llvm/test/CodeGen/AArch64/fadd-combines.ll
index 198b0d58d5ba0..bd7dfa55f11fd 100644
--- a/llvm/test/CodeGen/AArch64/fadd-combines.ll
+++ b/llvm/test/CodeGen/AArch64/fadd-combines.ll
@@ -128,9 +128,7 @@ define <4 x float> @fmulnegtwo_vec_undefs(<4 x float> %a, <4 x float> %b) {
; CHECK-GI-LABEL: fmulnegtwo_vec_undefs:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: fmov s2, #-2.00000000
-; CHECK-GI-NEXT: mov v3.s[1], v2.s[0]
-; CHECK-GI-NEXT: mov v3.s[3], v2.s[0]
-; CHECK-GI-NEXT: fmul v1.4s, v1.4s, v3.4s
+; CHECK-GI-NEXT: fmul v1.4s, v1.4s, v2.s[0]
; CHECK-GI-NEXT: fadd v0.4s, v0.4s, v1.4s
; CHECK-GI-NEXT: ret
%mul = fmul <4 x float> %b, <float undef, float -2.0, float undef, float -2.0>
@@ -148,10 +146,7 @@ define <4 x float> @fmulnegtwo_vec_commute_undefs(<4 x float> %a, <4 x float> %b
; CHECK-GI-LABEL: fmulnegtwo_vec_commute_undefs:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: fmov s2, #-2.00000000
-; CHECK-GI-NEXT: fmov s3, #-2.00000000
-; CHECK-GI-NEXT: mov v3.s[2], v2.s[0]
-; CHECK-GI-NEXT: mov v3.s[3], v2.s[0]
-; CHECK-GI-NEXT: fmul v1.4s, v1.4s, v3.4s
+; CHECK-GI-NEXT: fmul v1.4s, v1.4s, v2.s[0]
; CHECK-GI-NEXT: fadd v0.4s, v1.4s, v0.4s
; CHECK-GI-NEXT: ret
%mul = fmul <4 x float> %b, <float -2.0, float undef, float -2.0, float -2.0>
diff --git a/llvm/test/CodeGen/AArch64/fcmp.ll b/llvm/test/CodeGen/AArch64/fcmp.ll
index d360a9da7d966..3e443a1cf9111 100644
--- a/llvm/test/CodeGen/AArch64/fcmp.ll
+++ b/llvm/test/CodeGen/AArch64/fcmp.ll
@@ -925,26 +925,18 @@ define <3 x i32> @v3f64_i32(<3 x double> %a, <3 x double> %b, <3 x i32> %d, <3 x
; CHECK-GI-NEXT: // kill: def $d3 killed $d3 def $q3
; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-GI-NEXT: // kill: def $d4 killed $d4 def $q4
-; CHECK-GI-NEXT: mov w8, #31 // =0x1f
; CHECK-GI-NEXT: fcmp d2, d5
; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: mov v3.d[1], v4.d[0]
+; CHECK-GI-NEXT: cset w8, mi
; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: cset w9, mi
-; CHECK-GI-NEXT: mov v1.s[1], w8
-; CHECK-GI-NEXT: fmov s2, w9
; CHECK-GI-NEXT: fcmgt v0.2d, v3.2d, v0.2d
-; CHECK-GI-NEXT: mov v1.s[2], w8
-; CHECK-GI-NEXT: mov w8, #-1 // =0xffffffff
; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: mov v0.d[1], v2.d[0]
-; CHECK-GI-NEXT: fmov s2, w8
-; CHECK-GI-NEXT: mov v2.s[1], w8
-; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: neg v1.4s, v1.4s
-; CHECK-GI-NEXT: mov v2.s[2], w8
-; CHECK-GI-NEXT: sshl v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: eor v1.16b, v0.16b, v2.16b
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: movi v1.2d, #0xffffffffffffffff
+; CHECK-GI-NEXT: shl v0.4s, v0.4s, #31
+; CHECK-GI-NEXT: cmlt v0.4s, v0.4s, #0
+; CHECK-GI-NEXT: eor v1.16b, v0.16b, v1.16b
; CHECK-GI-NEXT: and v0.16b, v6.16b, v0.16b
; CHECK-GI-NEXT: and v1.16b, v7.16b, v1.16b
; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
@@ -998,18 +990,10 @@ define <3 x float> @v3f32_float(<3 x float> %a, <3 x float> %b, <3 x float> %d,
;
; CHECK-GI-LABEL: v3f32_float:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov w8, #31 // =0x1f
; CHECK-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s
-; CHECK-GI-NEXT: fmov s4, w8
-; CHECK-GI-NEXT: mov v4.s[1], w8
-; CHECK-GI-NEXT: mov v4.s[2], w8
-; CHECK-GI-NEXT: mov w8, #-1 // =0xffffffff
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: mov v1.s[1], w8
-; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v4.4s
-; CHECK-GI-NEXT: neg v4.4s, v4.4s
-; CHECK-GI-NEXT: sshl v0.4s, v0.4s, v4.4s
-; CHECK-GI-NEXT: mov v1.s[2], w8
+; CHECK-GI-NEXT: movi v1.2d, #0xffffffffffffffff
+; CHECK-GI-NEXT: shl v0.4s, v0.4s, #31
+; CHECK-GI-NEXT: cmlt v0.4s, v0.4s, #0
; CHECK-GI-NEXT: eor v1.16b, v0.16b, v1.16b
; CHECK-GI-NEXT: and v0.16b, v2.16b, v0.16b
; CHECK-GI-NEXT: and v1.16b, v3.16b, v1.16b
@@ -1076,18 +1060,10 @@ define <3 x i32> @v3f32_i32(<3 x float> %a, <3 x float> %b, <3 x i32> %d, <3 x i
;
; CHECK-GI-LABEL: v3f32_i32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov w8, #31 // =0x1f
; CHECK-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s
-; CHECK-GI-NEXT: fmov s4, w8
-; CHECK-GI-NEXT: mov v4.s[1], w8
-; CHECK-GI-NEXT: mov v4.s[2], w8
-; CHECK-GI-NEXT: mov w8, #-1 // =0xffffffff
-; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: mov v1.s[1], w8
-; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v4.4s
-; CHECK-GI-NEXT: neg v4.4s, v4.4s
-; CHECK-GI-NEXT: sshl v0.4s, v0.4s, v4.4s
-; CHECK-GI-NEXT: mov v1.s[2], w8
+; CHECK-GI-NEXT: movi v1.2d, #0xffffffffffffffff
+; CHECK-GI-NEXT: shl v0.4s, v0.4s, #31
+; CHECK-GI-NEXT: cmlt v0.4s, v0.4s, #0
; CHECK-GI-NEXT: eor v1.16b, v0.16b, v1.16b
; CHECK-GI-NEXT: and v0.16b, v2.16b, v0.16b
; CHECK-GI-NEXT: and v1.16b, v3.16b, v1.16b
@@ -1154,39 +1130,23 @@ define <7 x half> @v7f16_half(<7 x half> %a, <7 x half> %b, <7 x half> %d, <7 x
;
; CHECK-GI-NOFP16-LABEL: v7f16_half:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: mov w8, #15 // =0xf
; CHECK-GI-NOFP16-NEXT: mov v4.h[0], v0.h[4]
-; CHECK-GI-NOFP16-NEXT: mov v6.h[0], v1.h[4]
-; CHECK-GI-NOFP16-NEXT: fmov s5, w8
-; CHECK-GI-NOFP16-NEXT: mov w9, #65535 // =0xffff
-; CHECK-GI-NOFP16-NEXT: fmov s7, w9
-; CHECK-GI-NOFP16-NEXT: mov v5.h[1], w8
+; CHECK-GI-NOFP16-NEXT: mov v5.h[0], v1.h[4]
; CHECK-GI-NOFP16-NEXT: mov v4.h[1], v0.h[5]
-; CHECK-GI-NOFP16-NEXT: mov v6.h[1], v1.h[5]
-; CHECK-GI-NOFP16-NEXT: mov v7.h[1], w9
-; CHECK-GI-NOFP16-NEXT: mov v5.h[2], w8
+; C...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/195237
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