[llvm] [AArch64][GlobalISel] Normalize and cleanup test check lines. NFC (PR #195234)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Fri May 1 01:27:32 PDT 2026
https://github.com/davemgreen created https://github.com/llvm/llvm-project/pull/195234
None
>From 15dfdf6d8e24730ff1281a6c96e31c4c69b300c1 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Fri, 1 May 2026 09:27:19 +0100
Subject: [PATCH] [AArch64][GlobalISel] Normalize and cleanup test check lines.
NFC
---
llvm/test/CodeGen/AArch64/bool-ext-inc.ll | 102 +--
llvm/test/CodeGen/AArch64/call-rv-marker.ll | 852 ++++++++----------
.../CodeGen/AArch64/fast-isel-const-float.ll | 2 -
.../CodeGen/AArch64/fold-global-offsets.ll | 74 +-
llvm/test/CodeGen/AArch64/fpmode.ll | 82 +-
llvm/test/CodeGen/AArch64/mul_pow2.ll | 602 ++++---------
llvm/test/CodeGen/AArch64/reduce-and.ll | 827 +++++++++--------
llvm/test/CodeGen/AArch64/reduce-or.ll | 829 +++++++++--------
llvm/test/CodeGen/AArch64/reduce-xor.ll | 809 ++++++++---------
9 files changed, 1892 insertions(+), 2287 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/bool-ext-inc.ll b/llvm/test/CodeGen/AArch64/bool-ext-inc.ll
index 65c2cd85b71a9..26078008a54f6 100644
--- a/llvm/test/CodeGen/AArch64/bool-ext-inc.ll
+++ b/llvm/test/CodeGen/AArch64/bool-ext-inc.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
-; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=1 | FileCheck %s --check-prefix=GISEL
+; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define <4 x i32> @sextbool_add_vector(<4 x i32> %c1, <4 x i32> %c2, <4 x i32> %x) {
; CHECK-LABEL: sextbool_add_vector:
@@ -8,12 +8,6 @@ define <4 x i32> @sextbool_add_vector(<4 x i32> %c1, <4 x i32> %c2, <4 x i32> %x
; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s
; CHECK-NEXT: add v0.4s, v2.4s, v0.4s
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: sextbool_add_vector:
-; GISEL: // %bb.0:
-; GISEL-NEXT: cmeq v0.4s, v0.4s, v1.4s
-; GISEL-NEXT: add v0.4s, v2.4s, v0.4s
-; GISEL-NEXT: ret
%c = icmp eq <4 x i32> %c1, %c2
%b = sext <4 x i1> %c to <4 x i32>
%s = add <4 x i32> %x, %b
@@ -21,19 +15,19 @@ define <4 x i32> @sextbool_add_vector(<4 x i32> %c1, <4 x i32> %c2, <4 x i32> %x
}
define <4 x i32> @zextbool_sub_vector(<4 x i32> %c1, <4 x i32> %c2, <4 x i32> %x) {
-; CHECK-LABEL: zextbool_sub_vector:
-; CHECK: // %bb.0:
-; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s
-; CHECK-NEXT: add v0.4s, v2.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: zextbool_sub_vector:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT: add v0.4s, v2.4s, v0.4s
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: zextbool_sub_vector:
-; GISEL: // %bb.0:
-; GISEL-NEXT: movi v3.4s, #1
-; GISEL-NEXT: cmeq v0.4s, v0.4s, v1.4s
-; GISEL-NEXT: and v0.16b, v0.16b, v3.16b
-; GISEL-NEXT: sub v0.4s, v2.4s, v0.4s
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: zextbool_sub_vector:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v3.4s, #1
+; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v3.16b
+; CHECK-GI-NEXT: sub v0.4s, v2.4s, v0.4s
+; CHECK-GI-NEXT: ret
%c = icmp eq <4 x i32> %c1, %c2
%b = zext <4 x i1> %c to <4 x i32>
%s = sub <4 x i32> %x, %b
@@ -41,48 +35,48 @@ define <4 x i32> @zextbool_sub_vector(<4 x i32> %c1, <4 x i32> %c2, <4 x i32> %x
}
define i32 @assertsext_sub_1(i1 signext %cond, i32 %y) {
-; CHECK-LABEL: assertsext_sub_1:
-; CHECK: // %bb.0:
-; CHECK-NEXT: add w0, w1, w0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: assertsext_sub_1:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: add w0, w1, w0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: assertsext_sub_1:
-; GISEL: // %bb.0:
-; GISEL-NEXT: and w8, w0, #0x1
-; GISEL-NEXT: sub w0, w1, w8
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: assertsext_sub_1:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: and w8, w0, #0x1
+; CHECK-GI-NEXT: sub w0, w1, w8
+; CHECK-GI-NEXT: ret
%e = zext i1 %cond to i32
%r = sub i32 %y, %e
ret i32 %r
}
define i32 @assertsext_add_1(i1 signext %cond, i32 %y) {
-; CHECK-LABEL: assertsext_add_1:
-; CHECK: // %bb.0:
-; CHECK-NEXT: sub w0, w1, w0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: assertsext_add_1:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sub w0, w1, w0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: assertsext_add_1:
-; GISEL: // %bb.0:
-; GISEL-NEXT: and w8, w0, #0x1
-; GISEL-NEXT: add w0, w8, w1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: assertsext_add_1:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: and w8, w0, #0x1
+; CHECK-GI-NEXT: add w0, w8, w1
+; CHECK-GI-NEXT: ret
%e = zext i1 %cond to i32
%r = add i32 %e, %y
ret i32 %r
}
define i32 @assertsext_add_1_commute(i1 signext %cond, i32 %y) {
-; CHECK-LABEL: assertsext_add_1_commute:
-; CHECK: // %bb.0:
-; CHECK-NEXT: sub w0, w1, w0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: assertsext_add_1_commute:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sub w0, w1, w0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: assertsext_add_1_commute:
-; GISEL: // %bb.0:
-; GISEL-NEXT: and w8, w0, #0x1
-; GISEL-NEXT: add w0, w1, w8
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: assertsext_add_1_commute:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: and w8, w0, #0x1
+; CHECK-GI-NEXT: add w0, w1, w8
+; CHECK-GI-NEXT: ret
%e = zext i1 %cond to i32
%r = add i32 %y, %e
ret i32 %r
@@ -92,10 +86,6 @@ define i32 @callee_signext_i1(i1 signext %0) {
; CHECK-LABEL: callee_signext_i1:
; CHECK: // %bb.0:
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: callee_signext_i1:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ret
%r = sext i1 %0 to i32
ret i32 %r
}
@@ -110,16 +100,6 @@ define i32 @caller_signext_i1() {
; CHECK-NEXT: bl callee_signext_i1
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: caller_signext_i1:
-; GISEL: // %bb.0:
-; GISEL-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; GISEL-NEXT: .cfi_def_cfa_offset 16
-; GISEL-NEXT: .cfi_offset w30, -16
-; GISEL-NEXT: mov w0, #-1 // =0xffffffff
-; GISEL-NEXT: bl callee_signext_i1
-; GISEL-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; GISEL-NEXT: ret
%r = call i32 @callee_signext_i1(i1 signext true)
ret i32 %r
}
diff --git a/llvm/test/CodeGen/AArch64/call-rv-marker.ll b/llvm/test/CodeGen/AArch64/call-rv-marker.ll
index 0bc64498da324..fa291e6c7cd74 100644
--- a/llvm/test/CodeGen/AArch64/call-rv-marker.ll
+++ b/llvm/test/CodeGen/AArch64/call-rv-marker.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -o - %s | FileCheck --check-prefix=SELDAG --check-prefix=CHECK %s
-; RUN: llc -global-isel -o - %s | FileCheck --check-prefix=GISEL --check-prefix=CHECK %s
+; RUN: llc -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -global-isel -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-ios"
@@ -26,93 +26,54 @@ declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture)
@fptr = dso_local global ptr null, align 8
define dso_local ptr @rv_marker_1_retain() {
-; SELDAG-LABEL: rv_marker_1_retain:
-; SELDAG: ; %bb.0: ; %entry
-; SELDAG-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
-; SELDAG-NEXT: .cfi_def_cfa_offset 16
-; SELDAG-NEXT: .cfi_offset w30, -8
-; SELDAG-NEXT: .cfi_offset w29, -16
-; SELDAG-NEXT: bl _foo1
-; SELDAG-NEXT: mov x29, x29
-; SELDAG-NEXT: bl _objc_retainAutoreleasedReturnValue
-; SELDAG-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
-; SELDAG-NEXT: ret
-;
-; GISEL-LABEL: rv_marker_1_retain:
-; GISEL: ; %bb.0: ; %entry
-; GISEL-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
-; GISEL-NEXT: .cfi_def_cfa_offset 16
-; GISEL-NEXT: .cfi_offset w30, -8
-; GISEL-NEXT: .cfi_offset w29, -16
-; GISEL-NEXT: bl _foo1
-; GISEL-NEXT: mov x29, x29
-; GISEL-NEXT: bl _objc_retainAutoreleasedReturnValue
-; GISEL-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
-; GISEL-NEXT: ret
+; CHECK-LABEL: rv_marker_1_retain:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -8
+; CHECK-NEXT: .cfi_offset w29, -16
+; CHECK-NEXT: bl _foo1
+; CHECK-NEXT: mov x29, x29
+; CHECK-NEXT: bl _objc_retainAutoreleasedReturnValue
+; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
+; CHECK-NEXT: ret
entry:
%call = call ptr @foo1() [ "clang.arc.attachedcall"(ptr @objc_retainAutoreleasedReturnValue) ]
ret ptr %call
}
define dso_local ptr @rv_marker_1_unsafeClaim() {
-; SELDAG-LABEL: rv_marker_1_unsafeClaim:
-; SELDAG: ; %bb.0: ; %entry
-; SELDAG-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
-; SELDAG-NEXT: .cfi_def_cfa_offset 16
-; SELDAG-NEXT: .cfi_offset w30, -8
-; SELDAG-NEXT: .cfi_offset w29, -16
-; SELDAG-NEXT: bl _foo1
-; SELDAG-NEXT: mov x29, x29
-; SELDAG-NEXT: bl _objc_unsafeClaimAutoreleasedReturnValue
-; SELDAG-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
-; SELDAG-NEXT: ret
-;
-; GISEL-LABEL: rv_marker_1_unsafeClaim:
-; GISEL: ; %bb.0: ; %entry
-; GISEL-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
-; GISEL-NEXT: .cfi_def_cfa_offset 16
-; GISEL-NEXT: .cfi_offset w30, -8
-; GISEL-NEXT: .cfi_offset w29, -16
-; GISEL-NEXT: bl _foo1
-; GISEL-NEXT: mov x29, x29
-; GISEL-NEXT: bl _objc_unsafeClaimAutoreleasedReturnValue
-; GISEL-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
-; GISEL-NEXT: ret
+; CHECK-LABEL: rv_marker_1_unsafeClaim:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -8
+; CHECK-NEXT: .cfi_offset w29, -16
+; CHECK-NEXT: bl _foo1
+; CHECK-NEXT: mov x29, x29
+; CHECK-NEXT: bl _objc_unsafeClaimAutoreleasedReturnValue
+; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
+; CHECK-NEXT: ret
entry:
%call = call ptr @foo1() [ "clang.arc.attachedcall"(ptr @objc_unsafeClaimAutoreleasedReturnValue) ]
ret ptr %call
}
define dso_local void @rv_marker_2_select(i32 %c) {
-; SELDAG-LABEL: rv_marker_2_select:
-; SELDAG: ; %bb.0: ; %entry
-; SELDAG-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
-; SELDAG-NEXT: .cfi_def_cfa_offset 16
-; SELDAG-NEXT: .cfi_offset w30, -8
-; SELDAG-NEXT: .cfi_offset w29, -16
-; SELDAG-NEXT: mov w8, #1 ; =0x1
-; SELDAG-NEXT: cmp w0, #0
-; SELDAG-NEXT: cinc w0, w8, eq
-; SELDAG-NEXT: bl _foo0
-; SELDAG-NEXT: mov x29, x29
-; SELDAG-NEXT: bl _objc_retainAutoreleasedReturnValue
-; SELDAG-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
-; SELDAG-NEXT: b _foo2
-;
-; GISEL-LABEL: rv_marker_2_select:
-; GISEL: ; %bb.0: ; %entry
-; GISEL-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
-; GISEL-NEXT: .cfi_def_cfa_offset 16
-; GISEL-NEXT: .cfi_offset w30, -8
-; GISEL-NEXT: .cfi_offset w29, -16
-; GISEL-NEXT: mov w8, #1 ; =0x1
-; GISEL-NEXT: cmp w0, #0
-; GISEL-NEXT: cinc w0, w8, eq
-; GISEL-NEXT: bl _foo0
-; GISEL-NEXT: mov x29, x29
-; GISEL-NEXT: bl _objc_retainAutoreleasedReturnValue
-; GISEL-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
-; GISEL-NEXT: b _foo2
+; CHECK-LABEL: rv_marker_2_select:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -8
+; CHECK-NEXT: .cfi_offset w29, -16
+; CHECK-NEXT: mov w8, #1 ; =0x1
+; CHECK-NEXT: cmp w0, #0
+; CHECK-NEXT: cinc w0, w8, eq
+; CHECK-NEXT: bl _foo0
+; CHECK-NEXT: mov x29, x29
+; CHECK-NEXT: bl _objc_retainAutoreleasedReturnValue
+; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
+; CHECK-NEXT: b _foo2
entry:
%tobool.not = icmp eq i32 %c, 0
%.sink = select i1 %tobool.not, i32 2, i32 1
@@ -122,131 +83,131 @@ entry:
}
define dso_local void @rv_marker_3() personality ptr @__gxx_personality_v0 {
-; SELDAG-LABEL: rv_marker_3:
-; SELDAG: Lfunc_begin0:
-; SELDAG-NEXT: .cfi_startproc
-; SELDAG-NEXT: .cfi_personality 155, ___gxx_personality_v0
-; SELDAG-NEXT: .cfi_lsda 16, Lexception0
-; SELDAG-NEXT: ; %bb.0: ; %entry
-; SELDAG-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
-; SELDAG-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; SELDAG-NEXT: .cfi_def_cfa_offset 32
-; SELDAG-NEXT: .cfi_offset w30, -8
-; SELDAG-NEXT: .cfi_offset w29, -16
-; SELDAG-NEXT: .cfi_offset w19, -24
-; SELDAG-NEXT: .cfi_offset w20, -32
-; SELDAG-NEXT: bl _foo1
-; SELDAG-NEXT: mov x29, x29
-; SELDAG-NEXT: bl _objc_retainAutoreleasedReturnValue
-; SELDAG-NEXT: mov x19, x0
-; SELDAG-NEXT: Ltmp0: ; EH_LABEL
-; SELDAG-NEXT: bl _objc_object
-; SELDAG-NEXT: Ltmp1: ; EH_LABEL
-; SELDAG-NEXT: ; %bb.1: ; %invoke.cont
-; SELDAG-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
-; SELDAG-NEXT: mov x0, x19
-; SELDAG-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
-; SELDAG-NEXT: b _objc_release
-; SELDAG-NEXT: LBB3_2: ; %lpad
-; SELDAG-NEXT: Ltmp2: ; EH_LABEL
-; SELDAG-NEXT: mov x20, x0
-; SELDAG-NEXT: mov x0, x19
-; SELDAG-NEXT: bl _objc_release
-; SELDAG-NEXT: mov x0, x20
-; SELDAG-NEXT: bl __Unwind_Resume
-; SELDAG-NEXT: Lfunc_end0:
-; SELDAG-NEXT: .cfi_endproc
-; SELDAG-NEXT: .section __TEXT,__gcc_except_tab
-; SELDAG-NEXT: .p2align 2, 0x0
-; SELDAG-NEXT: GCC_except_table3:
-; SELDAG-NEXT: Lexception0:
-; SELDAG-NEXT: .byte 255 ; @LPStart Encoding = omit
-; SELDAG-NEXT: .byte 255 ; @TType Encoding = omit
-; SELDAG-NEXT: .byte 1 ; Call site Encoding = uleb128
-; SELDAG-NEXT: .uleb128 Lcst_end0-Lcst_begin0
-; SELDAG-NEXT: Lcst_begin0:
-; SELDAG-NEXT: .uleb128 Lfunc_begin0-Lfunc_begin0 ; >> Call Site 1 <<
-; SELDAG-NEXT: .uleb128 Ltmp0-Lfunc_begin0 ; Call between Lfunc_begin0 and Ltmp0
-; SELDAG-NEXT: .byte 0 ; has no landing pad
-; SELDAG-NEXT: .byte 0 ; On action: cleanup
-; SELDAG-NEXT: .uleb128 Ltmp0-Lfunc_begin0 ; >> Call Site 2 <<
-; SELDAG-NEXT: .uleb128 Ltmp1-Ltmp0 ; Call between Ltmp0 and Ltmp1
-; SELDAG-NEXT: .uleb128 Ltmp2-Lfunc_begin0 ; jumps to Ltmp2
-; SELDAG-NEXT: .byte 0 ; On action: cleanup
-; SELDAG-NEXT: .uleb128 Ltmp1-Lfunc_begin0 ; >> Call Site 3 <<
-; SELDAG-NEXT: .uleb128 Lfunc_end0-Ltmp1 ; Call between Ltmp1 and Lfunc_end0
-; SELDAG-NEXT: .byte 0 ; has no landing pad
-; SELDAG-NEXT: .byte 0 ; On action: cleanup
-; SELDAG-NEXT: Lcst_end0:
-; SELDAG-NEXT: .p2align 2, 0x0
+; CHECK-SD-LABEL: rv_marker_3:
+; CHECK-SD: Lfunc_begin0:
+; CHECK-SD-NEXT: .cfi_startproc
+; CHECK-SD-NEXT: .cfi_personality 155, ___gxx_personality_v0
+; CHECK-SD-NEXT: .cfi_lsda 16, Lexception0
+; CHECK-SD-NEXT: ; %bb.0: ; %entry
+; CHECK-SD-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
+; CHECK-SD-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 32
+; CHECK-SD-NEXT: .cfi_offset w30, -8
+; CHECK-SD-NEXT: .cfi_offset w29, -16
+; CHECK-SD-NEXT: .cfi_offset w19, -24
+; CHECK-SD-NEXT: .cfi_offset w20, -32
+; CHECK-SD-NEXT: bl _foo1
+; CHECK-SD-NEXT: mov x29, x29
+; CHECK-SD-NEXT: bl _objc_retainAutoreleasedReturnValue
+; CHECK-SD-NEXT: mov x19, x0
+; CHECK-SD-NEXT: Ltmp0: ; EH_LABEL
+; CHECK-SD-NEXT: bl _objc_object
+; CHECK-SD-NEXT: Ltmp1: ; EH_LABEL
+; CHECK-SD-NEXT: ; %bb.1: ; %invoke.cont
+; CHECK-SD-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
+; CHECK-SD-NEXT: mov x0, x19
+; CHECK-SD-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
+; CHECK-SD-NEXT: b _objc_release
+; CHECK-SD-NEXT: LBB3_2: ; %lpad
+; CHECK-SD-NEXT: Ltmp2: ; EH_LABEL
+; CHECK-SD-NEXT: mov x20, x0
+; CHECK-SD-NEXT: mov x0, x19
+; CHECK-SD-NEXT: bl _objc_release
+; CHECK-SD-NEXT: mov x0, x20
+; CHECK-SD-NEXT: bl __Unwind_Resume
+; CHECK-SD-NEXT: Lfunc_end0:
+; CHECK-SD-NEXT: .cfi_endproc
+; CHECK-SD-NEXT: .section __TEXT,__gcc_except_tab
+; CHECK-SD-NEXT: .p2align 2, 0x0
+; CHECK-SD-NEXT: GCC_except_table3:
+; CHECK-SD-NEXT: Lexception0:
+; CHECK-SD-NEXT: .byte 255 ; @LPStart Encoding = omit
+; CHECK-SD-NEXT: .byte 255 ; @TType Encoding = omit
+; CHECK-SD-NEXT: .byte 1 ; Call site Encoding = uleb128
+; CHECK-SD-NEXT: .uleb128 Lcst_end0-Lcst_begin0
+; CHECK-SD-NEXT: Lcst_begin0:
+; CHECK-SD-NEXT: .uleb128 Lfunc_begin0-Lfunc_begin0 ; >> Call Site 1 <<
+; CHECK-SD-NEXT: .uleb128 Ltmp0-Lfunc_begin0 ; Call between Lfunc_begin0 and Ltmp0
+; CHECK-SD-NEXT: .byte 0 ; has no landing pad
+; CHECK-SD-NEXT: .byte 0 ; On action: cleanup
+; CHECK-SD-NEXT: .uleb128 Ltmp0-Lfunc_begin0 ; >> Call Site 2 <<
+; CHECK-SD-NEXT: .uleb128 Ltmp1-Ltmp0 ; Call between Ltmp0 and Ltmp1
+; CHECK-SD-NEXT: .uleb128 Ltmp2-Lfunc_begin0 ; jumps to Ltmp2
+; CHECK-SD-NEXT: .byte 0 ; On action: cleanup
+; CHECK-SD-NEXT: .uleb128 Ltmp1-Lfunc_begin0 ; >> Call Site 3 <<
+; CHECK-SD-NEXT: .uleb128 Lfunc_end0-Ltmp1 ; Call between Ltmp1 and Lfunc_end0
+; CHECK-SD-NEXT: .byte 0 ; has no landing pad
+; CHECK-SD-NEXT: .byte 0 ; On action: cleanup
+; CHECK-SD-NEXT: Lcst_end0:
+; CHECK-SD-NEXT: .p2align 2, 0x0
;
-; GISEL-LABEL: rv_marker_3:
-; GISEL: Lfunc_begin0:
-; GISEL-NEXT: .cfi_startproc
-; GISEL-NEXT: .cfi_personality 155, ___gxx_personality_v0
-; GISEL-NEXT: .cfi_lsda 16, Lexception0
-; GISEL-NEXT: ; %bb.0: ; %entry
-; GISEL-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
-; GISEL-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; GISEL-NEXT: .cfi_def_cfa_offset 32
-; GISEL-NEXT: .cfi_offset w30, -8
-; GISEL-NEXT: .cfi_offset w29, -16
-; GISEL-NEXT: .cfi_offset w19, -24
-; GISEL-NEXT: .cfi_offset w20, -32
-; GISEL-NEXT: bl _foo1
-; GISEL-NEXT: mov x29, x29
-; GISEL-NEXT: bl _objc_retainAutoreleasedReturnValue
-; GISEL-NEXT: mov x19, x0
-; GISEL-NEXT: Ltmp0: ; EH_LABEL
-; GISEL-NEXT: bl _objc_object
-; GISEL-NEXT: Ltmp1: ; EH_LABEL
-; GISEL-NEXT: ; %bb.1: ; %invoke.cont
-; GISEL-NEXT: Lloh0:
-; GISEL-NEXT: adrp x1, _objc_release at GOTPAGE
-; GISEL-NEXT: mov x0, x19
-; GISEL-NEXT: Lloh1:
-; GISEL-NEXT: ldr x1, [x1, _objc_release at GOTPAGEOFF]
-; GISEL-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
-; GISEL-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
-; GISEL-NEXT: br x1
-; GISEL-NEXT: LBB3_2: ; %lpad
-; GISEL-NEXT: Ltmp2: ; EH_LABEL
-; GISEL-NEXT: Lloh2:
-; GISEL-NEXT: adrp x8, _objc_release at GOTPAGE
-; GISEL-NEXT: mov x20, x0
-; GISEL-NEXT: mov x0, x19
-; GISEL-NEXT: Lloh3:
-; GISEL-NEXT: ldr x8, [x8, _objc_release at GOTPAGEOFF]
-; GISEL-NEXT: blr x8
-; GISEL-NEXT: mov x0, x20
-; GISEL-NEXT: bl __Unwind_Resume
-; GISEL-NEXT: .loh AdrpLdrGot Lloh0, Lloh1
-; GISEL-NEXT: .loh AdrpLdrGot Lloh2, Lloh3
-; GISEL-NEXT: Lfunc_end0:
-; GISEL-NEXT: .cfi_endproc
-; GISEL-NEXT: .section __TEXT,__gcc_except_tab
-; GISEL-NEXT: .p2align 2, 0x0
-; GISEL-NEXT: GCC_except_table3:
-; GISEL-NEXT: Lexception0:
-; GISEL-NEXT: .byte 255 ; @LPStart Encoding = omit
-; GISEL-NEXT: .byte 255 ; @TType Encoding = omit
-; GISEL-NEXT: .byte 1 ; Call site Encoding = uleb128
-; GISEL-NEXT: .uleb128 Lcst_end0-Lcst_begin0
-; GISEL-NEXT: Lcst_begin0:
-; GISEL-NEXT: .uleb128 Lfunc_begin0-Lfunc_begin0 ; >> Call Site 1 <<
-; GISEL-NEXT: .uleb128 Ltmp0-Lfunc_begin0 ; Call between Lfunc_begin0 and Ltmp0
-; GISEL-NEXT: .byte 0 ; has no landing pad
-; GISEL-NEXT: .byte 0 ; On action: cleanup
-; GISEL-NEXT: .uleb128 Ltmp0-Lfunc_begin0 ; >> Call Site 2 <<
-; GISEL-NEXT: .uleb128 Ltmp1-Ltmp0 ; Call between Ltmp0 and Ltmp1
-; GISEL-NEXT: .uleb128 Ltmp2-Lfunc_begin0 ; jumps to Ltmp2
-; GISEL-NEXT: .byte 0 ; On action: cleanup
-; GISEL-NEXT: .uleb128 Ltmp1-Lfunc_begin0 ; >> Call Site 3 <<
-; GISEL-NEXT: .uleb128 Lfunc_end0-Ltmp1 ; Call between Ltmp1 and Lfunc_end0
-; GISEL-NEXT: .byte 0 ; has no landing pad
-; GISEL-NEXT: .byte 0 ; On action: cleanup
-; GISEL-NEXT: Lcst_end0:
-; GISEL-NEXT: .p2align 2, 0x0
+; CHECK-GI-LABEL: rv_marker_3:
+; CHECK-GI: Lfunc_begin0:
+; CHECK-GI-NEXT: .cfi_startproc
+; CHECK-GI-NEXT: .cfi_personality 155, ___gxx_personality_v0
+; CHECK-GI-NEXT: .cfi_lsda 16, Lexception0
+; CHECK-GI-NEXT: ; %bb.0: ; %entry
+; CHECK-GI-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-GI-NEXT: .cfi_offset w30, -8
+; CHECK-GI-NEXT: .cfi_offset w29, -16
+; CHECK-GI-NEXT: .cfi_offset w19, -24
+; CHECK-GI-NEXT: .cfi_offset w20, -32
+; CHECK-GI-NEXT: bl _foo1
+; CHECK-GI-NEXT: mov x29, x29
+; CHECK-GI-NEXT: bl _objc_retainAutoreleasedReturnValue
+; CHECK-GI-NEXT: mov x19, x0
+; CHECK-GI-NEXT: Ltmp0: ; EH_LABEL
+; CHECK-GI-NEXT: bl _objc_object
+; CHECK-GI-NEXT: Ltmp1: ; EH_LABEL
+; CHECK-GI-NEXT: ; %bb.1: ; %invoke.cont
+; CHECK-GI-NEXT: Lloh0:
+; CHECK-GI-NEXT: adrp x1, _objc_release at GOTPAGE
+; CHECK-GI-NEXT: mov x0, x19
+; CHECK-GI-NEXT: Lloh1:
+; CHECK-GI-NEXT: ldr x1, [x1, _objc_release at GOTPAGEOFF]
+; CHECK-GI-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
+; CHECK-GI-NEXT: br x1
+; CHECK-GI-NEXT: LBB3_2: ; %lpad
+; CHECK-GI-NEXT: Ltmp2: ; EH_LABEL
+; CHECK-GI-NEXT: Lloh2:
+; CHECK-GI-NEXT: adrp x8, _objc_release at GOTPAGE
+; CHECK-GI-NEXT: mov x20, x0
+; CHECK-GI-NEXT: mov x0, x19
+; CHECK-GI-NEXT: Lloh3:
+; CHECK-GI-NEXT: ldr x8, [x8, _objc_release at GOTPAGEOFF]
+; CHECK-GI-NEXT: blr x8
+; CHECK-GI-NEXT: mov x0, x20
+; CHECK-GI-NEXT: bl __Unwind_Resume
+; CHECK-GI-NEXT: .loh AdrpLdrGot Lloh0, Lloh1
+; CHECK-GI-NEXT: .loh AdrpLdrGot Lloh2, Lloh3
+; CHECK-GI-NEXT: Lfunc_end0:
+; CHECK-GI-NEXT: .cfi_endproc
+; CHECK-GI-NEXT: .section __TEXT,__gcc_except_tab
+; CHECK-GI-NEXT: .p2align 2, 0x0
+; CHECK-GI-NEXT: GCC_except_table3:
+; CHECK-GI-NEXT: Lexception0:
+; CHECK-GI-NEXT: .byte 255 ; @LPStart Encoding = omit
+; CHECK-GI-NEXT: .byte 255 ; @TType Encoding = omit
+; CHECK-GI-NEXT: .byte 1 ; Call site Encoding = uleb128
+; CHECK-GI-NEXT: .uleb128 Lcst_end0-Lcst_begin0
+; CHECK-GI-NEXT: Lcst_begin0:
+; CHECK-GI-NEXT: .uleb128 Lfunc_begin0-Lfunc_begin0 ; >> Call Site 1 <<
+; CHECK-GI-NEXT: .uleb128 Ltmp0-Lfunc_begin0 ; Call between Lfunc_begin0 and Ltmp0
+; CHECK-GI-NEXT: .byte 0 ; has no landing pad
+; CHECK-GI-NEXT: .byte 0 ; On action: cleanup
+; CHECK-GI-NEXT: .uleb128 Ltmp0-Lfunc_begin0 ; >> Call Site 2 <<
+; CHECK-GI-NEXT: .uleb128 Ltmp1-Ltmp0 ; Call between Ltmp0 and Ltmp1
+; CHECK-GI-NEXT: .uleb128 Ltmp2-Lfunc_begin0 ; jumps to Ltmp2
+; CHECK-GI-NEXT: .byte 0 ; On action: cleanup
+; CHECK-GI-NEXT: .uleb128 Ltmp1-Lfunc_begin0 ; >> Call Site 3 <<
+; CHECK-GI-NEXT: .uleb128 Lfunc_end0-Ltmp1 ; Call between Ltmp1 and Lfunc_end0
+; CHECK-GI-NEXT: .byte 0 ; has no landing pad
+; CHECK-GI-NEXT: .byte 0 ; On action: cleanup
+; CHECK-GI-NEXT: Lcst_end0:
+; CHECK-GI-NEXT: .p2align 2, 0x0
entry:
%call = call ptr @foo1() [ "clang.arc.attachedcall"(ptr @objc_retainAutoreleasedReturnValue) ]
invoke void @objc_object(ptr %call) #5
@@ -264,161 +225,161 @@ lpad: ; preds = %entry
}
define dso_local void @rv_marker_4() personality ptr @__gxx_personality_v0 {
-; SELDAG-LABEL: rv_marker_4:
-; SELDAG: Lfunc_begin1:
-; SELDAG-NEXT: .cfi_startproc
-; SELDAG-NEXT: .cfi_personality 155, ___gxx_personality_v0
-; SELDAG-NEXT: .cfi_lsda 16, Lexception1
-; SELDAG-NEXT: ; %bb.0: ; %entry
-; SELDAG-NEXT: sub sp, sp, #48
-; SELDAG-NEXT: stp x20, x19, [sp, #16] ; 16-byte Folded Spill
-; SELDAG-NEXT: stp x29, x30, [sp, #32] ; 16-byte Folded Spill
-; SELDAG-NEXT: .cfi_def_cfa_offset 48
-; SELDAG-NEXT: .cfi_offset w30, -8
-; SELDAG-NEXT: .cfi_offset w29, -16
-; SELDAG-NEXT: .cfi_offset w19, -24
-; SELDAG-NEXT: .cfi_offset w20, -32
-; SELDAG-NEXT: Ltmp3: ; EH_LABEL
-; SELDAG-NEXT: bl _foo1
-; SELDAG-NEXT: mov x29, x29
-; SELDAG-NEXT: bl _objc_retainAutoreleasedReturnValue
-; SELDAG-NEXT: Ltmp4: ; EH_LABEL
-; SELDAG-NEXT: ; %bb.1: ; %invoke.cont
-; SELDAG-NEXT: Ltmp6: ; EH_LABEL
-; SELDAG-NEXT: mov x19, x0
-; SELDAG-NEXT: bl _objc_object
-; SELDAG-NEXT: Ltmp7: ; EH_LABEL
-; SELDAG-NEXT: ; %bb.2: ; %invoke.cont2
-; SELDAG-NEXT: mov x0, x19
-; SELDAG-NEXT: bl _objc_release
-; SELDAG-NEXT: add x0, sp, #15
-; SELDAG-NEXT: bl __ZN1SD1Ev
-; SELDAG-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload
-; SELDAG-NEXT: ldp x20, x19, [sp, #16] ; 16-byte Folded Reload
-; SELDAG-NEXT: add sp, sp, #48
-; SELDAG-NEXT: ret
-; SELDAG-NEXT: LBB4_3: ; %lpad1
-; SELDAG-NEXT: Ltmp8: ; EH_LABEL
-; SELDAG-NEXT: mov x20, x0
-; SELDAG-NEXT: mov x0, x19
-; SELDAG-NEXT: bl _objc_release
-; SELDAG-NEXT: b LBB4_5
-; SELDAG-NEXT: LBB4_4: ; %lpad
-; SELDAG-NEXT: Ltmp5: ; EH_LABEL
-; SELDAG-NEXT: mov x20, x0
-; SELDAG-NEXT: LBB4_5: ; %ehcleanup
-; SELDAG-NEXT: add x0, sp, #15
-; SELDAG-NEXT: bl __ZN1SD1Ev
-; SELDAG-NEXT: mov x0, x20
-; SELDAG-NEXT: bl __Unwind_Resume
-; SELDAG-NEXT: Lfunc_end1:
-; SELDAG-NEXT: .cfi_endproc
-; SELDAG-NEXT: .section __TEXT,__gcc_except_tab
-; SELDAG-NEXT: .p2align 2, 0x0
-; SELDAG-NEXT: GCC_except_table4:
-; SELDAG-NEXT: Lexception1:
-; SELDAG-NEXT: .byte 255 ; @LPStart Encoding = omit
-; SELDAG-NEXT: .byte 255 ; @TType Encoding = omit
-; SELDAG-NEXT: .byte 1 ; Call site Encoding = uleb128
-; SELDAG-NEXT: .uleb128 Lcst_end1-Lcst_begin1
-; SELDAG-NEXT: Lcst_begin1:
-; SELDAG-NEXT: .uleb128 Ltmp3-Lfunc_begin1 ; >> Call Site 1 <<
-; SELDAG-NEXT: .uleb128 Ltmp4-Ltmp3 ; Call between Ltmp3 and Ltmp4
-; SELDAG-NEXT: .uleb128 Ltmp5-Lfunc_begin1 ; jumps to Ltmp5
-; SELDAG-NEXT: .byte 0 ; On action: cleanup
-; SELDAG-NEXT: .uleb128 Ltmp6-Lfunc_begin1 ; >> Call Site 2 <<
-; SELDAG-NEXT: .uleb128 Ltmp7-Ltmp6 ; Call between Ltmp6 and Ltmp7
-; SELDAG-NEXT: .uleb128 Ltmp8-Lfunc_begin1 ; jumps to Ltmp8
-; SELDAG-NEXT: .byte 0 ; On action: cleanup
-; SELDAG-NEXT: .uleb128 Ltmp7-Lfunc_begin1 ; >> Call Site 3 <<
-; SELDAG-NEXT: .uleb128 Lfunc_end1-Ltmp7 ; Call between Ltmp7 and Lfunc_end1
-; SELDAG-NEXT: .byte 0 ; has no landing pad
-; SELDAG-NEXT: .byte 0 ; On action: cleanup
-; SELDAG-NEXT: Lcst_end1:
-; SELDAG-NEXT: .p2align 2, 0x0
+; CHECK-SD-LABEL: rv_marker_4:
+; CHECK-SD: Lfunc_begin1:
+; CHECK-SD-NEXT: .cfi_startproc
+; CHECK-SD-NEXT: .cfi_personality 155, ___gxx_personality_v0
+; CHECK-SD-NEXT: .cfi_lsda 16, Lexception1
+; CHECK-SD-NEXT: ; %bb.0: ; %entry
+; CHECK-SD-NEXT: sub sp, sp, #48
+; CHECK-SD-NEXT: stp x20, x19, [sp, #16] ; 16-byte Folded Spill
+; CHECK-SD-NEXT: stp x29, x30, [sp, #32] ; 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-SD-NEXT: .cfi_offset w30, -8
+; CHECK-SD-NEXT: .cfi_offset w29, -16
+; CHECK-SD-NEXT: .cfi_offset w19, -24
+; CHECK-SD-NEXT: .cfi_offset w20, -32
+; CHECK-SD-NEXT: Ltmp3: ; EH_LABEL
+; CHECK-SD-NEXT: bl _foo1
+; CHECK-SD-NEXT: mov x29, x29
+; CHECK-SD-NEXT: bl _objc_retainAutoreleasedReturnValue
+; CHECK-SD-NEXT: Ltmp4: ; EH_LABEL
+; CHECK-SD-NEXT: ; %bb.1: ; %invoke.cont
+; CHECK-SD-NEXT: Ltmp6: ; EH_LABEL
+; CHECK-SD-NEXT: mov x19, x0
+; CHECK-SD-NEXT: bl _objc_object
+; CHECK-SD-NEXT: Ltmp7: ; EH_LABEL
+; CHECK-SD-NEXT: ; %bb.2: ; %invoke.cont2
+; CHECK-SD-NEXT: mov x0, x19
+; CHECK-SD-NEXT: bl _objc_release
+; CHECK-SD-NEXT: add x0, sp, #15
+; CHECK-SD-NEXT: bl __ZN1SD1Ev
+; CHECK-SD-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload
+; CHECK-SD-NEXT: ldp x20, x19, [sp, #16] ; 16-byte Folded Reload
+; CHECK-SD-NEXT: add sp, sp, #48
+; CHECK-SD-NEXT: ret
+; CHECK-SD-NEXT: LBB4_3: ; %lpad1
+; CHECK-SD-NEXT: Ltmp8: ; EH_LABEL
+; CHECK-SD-NEXT: mov x20, x0
+; CHECK-SD-NEXT: mov x0, x19
+; CHECK-SD-NEXT: bl _objc_release
+; CHECK-SD-NEXT: b LBB4_5
+; CHECK-SD-NEXT: LBB4_4: ; %lpad
+; CHECK-SD-NEXT: Ltmp5: ; EH_LABEL
+; CHECK-SD-NEXT: mov x20, x0
+; CHECK-SD-NEXT: LBB4_5: ; %ehcleanup
+; CHECK-SD-NEXT: add x0, sp, #15
+; CHECK-SD-NEXT: bl __ZN1SD1Ev
+; CHECK-SD-NEXT: mov x0, x20
+; CHECK-SD-NEXT: bl __Unwind_Resume
+; CHECK-SD-NEXT: Lfunc_end1:
+; CHECK-SD-NEXT: .cfi_endproc
+; CHECK-SD-NEXT: .section __TEXT,__gcc_except_tab
+; CHECK-SD-NEXT: .p2align 2, 0x0
+; CHECK-SD-NEXT: GCC_except_table4:
+; CHECK-SD-NEXT: Lexception1:
+; CHECK-SD-NEXT: .byte 255 ; @LPStart Encoding = omit
+; CHECK-SD-NEXT: .byte 255 ; @TType Encoding = omit
+; CHECK-SD-NEXT: .byte 1 ; Call site Encoding = uleb128
+; CHECK-SD-NEXT: .uleb128 Lcst_end1-Lcst_begin1
+; CHECK-SD-NEXT: Lcst_begin1:
+; CHECK-SD-NEXT: .uleb128 Ltmp3-Lfunc_begin1 ; >> Call Site 1 <<
+; CHECK-SD-NEXT: .uleb128 Ltmp4-Ltmp3 ; Call between Ltmp3 and Ltmp4
+; CHECK-SD-NEXT: .uleb128 Ltmp5-Lfunc_begin1 ; jumps to Ltmp5
+; CHECK-SD-NEXT: .byte 0 ; On action: cleanup
+; CHECK-SD-NEXT: .uleb128 Ltmp6-Lfunc_begin1 ; >> Call Site 2 <<
+; CHECK-SD-NEXT: .uleb128 Ltmp7-Ltmp6 ; Call between Ltmp6 and Ltmp7
+; CHECK-SD-NEXT: .uleb128 Ltmp8-Lfunc_begin1 ; jumps to Ltmp8
+; CHECK-SD-NEXT: .byte 0 ; On action: cleanup
+; CHECK-SD-NEXT: .uleb128 Ltmp7-Lfunc_begin1 ; >> Call Site 3 <<
+; CHECK-SD-NEXT: .uleb128 Lfunc_end1-Ltmp7 ; Call between Ltmp7 and Lfunc_end1
+; CHECK-SD-NEXT: .byte 0 ; has no landing pad
+; CHECK-SD-NEXT: .byte 0 ; On action: cleanup
+; CHECK-SD-NEXT: Lcst_end1:
+; CHECK-SD-NEXT: .p2align 2, 0x0
;
-; GISEL-LABEL: rv_marker_4:
-; GISEL: Lfunc_begin1:
-; GISEL-NEXT: .cfi_startproc
-; GISEL-NEXT: .cfi_personality 155, ___gxx_personality_v0
-; GISEL-NEXT: .cfi_lsda 16, Lexception1
-; GISEL-NEXT: ; %bb.0: ; %entry
-; GISEL-NEXT: sub sp, sp, #48
-; GISEL-NEXT: stp x20, x19, [sp, #16] ; 16-byte Folded Spill
-; GISEL-NEXT: stp x29, x30, [sp, #32] ; 16-byte Folded Spill
-; GISEL-NEXT: .cfi_def_cfa_offset 48
-; GISEL-NEXT: .cfi_offset w30, -8
-; GISEL-NEXT: .cfi_offset w29, -16
-; GISEL-NEXT: .cfi_offset w19, -24
-; GISEL-NEXT: .cfi_offset w20, -32
-; GISEL-NEXT: Ltmp3: ; EH_LABEL
-; GISEL-NEXT: bl _foo1
-; GISEL-NEXT: mov x29, x29
-; GISEL-NEXT: bl _objc_retainAutoreleasedReturnValue
-; GISEL-NEXT: Ltmp4: ; EH_LABEL
-; GISEL-NEXT: ; %bb.1: ; %invoke.cont
-; GISEL-NEXT: Ltmp6: ; EH_LABEL
-; GISEL-NEXT: mov x19, x0
-; GISEL-NEXT: bl _objc_object
-; GISEL-NEXT: Ltmp7: ; EH_LABEL
-; GISEL-NEXT: ; %bb.2: ; %invoke.cont2
-; GISEL-NEXT: Lloh4:
-; GISEL-NEXT: adrp x8, _objc_release at GOTPAGE
-; GISEL-NEXT: mov x0, x19
-; GISEL-NEXT: Lloh5:
-; GISEL-NEXT: ldr x8, [x8, _objc_release at GOTPAGEOFF]
-; GISEL-NEXT: blr x8
-; GISEL-NEXT: add x0, sp, #15
-; GISEL-NEXT: bl __ZN1SD1Ev
-; GISEL-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload
-; GISEL-NEXT: ldp x20, x19, [sp, #16] ; 16-byte Folded Reload
-; GISEL-NEXT: add sp, sp, #48
-; GISEL-NEXT: ret
-; GISEL-NEXT: LBB4_3: ; %lpad1
-; GISEL-NEXT: Ltmp8: ; EH_LABEL
-; GISEL-NEXT: Lloh6:
-; GISEL-NEXT: adrp x8, _objc_release at GOTPAGE
-; GISEL-NEXT: mov x20, x0
-; GISEL-NEXT: mov x0, x19
-; GISEL-NEXT: Lloh7:
-; GISEL-NEXT: ldr x8, [x8, _objc_release at GOTPAGEOFF]
-; GISEL-NEXT: blr x8
-; GISEL-NEXT: b LBB4_5
-; GISEL-NEXT: LBB4_4: ; %lpad
-; GISEL-NEXT: Ltmp5: ; EH_LABEL
-; GISEL-NEXT: mov x20, x0
-; GISEL-NEXT: LBB4_5: ; %ehcleanup
-; GISEL-NEXT: add x0, sp, #15
-; GISEL-NEXT: bl __ZN1SD1Ev
-; GISEL-NEXT: mov x0, x20
-; GISEL-NEXT: bl __Unwind_Resume
-; GISEL-NEXT: .loh AdrpLdrGot Lloh4, Lloh5
-; GISEL-NEXT: .loh AdrpLdrGot Lloh6, Lloh7
-; GISEL-NEXT: Lfunc_end1:
-; GISEL-NEXT: .cfi_endproc
-; GISEL-NEXT: .section __TEXT,__gcc_except_tab
-; GISEL-NEXT: .p2align 2, 0x0
-; GISEL-NEXT: GCC_except_table4:
-; GISEL-NEXT: Lexception1:
-; GISEL-NEXT: .byte 255 ; @LPStart Encoding = omit
-; GISEL-NEXT: .byte 255 ; @TType Encoding = omit
-; GISEL-NEXT: .byte 1 ; Call site Encoding = uleb128
-; GISEL-NEXT: .uleb128 Lcst_end1-Lcst_begin1
-; GISEL-NEXT: Lcst_begin1:
-; GISEL-NEXT: .uleb128 Ltmp3-Lfunc_begin1 ; >> Call Site 1 <<
-; GISEL-NEXT: .uleb128 Ltmp4-Ltmp3 ; Call between Ltmp3 and Ltmp4
-; GISEL-NEXT: .uleb128 Ltmp5-Lfunc_begin1 ; jumps to Ltmp5
-; GISEL-NEXT: .byte 0 ; On action: cleanup
-; GISEL-NEXT: .uleb128 Ltmp6-Lfunc_begin1 ; >> Call Site 2 <<
-; GISEL-NEXT: .uleb128 Ltmp7-Ltmp6 ; Call between Ltmp6 and Ltmp7
-; GISEL-NEXT: .uleb128 Ltmp8-Lfunc_begin1 ; jumps to Ltmp8
-; GISEL-NEXT: .byte 0 ; On action: cleanup
-; GISEL-NEXT: .uleb128 Ltmp7-Lfunc_begin1 ; >> Call Site 3 <<
-; GISEL-NEXT: .uleb128 Lfunc_end1-Ltmp7 ; Call between Ltmp7 and Lfunc_end1
-; GISEL-NEXT: .byte 0 ; has no landing pad
-; GISEL-NEXT: .byte 0 ; On action: cleanup
-; GISEL-NEXT: Lcst_end1:
-; GISEL-NEXT: .p2align 2, 0x0
+; CHECK-GI-LABEL: rv_marker_4:
+; CHECK-GI: Lfunc_begin1:
+; CHECK-GI-NEXT: .cfi_startproc
+; CHECK-GI-NEXT: .cfi_personality 155, ___gxx_personality_v0
+; CHECK-GI-NEXT: .cfi_lsda 16, Lexception1
+; CHECK-GI-NEXT: ; %bb.0: ; %entry
+; CHECK-GI-NEXT: sub sp, sp, #48
+; CHECK-GI-NEXT: stp x20, x19, [sp, #16] ; 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x29, x30, [sp, #32] ; 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 48
+; CHECK-GI-NEXT: .cfi_offset w30, -8
+; CHECK-GI-NEXT: .cfi_offset w29, -16
+; CHECK-GI-NEXT: .cfi_offset w19, -24
+; CHECK-GI-NEXT: .cfi_offset w20, -32
+; CHECK-GI-NEXT: Ltmp3: ; EH_LABEL
+; CHECK-GI-NEXT: bl _foo1
+; CHECK-GI-NEXT: mov x29, x29
+; CHECK-GI-NEXT: bl _objc_retainAutoreleasedReturnValue
+; CHECK-GI-NEXT: Ltmp4: ; EH_LABEL
+; CHECK-GI-NEXT: ; %bb.1: ; %invoke.cont
+; CHECK-GI-NEXT: Ltmp6: ; EH_LABEL
+; CHECK-GI-NEXT: mov x19, x0
+; CHECK-GI-NEXT: bl _objc_object
+; CHECK-GI-NEXT: Ltmp7: ; EH_LABEL
+; CHECK-GI-NEXT: ; %bb.2: ; %invoke.cont2
+; CHECK-GI-NEXT: Lloh4:
+; CHECK-GI-NEXT: adrp x8, _objc_release at GOTPAGE
+; CHECK-GI-NEXT: mov x0, x19
+; CHECK-GI-NEXT: Lloh5:
+; CHECK-GI-NEXT: ldr x8, [x8, _objc_release at GOTPAGEOFF]
+; CHECK-GI-NEXT: blr x8
+; CHECK-GI-NEXT: add x0, sp, #15
+; CHECK-GI-NEXT: bl __ZN1SD1Ev
+; CHECK-GI-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #16] ; 16-byte Folded Reload
+; CHECK-GI-NEXT: add sp, sp, #48
+; CHECK-GI-NEXT: ret
+; CHECK-GI-NEXT: LBB4_3: ; %lpad1
+; CHECK-GI-NEXT: Ltmp8: ; EH_LABEL
+; CHECK-GI-NEXT: Lloh6:
+; CHECK-GI-NEXT: adrp x8, _objc_release at GOTPAGE
+; CHECK-GI-NEXT: mov x20, x0
+; CHECK-GI-NEXT: mov x0, x19
+; CHECK-GI-NEXT: Lloh7:
+; CHECK-GI-NEXT: ldr x8, [x8, _objc_release at GOTPAGEOFF]
+; CHECK-GI-NEXT: blr x8
+; CHECK-GI-NEXT: b LBB4_5
+; CHECK-GI-NEXT: LBB4_4: ; %lpad
+; CHECK-GI-NEXT: Ltmp5: ; EH_LABEL
+; CHECK-GI-NEXT: mov x20, x0
+; CHECK-GI-NEXT: LBB4_5: ; %ehcleanup
+; CHECK-GI-NEXT: add x0, sp, #15
+; CHECK-GI-NEXT: bl __ZN1SD1Ev
+; CHECK-GI-NEXT: mov x0, x20
+; CHECK-GI-NEXT: bl __Unwind_Resume
+; CHECK-GI-NEXT: .loh AdrpLdrGot Lloh4, Lloh5
+; CHECK-GI-NEXT: .loh AdrpLdrGot Lloh6, Lloh7
+; CHECK-GI-NEXT: Lfunc_end1:
+; CHECK-GI-NEXT: .cfi_endproc
+; CHECK-GI-NEXT: .section __TEXT,__gcc_except_tab
+; CHECK-GI-NEXT: .p2align 2, 0x0
+; CHECK-GI-NEXT: GCC_except_table4:
+; CHECK-GI-NEXT: Lexception1:
+; CHECK-GI-NEXT: .byte 255 ; @LPStart Encoding = omit
+; CHECK-GI-NEXT: .byte 255 ; @TType Encoding = omit
+; CHECK-GI-NEXT: .byte 1 ; Call site Encoding = uleb128
+; CHECK-GI-NEXT: .uleb128 Lcst_end1-Lcst_begin1
+; CHECK-GI-NEXT: Lcst_begin1:
+; CHECK-GI-NEXT: .uleb128 Ltmp3-Lfunc_begin1 ; >> Call Site 1 <<
+; CHECK-GI-NEXT: .uleb128 Ltmp4-Ltmp3 ; Call between Ltmp3 and Ltmp4
+; CHECK-GI-NEXT: .uleb128 Ltmp5-Lfunc_begin1 ; jumps to Ltmp5
+; CHECK-GI-NEXT: .byte 0 ; On action: cleanup
+; CHECK-GI-NEXT: .uleb128 Ltmp6-Lfunc_begin1 ; >> Call Site 2 <<
+; CHECK-GI-NEXT: .uleb128 Ltmp7-Ltmp6 ; Call between Ltmp6 and Ltmp7
+; CHECK-GI-NEXT: .uleb128 Ltmp8-Lfunc_begin1 ; jumps to Ltmp8
+; CHECK-GI-NEXT: .byte 0 ; On action: cleanup
+; CHECK-GI-NEXT: .uleb128 Ltmp7-Lfunc_begin1 ; >> Call Site 3 <<
+; CHECK-GI-NEXT: .uleb128 Lfunc_end1-Ltmp7 ; Call between Ltmp7 and Lfunc_end1
+; CHECK-GI-NEXT: .byte 0 ; has no landing pad
+; CHECK-GI-NEXT: .byte 0 ; On action: cleanup
+; CHECK-GI-NEXT: Lcst_end1:
+; CHECK-GI-NEXT: .p2align 2, 0x0
entry:
%s = alloca %struct.S, align 1
call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %s) #2
@@ -454,53 +415,53 @@ ehcleanup: ; preds = %lpad1, %lpad
}
define dso_local ptr @rv_marker_5_indirect_call() {
-; SELDAG-LABEL: rv_marker_5_indirect_call:
-; SELDAG: ; %bb.0: ; %entry
-; SELDAG-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
-; SELDAG-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; SELDAG-NEXT: .cfi_def_cfa_offset 32
-; SELDAG-NEXT: .cfi_offset w30, -8
-; SELDAG-NEXT: .cfi_offset w29, -16
-; SELDAG-NEXT: .cfi_offset w19, -24
-; SELDAG-NEXT: .cfi_offset w20, -32
-; SELDAG-NEXT: Lloh0:
-; SELDAG-NEXT: adrp x8, _fptr at PAGE
-; SELDAG-NEXT: Lloh1:
-; SELDAG-NEXT: ldr x8, [x8, _fptr at PAGEOFF]
-; SELDAG-NEXT: blr x8
-; SELDAG-NEXT: mov x29, x29
-; SELDAG-NEXT: bl _objc_retainAutoreleasedReturnValue
-; SELDAG-NEXT: mov x19, x0
-; SELDAG-NEXT: bl _foo2
-; SELDAG-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
-; SELDAG-NEXT: mov x0, x19
-; SELDAG-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
-; SELDAG-NEXT: ret
-; SELDAG-NEXT: .loh AdrpLdr Lloh0, Lloh1
+; CHECK-SD-LABEL: rv_marker_5_indirect_call:
+; CHECK-SD: ; %bb.0: ; %entry
+; CHECK-SD-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
+; CHECK-SD-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 32
+; CHECK-SD-NEXT: .cfi_offset w30, -8
+; CHECK-SD-NEXT: .cfi_offset w29, -16
+; CHECK-SD-NEXT: .cfi_offset w19, -24
+; CHECK-SD-NEXT: .cfi_offset w20, -32
+; CHECK-SD-NEXT: Lloh0:
+; CHECK-SD-NEXT: adrp x8, _fptr at PAGE
+; CHECK-SD-NEXT: Lloh1:
+; CHECK-SD-NEXT: ldr x8, [x8, _fptr at PAGEOFF]
+; CHECK-SD-NEXT: blr x8
+; CHECK-SD-NEXT: mov x29, x29
+; CHECK-SD-NEXT: bl _objc_retainAutoreleasedReturnValue
+; CHECK-SD-NEXT: mov x19, x0
+; CHECK-SD-NEXT: bl _foo2
+; CHECK-SD-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
+; CHECK-SD-NEXT: mov x0, x19
+; CHECK-SD-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
+; CHECK-SD-NEXT: ret
+; CHECK-SD-NEXT: .loh AdrpLdr Lloh0, Lloh1
;
-; GISEL-LABEL: rv_marker_5_indirect_call:
-; GISEL: ; %bb.0: ; %entry
-; GISEL-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
-; GISEL-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; GISEL-NEXT: .cfi_def_cfa_offset 32
-; GISEL-NEXT: .cfi_offset w30, -8
-; GISEL-NEXT: .cfi_offset w29, -16
-; GISEL-NEXT: .cfi_offset w19, -24
-; GISEL-NEXT: .cfi_offset w20, -32
-; GISEL-NEXT: Lloh8:
-; GISEL-NEXT: adrp x8, _fptr at PAGE
-; GISEL-NEXT: Lloh9:
-; GISEL-NEXT: ldr x8, [x8, _fptr at PAGEOFF]
-; GISEL-NEXT: blr x8
-; GISEL-NEXT: mov x29, x29
-; GISEL-NEXT: bl _objc_retainAutoreleasedReturnValue
-; GISEL-NEXT: mov x19, x0
-; GISEL-NEXT: bl _foo2
-; GISEL-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
-; GISEL-NEXT: mov x0, x19
-; GISEL-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
-; GISEL-NEXT: ret
-; GISEL-NEXT: .loh AdrpLdr Lloh8, Lloh9
+; CHECK-GI-LABEL: rv_marker_5_indirect_call:
+; CHECK-GI: ; %bb.0: ; %entry
+; CHECK-GI-NEXT: stp x20, x19, [sp, #-32]! ; 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-GI-NEXT: .cfi_offset w30, -8
+; CHECK-GI-NEXT: .cfi_offset w29, -16
+; CHECK-GI-NEXT: .cfi_offset w19, -24
+; CHECK-GI-NEXT: .cfi_offset w20, -32
+; CHECK-GI-NEXT: Lloh8:
+; CHECK-GI-NEXT: adrp x8, _fptr at PAGE
+; CHECK-GI-NEXT: Lloh9:
+; CHECK-GI-NEXT: ldr x8, [x8, _fptr at PAGEOFF]
+; CHECK-GI-NEXT: blr x8
+; CHECK-GI-NEXT: mov x29, x29
+; CHECK-GI-NEXT: bl _objc_retainAutoreleasedReturnValue
+; CHECK-GI-NEXT: mov x19, x0
+; CHECK-GI-NEXT: bl _foo2
+; CHECK-GI-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
+; CHECK-GI-NEXT: mov x0, x19
+; CHECK-GI-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
+; CHECK-GI-NEXT: ret
+; CHECK-GI-NEXT: .loh AdrpLdr Lloh8, Lloh9
entry:
%0 = load ptr, ptr @fptr, align 8
%call = call ptr %0() [ "clang.arc.attachedcall"(ptr @objc_retainAutoreleasedReturnValue) ]
@@ -511,61 +472,50 @@ entry:
declare ptr @foo(i64, i64, i64)
define dso_local void @rv_marker_multiarg(i64 %a, i64 %b, i64 %c) {
-; SELDAG-LABEL: rv_marker_multiarg:
-; SELDAG: ; %bb.0:
-; SELDAG-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
-; SELDAG-NEXT: .cfi_def_cfa_offset 16
-; SELDAG-NEXT: .cfi_offset w30, -8
-; SELDAG-NEXT: .cfi_offset w29, -16
-; SELDAG-NEXT: mov x8, x0
-; SELDAG-NEXT: mov x0, x2
-; SELDAG-NEXT: mov x2, x8
-; SELDAG-NEXT: bl _foo
-; SELDAG-NEXT: mov x29, x29
-; SELDAG-NEXT: bl _objc_retainAutoreleasedReturnValue
-; SELDAG-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
-; SELDAG-NEXT: ret
+; CHECK-SD-LABEL: rv_marker_multiarg:
+; CHECK-SD: ; %bb.0:
+; CHECK-SD-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
+; CHECK-SD-NEXT: .cfi_offset w30, -8
+; CHECK-SD-NEXT: .cfi_offset w29, -16
+; CHECK-SD-NEXT: mov x8, x0
+; CHECK-SD-NEXT: mov x0, x2
+; CHECK-SD-NEXT: mov x2, x8
+; CHECK-SD-NEXT: bl _foo
+; CHECK-SD-NEXT: mov x29, x29
+; CHECK-SD-NEXT: bl _objc_retainAutoreleasedReturnValue
+; CHECK-SD-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: rv_marker_multiarg:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
-; GISEL-NEXT: .cfi_def_cfa_offset 16
-; GISEL-NEXT: .cfi_offset w30, -8
-; GISEL-NEXT: .cfi_offset w29, -16
-; GISEL-NEXT: mov x3, x0
-; GISEL-NEXT: mov x0, x2
-; GISEL-NEXT: mov x2, x3
-; GISEL-NEXT: bl _foo
-; GISEL-NEXT: mov x29, x29
-; GISEL-NEXT: bl _objc_retainAutoreleasedReturnValue
-; GISEL-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: rv_marker_multiarg:
+; CHECK-GI: ; %bb.0:
+; CHECK-GI-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
+; CHECK-GI-NEXT: .cfi_offset w30, -8
+; CHECK-GI-NEXT: .cfi_offset w29, -16
+; CHECK-GI-NEXT: mov x3, x0
+; CHECK-GI-NEXT: mov x0, x2
+; CHECK-GI-NEXT: mov x2, x3
+; CHECK-GI-NEXT: bl _foo
+; CHECK-GI-NEXT: mov x29, x29
+; CHECK-GI-NEXT: bl _objc_retainAutoreleasedReturnValue
+; CHECK-GI-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
+; CHECK-GI-NEXT: ret
call ptr @foo(i64 %c, i64 %b, i64 %a) [ "clang.arc.attachedcall"(ptr @objc_retainAutoreleasedReturnValue) ]
ret void
}
define dso_local ptr @rv_marker_claim() {
-; SELDAG-LABEL: rv_marker_claim:
-; SELDAG: ; %bb.0: ; %entry
-; SELDAG-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
-; SELDAG-NEXT: .cfi_def_cfa_offset 16
-; SELDAG-NEXT: .cfi_offset w30, -8
-; SELDAG-NEXT: .cfi_offset w29, -16
-; SELDAG-NEXT: bl _foo1
-; SELDAG-NEXT: bl _objc_claimAutoreleasedReturnValue
-; SELDAG-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
-; SELDAG-NEXT: ret
-;
-; GISEL-LABEL: rv_marker_claim:
-; GISEL: ; %bb.0: ; %entry
-; GISEL-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
-; GISEL-NEXT: .cfi_def_cfa_offset 16
-; GISEL-NEXT: .cfi_offset w30, -8
-; GISEL-NEXT: .cfi_offset w29, -16
-; GISEL-NEXT: bl _foo1
-; GISEL-NEXT: bl _objc_claimAutoreleasedReturnValue
-; GISEL-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
-; GISEL-NEXT: ret
+; CHECK-LABEL: rv_marker_claim:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -8
+; CHECK-NEXT: .cfi_offset w29, -16
+; CHECK-NEXT: bl _foo1
+; CHECK-NEXT: bl _objc_claimAutoreleasedReturnValue
+; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
+; CHECK-NEXT: ret
entry:
%call = call ptr @foo1() [ "clang.arc.attachedcall"(ptr @objc_claimAutoreleasedReturnValue) ]
ret ptr %call
@@ -575,5 +525,3 @@ declare ptr @objc_retainAutoreleasedReturnValue(ptr)
declare ptr @objc_claimAutoreleasedReturnValue(ptr)
declare ptr @objc_unsafeClaimAutoreleasedReturnValue(ptr)
declare i32 @__gxx_personality_v0(...)
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/fast-isel-const-float.ll b/llvm/test/CodeGen/AArch64/fast-isel-const-float.ll
index 4de2c934a672e..18f8d21a8531f 100644
--- a/llvm/test/CodeGen/AArch64/fast-isel-const-float.ll
+++ b/llvm/test/CodeGen/AArch64/fast-isel-const-float.ll
@@ -4,8 +4,6 @@
; float foo(void) { return float(2147483648); }
define float @select_fp_const() {
-; CHECK-LABEL: select_opt4
-; CHECK: movi v0.2s, #79, lsl #24
; GISEL-LABEL: select_fp_const:
; GISEL: // %bb.0: // %entry
; GISEL-NEXT: movi v0.2s, #79, lsl #24
diff --git a/llvm/test/CodeGen/AArch64/fold-global-offsets.ll b/llvm/test/CodeGen/AArch64/fold-global-offsets.ll
index 8de0f0d121f90..8c2f019fd4735 100644
--- a/llvm/test/CodeGen/AArch64/fold-global-offsets.ll
+++ b/llvm/test/CodeGen/AArch64/fold-global-offsets.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s
-; RUN: llc < %s -global-isel -mtriple=arm64-linux-gnu | FileCheck %s --check-prefix=GISEL
+; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -global-isel -mtriple=arm64-linux-gnu | FileCheck %s --check-prefixes=CHECK,CHECK-GI
@x1 = external hidden global [2 x i64]
@x2 = external hidden global [16777216 x i64]
@@ -12,12 +12,6 @@ define i64 @f1() {
; CHECK-NEXT: adrp x8, x1+16
; CHECK-NEXT: ldr x0, [x8, :lo12:x1+16]
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: f1:
-; GISEL: // %bb.0:
-; GISEL-NEXT: adrp x8, x1+16
-; GISEL-NEXT: ldr x0, [x8, :lo12:x1+16]
-; GISEL-NEXT: ret
%l = load i64, ptr getelementptr ([2 x i64], ptr @x1, i64 0, i64 2)
ret i64 %l
}
@@ -29,13 +23,6 @@ define i64 @f2() {
; CHECK-NEXT: add x8, x8, :lo12:x1
; CHECK-NEXT: ldr x0, [x8, #24]
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: f2:
-; GISEL: // %bb.0:
-; GISEL-NEXT: adrp x8, x1
-; GISEL-NEXT: add x8, x8, :lo12:x1
-; GISEL-NEXT: ldr x0, [x8, #24]
-; GISEL-NEXT: ret
%l = load i64, ptr getelementptr ([2 x i64], ptr @x1, i64 0, i64 3)
ret i64 %l
@@ -48,13 +35,6 @@ define i64 @f3() {
; CHECK-NEXT: add x8, x8, :lo12:x1+1
; CHECK-NEXT: ldr x0, [x8]
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: f3:
-; GISEL: // %bb.0:
-; GISEL-NEXT: adrp x8, x1+1
-; GISEL-NEXT: add x8, x8, :lo12:x1+1
-; GISEL-NEXT: ldr x0, [x8]
-; GISEL-NEXT: ret
%l = load i64, ptr getelementptr (i8, ptr @x1, i64 1)
ret i64 %l
}
@@ -62,21 +42,21 @@ define i64 @f3() {
define [2 x i64] @f4() {
; FIXME: GlobalISel misses the opportunity to form a LDP here.
;
-; CHECK-LABEL: f4:
-; CHECK: // %bb.0:
-; CHECK-NEXT: adrp x8, x2+8
-; CHECK-NEXT: add x8, x8, :lo12:x2+8
-; CHECK-NEXT: ldp x0, x1, [x8]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: f4:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: adrp x8, x2+8
+; CHECK-SD-NEXT: add x8, x8, :lo12:x2+8
+; CHECK-SD-NEXT: ldp x0, x1, [x8]
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: f4:
-; GISEL: // %bb.0:
-; GISEL-NEXT: adrp x8, x2+8
-; GISEL-NEXT: adrp x9, x2+8
-; GISEL-NEXT: add x9, x9, :lo12:x2+8
-; GISEL-NEXT: ldr x0, [x8, :lo12:x2+8]
-; GISEL-NEXT: ldr x1, [x9, #8]
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: f4:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, x2+8
+; CHECK-GI-NEXT: adrp x9, x2+8
+; CHECK-GI-NEXT: add x9, x9, :lo12:x2+8
+; CHECK-GI-NEXT: ldr x0, [x8, :lo12:x2+8]
+; CHECK-GI-NEXT: ldr x1, [x9, #8]
+; CHECK-GI-NEXT: ret
%l = load [2 x i64], ptr getelementptr (i8, ptr @x2, i64 8)
ret [2 x i64] %l
}
@@ -87,12 +67,6 @@ define i64 @f5() {
; CHECK-NEXT: adrp x8, x2+1048568
; CHECK-NEXT: ldr x0, [x8, :lo12:x2+1048568]
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: f5:
-; GISEL: // %bb.0:
-; GISEL-NEXT: adrp x8, x2+1048568
-; GISEL-NEXT: ldr x0, [x8, :lo12:x2+1048568]
-; GISEL-NEXT: ret
%l = load i64, ptr getelementptr ([16777216 x i64], ptr @x2, i64 0, i64 131071)
ret i64 %l
}
@@ -100,19 +74,11 @@ define i64 @f5() {
define i64 @f6() {
; CHECK-LABEL: f6:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #1048576
+; CHECK-NEXT: mov w8, #1048576 // =0x100000
; CHECK-NEXT: adrp x9, x2
; CHECK-NEXT: add x9, x9, :lo12:x2
; CHECK-NEXT: ldr x0, [x9, x8]
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: f6:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #1048576
-; GISEL-NEXT: adrp x9, x2
-; GISEL-NEXT: add x9, x9, :lo12:x2
-; GISEL-NEXT: ldr x0, [x9, x8]
-; GISEL-NEXT: ret
%l = load i64, ptr getelementptr ([16777216 x i64], ptr @x2, i64 0, i64 131072)
ret i64 %l
}
@@ -123,12 +89,6 @@ define i32 @f7() {
; CHECK-NEXT: adrp x8, x3+108
; CHECK-NEXT: ldr w0, [x8, :lo12:x3+108]
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: f7:
-; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: adrp x8, x3+108
-; GISEL-NEXT: ldr w0, [x8, :lo12:x3+108]
-; GISEL-NEXT: ret
entry:
%lshr = lshr i128 bitcast (<2 x i64> <i64 undef, i64 ptrtoint (ptr getelementptr inbounds ({ [9 x ptr], [8 x ptr] }, ptr @x3, i64 0, i32 1, i64 2) to i64)> to i128), 64
diff --git a/llvm/test/CodeGen/AArch64/fpmode.ll b/llvm/test/CodeGen/AArch64/fpmode.ll
index b185d9e049411..fc6fc7b2016b9 100644
--- a/llvm/test/CodeGen/AArch64/fpmode.ll
+++ b/llvm/test/CodeGen/AArch64/fpmode.ll
@@ -1,68 +1,70 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -mtriple=aarch64-none-linux-gnu %s -o - | FileCheck --check-prefix=DAG %s
-; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel %s -o - | FileCheck --check-prefix=GIS %s
+; RUN: llc -mtriple=aarch64-none-linux-gnu %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
declare i32 @llvm.get.fpmode.i32()
declare void @llvm.set.fpmode.i32(i32 %fpmode)
declare void @llvm.reset.fpmode()
define i32 @func_get_fpmode() #0 {
-; DAG-LABEL: func_get_fpmode:
-; DAG: // %bb.0: // %entry
-; DAG-NEXT: mrs x0, FPCR
-; DAG-NEXT: // kill: def $w0 killed $w0 killed $x0
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: func_get_fpmode:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mrs x0, FPCR
+; CHECK-SD-NEXT: // kill: def $w0 killed $w0 killed $x0
+; CHECK-SD-NEXT: ret
;
-; GIS-LABEL: func_get_fpmode:
-; GIS: // %bb.0: // %entry
-; GIS-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; GIS-NEXT: add x0, sp, #12
-; GIS-NEXT: bl fegetmode
-; GIS-NEXT: ldr w0, [sp, #12]
-; GIS-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; GIS-NEXT: ret
+; CHECK-GI-LABEL: func_get_fpmode:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-GI-NEXT: add x0, sp, #12
+; CHECK-GI-NEXT: bl fegetmode
+; CHECK-GI-NEXT: ldr w0, [sp, #12]
+; CHECK-GI-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-GI-NEXT: ret
entry:
%fpmode = call i32 @llvm.get.fpmode.i32()
ret i32 %fpmode
}
define void @func_set_fpmode(i32 %fpmode) #0 {
-; DAG-LABEL: func_set_fpmode:
-; DAG: // %bb.0: // %entry
-; DAG-NEXT: mov w8, w0
-; DAG-NEXT: msr FPCR, x8
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: func_set_fpmode:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mov w8, w0
+; CHECK-SD-NEXT: msr FPCR, x8
+; CHECK-SD-NEXT: ret
;
-; GIS-LABEL: func_set_fpmode:
-; GIS: // %bb.0: // %entry
-; GIS-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; GIS-NEXT: str w0, [sp, #12]
-; GIS-NEXT: add x0, sp, #12
-; GIS-NEXT: bl fesetmode
-; GIS-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; GIS-NEXT: ret
+; CHECK-GI-LABEL: func_set_fpmode:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-GI-NEXT: str w0, [sp, #12]
+; CHECK-GI-NEXT: add x0, sp, #12
+; CHECK-GI-NEXT: bl fesetmode
+; CHECK-GI-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-GI-NEXT: ret
entry:
call void @llvm.set.fpmode.i32(i32 %fpmode)
ret void
}
define void @func_reset_fpmode() #0 {
-; DAG-LABEL: func_reset_fpmode:
-; DAG: // %bb.0: // %entry
-; DAG-NEXT: mov x9, #-48904 // =0xffffffffffff40f8
-; DAG-NEXT: mrs x8, FPCR
-; DAG-NEXT: movk x9, #63488, lsl #16
-; DAG-NEXT: and x8, x8, x9
-; DAG-NEXT: msr FPCR, x8
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: func_reset_fpmode:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mov x9, #-48904 // =0xffffffffffff40f8
+; CHECK-SD-NEXT: mrs x8, FPCR
+; CHECK-SD-NEXT: movk x9, #63488, lsl #16
+; CHECK-SD-NEXT: and x8, x8, x9
+; CHECK-SD-NEXT: msr FPCR, x8
+; CHECK-SD-NEXT: ret
;
-; GIS-LABEL: func_reset_fpmode:
-; GIS: // %bb.0: // %entry
-; GIS-NEXT: mov x0, #-1 // =0xffffffffffffffff
-; GIS-NEXT: b fesetmode
+; CHECK-GI-LABEL: func_reset_fpmode:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov x0, #-1 // =0xffffffffffffffff
+; CHECK-GI-NEXT: b fesetmode
entry:
call void @llvm.reset.fpmode()
ret void
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/mul_pow2.ll b/llvm/test/CodeGen/AArch64/mul_pow2.ll
index 7e26b877a4228..07becb3f5efbb 100644
--- a/llvm/test/CodeGen/AArch64/mul_pow2.ll
+++ b/llvm/test/CodeGen/AArch64/mul_pow2.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
-; RUN: llc < %s -mtriple=aarch64 -global-isel -global-isel-abort=1 | FileCheck %s --check-prefix=GISEL
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64 -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; Convert mul x, pow2 to shift.
; Convert mul x, pow2 +/- 1 to shift + add/sub.
@@ -12,11 +12,6 @@ define i32 @test2(i32 %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: lsl w0, w0, #1
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test2:
-; GISEL: // %bb.0:
-; GISEL-NEXT: lsl w0, w0, #1
-; GISEL-NEXT: ret
%mul = shl nsw i32 %x, 1
ret i32 %mul
@@ -27,11 +22,6 @@ define i32 @test3(i32 %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: add w0, w0, w0, lsl #1
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test3:
-; GISEL: // %bb.0:
-; GISEL-NEXT: add w0, w0, w0, lsl #1
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, 3
ret i32 %mul
@@ -42,11 +32,6 @@ define i32 @test4(i32 %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: lsl w0, w0, #2
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test4:
-; GISEL: // %bb.0:
-; GISEL-NEXT: lsl w0, w0, #2
-; GISEL-NEXT: ret
%mul = shl nsw i32 %x, 2
ret i32 %mul
@@ -57,11 +42,6 @@ define i32 @test5(i32 %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: add w0, w0, w0, lsl #2
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test5:
-; GISEL: // %bb.0:
-; GISEL-NEXT: add w0, w0, w0, lsl #2
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, 5
@@ -74,12 +54,6 @@ define i32 @test6_32b(i32 %x) {
; CHECK-NEXT: add w8, w0, w0, lsl #1
; CHECK-NEXT: lsl w0, w8, #1
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test6_32b:
-; GISEL: // %bb.0:
-; GISEL-NEXT: add w8, w0, w0, lsl #1
-; GISEL-NEXT: lsl w0, w8, #1
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, 6
ret i32 %mul
@@ -91,12 +65,6 @@ define i64 @test6_64b(i64 %x) {
; CHECK-NEXT: add x8, x0, x0, lsl #1
; CHECK-NEXT: lsl x0, x8, #1
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test6_64b:
-; GISEL: // %bb.0:
-; GISEL-NEXT: add x8, x0, x0, lsl #1
-; GISEL-NEXT: lsl x0, x8, #1
-; GISEL-NEXT: ret
%mul = mul nsw i64 %x, 6
ret i64 %mul
@@ -110,12 +78,6 @@ define i64 @test6_umull(i32 %x) {
; CHECK-NEXT: mov w8, #6 // =0x6
; CHECK-NEXT: umull x0, w0, w8
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test6_umull:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #6 // =0x6
-; GISEL-NEXT: umull x0, w0, w8
-; GISEL-NEXT: ret
%ext = zext i32 %x to i64
%mul = mul nsw i64 %ext, 6
@@ -128,12 +90,6 @@ define i64 @test6_smull(i32 %x) {
; CHECK-NEXT: mov w8, #6 // =0x6
; CHECK-NEXT: smull x0, w0, w8
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test6_smull:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #6 // =0x6
-; GISEL-NEXT: smull x0, w0, w8
-; GISEL-NEXT: ret
%ext = sext i32 %x to i64
%mul = mul nsw i64 %ext, 6
@@ -146,12 +102,6 @@ define i32 @test6_madd(i32 %x, i32 %y) {
; CHECK-NEXT: mov w8, #6 // =0x6
; CHECK-NEXT: madd w0, w0, w8, w1
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test6_madd:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #6 // =0x6
-; GISEL-NEXT: madd w0, w0, w8, w1
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, 6
%add = add i32 %mul, %y
@@ -164,12 +114,6 @@ define i32 @test6_msub(i32 %x, i32 %y) {
; CHECK-NEXT: mov w8, #6 // =0x6
; CHECK-NEXT: msub w0, w0, w8, w1
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test6_msub:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #6 // =0x6
-; GISEL-NEXT: msub w0, w0, w8, w1
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, 6
%sub = sub i32 %y, %mul
@@ -182,12 +126,6 @@ define i64 @test6_umaddl(i32 %x, i64 %y) {
; CHECK-NEXT: mov w8, #6 // =0x6
; CHECK-NEXT: umaddl x0, w0, w8, x1
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test6_umaddl:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #6 // =0x6
-; GISEL-NEXT: umaddl x0, w0, w8, x1
-; GISEL-NEXT: ret
%ext = zext i32 %x to i64
%mul = mul nsw i64 %ext, 6
@@ -201,12 +139,6 @@ define i64 @test6_smaddl(i32 %x, i64 %y) {
; CHECK-NEXT: mov w8, #6 // =0x6
; CHECK-NEXT: smaddl x0, w0, w8, x1
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test6_smaddl:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #6 // =0x6
-; GISEL-NEXT: smaddl x0, w0, w8, x1
-; GISEL-NEXT: ret
%ext = sext i32 %x to i64
%mul = mul nsw i64 %ext, 6
@@ -220,12 +152,6 @@ define i64 @test6_umsubl(i32 %x, i64 %y) {
; CHECK-NEXT: mov w8, #6 // =0x6
; CHECK-NEXT: umsubl x0, w0, w8, x1
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test6_umsubl:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #6 // =0x6
-; GISEL-NEXT: umsubl x0, w0, w8, x1
-; GISEL-NEXT: ret
%ext = zext i32 %x to i64
%mul = mul nsw i64 %ext, 6
@@ -239,12 +165,6 @@ define i64 @test6_smsubl(i32 %x, i64 %y) {
; CHECK-NEXT: mov w8, #6 // =0x6
; CHECK-NEXT: smsubl x0, w0, w8, x1
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test6_smsubl:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #6 // =0x6
-; GISEL-NEXT: smsubl x0, w0, w8, x1
-; GISEL-NEXT: ret
%ext = sext i32 %x to i64
%mul = mul nsw i64 %ext, 6
@@ -258,12 +178,6 @@ define i64 @test6_umnegl(i32 %x) {
; CHECK-NEXT: mov w8, #6 // =0x6
; CHECK-NEXT: umnegl x0, w0, w8
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test6_umnegl:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #6 // =0x6
-; GISEL-NEXT: umnegl x0, w0, w8
-; GISEL-NEXT: ret
%ext = zext i32 %x to i64
%mul = mul nsw i64 %ext, 6
@@ -277,12 +191,6 @@ define i64 @test6_smnegl(i32 %x) {
; CHECK-NEXT: mov w8, #6 // =0x6
; CHECK-NEXT: smnegl x0, w0, w8
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test6_smnegl:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #6 // =0x6
-; GISEL-NEXT: smnegl x0, w0, w8
-; GISEL-NEXT: ret
%ext = sext i32 %x to i64
%mul = mul nsw i64 %ext, 6
@@ -298,13 +206,6 @@ define i32 @mull6_sub(i32 %x) {
; CHECK-NEXT: mov w9, #-1 // =0xffffffff
; CHECK-NEXT: madd w0, w0, w8, w9
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: mull6_sub:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #6 // =0x6
-; GISEL-NEXT: mov w9, #-1 // =0xffffffff
-; GISEL-NEXT: madd w0, w0, w8, w9
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, 6
%sub = add nsw i32 %mul, -1
ret i32 %sub
@@ -317,13 +218,6 @@ define i64 @mull6_sub_orr(i64 %x) {
; CHECK-NEXT: mov x9, #16773120 // =0xfff000
; CHECK-NEXT: madd x0, x0, x8, x9
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: mull6_sub_orr:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #6 // =0x6
-; GISEL-NEXT: mov x9, #16773120 // =0xfff000
-; GISEL-NEXT: madd x0, x0, x8, x9
-; GISEL-NEXT: ret
%mul = mul nsw i64 %x, 6
%sub = add nsw i64 %mul, 16773120
ret i64 %sub
@@ -335,12 +229,6 @@ define i32 @test7(i32 %x) {
; CHECK-NEXT: lsl w8, w0, #3
; CHECK-NEXT: sub w0, w8, w0
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test7:
-; GISEL: // %bb.0:
-; GISEL-NEXT: lsl w8, w0, #3
-; GISEL-NEXT: sub w0, w8, w0
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, 7
ret i32 %mul
@@ -351,11 +239,6 @@ define i32 @test8(i32 %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: lsl w0, w0, #3
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: lsl w0, w0, #3
-; GISEL-NEXT: ret
%mul = shl nsw i32 %x, 3
ret i32 %mul
@@ -366,11 +249,6 @@ define i32 @test9(i32 %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: add w0, w0, w0, lsl #3
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test9:
-; GISEL: // %bb.0:
-; GISEL-NEXT: add w0, w0, w0, lsl #3
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, 9
ret i32 %mul
@@ -382,12 +260,6 @@ define i32 @test10(i32 %x) {
; CHECK-NEXT: add w8, w0, w0, lsl #2
; CHECK-NEXT: lsl w0, w8, #1
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test10:
-; GISEL: // %bb.0:
-; GISEL-NEXT: add w8, w0, w0, lsl #2
-; GISEL-NEXT: lsl w0, w8, #1
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, 10
ret i32 %mul
@@ -399,29 +271,23 @@ define i32 @test11(i32 %x) {
; CHECK-NEXT: mov w8, #11 // =0xb
; CHECK-NEXT: mul w0, w0, w8
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test11:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #11 // =0xb
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, 11
ret i32 %mul
}
define i32 @test11_fast_shift(i32 %x) "target-features"="+alu-lsl-fast" {
-; CHECK-LABEL: test11_fast_shift:
-; CHECK: // %bb.0:
-; CHECK-NEXT: add w8, w0, w0, lsl #2
-; CHECK-NEXT: add w0, w0, w8, lsl #1
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test11_fast_shift:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #11 // =0xb
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: test11_fast_shift:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: add w8, w0, w0, lsl #2
+; CHECK-SD-NEXT: add w0, w0, w8, lsl #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test11_fast_shift:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #11 // =0xb
+; CHECK-GI-NEXT: mul w0, w0, w8
+; CHECK-GI-NEXT: ret
%mul = mul nsw i32 %x, 11 ; 11 = (((1<<2) + 1) << 1) + 1
ret i32 %mul
@@ -433,12 +299,6 @@ define i32 @test12(i32 %x) {
; CHECK-NEXT: add w8, w0, w0, lsl #1
; CHECK-NEXT: lsl w0, w8, #2
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test12:
-; GISEL: // %bb.0:
-; GISEL-NEXT: add w8, w0, w0, lsl #1
-; GISEL-NEXT: lsl w0, w8, #2
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, 12
ret i32 %mul
@@ -450,29 +310,23 @@ define i32 @test13(i32 %x) {
; CHECK-NEXT: mov w8, #13 // =0xd
; CHECK-NEXT: mul w0, w0, w8
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test13:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #13 // =0xd
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, 13
ret i32 %mul
}
define i32 @test14(i32 %x) {
-; CHECK-LABEL: test14:
-; CHECK: // %bb.0:
-; CHECK-NEXT: lsl w8, w0, #4
-; CHECK-NEXT: sub w0, w8, w0, lsl #1
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test14:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #14 // =0xe
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: test14:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: lsl w8, w0, #4
+; CHECK-SD-NEXT: sub w0, w8, w0, lsl #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test14:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #14 // =0xe
+; CHECK-GI-NEXT: mul w0, w0, w8
+; CHECK-GI-NEXT: ret
%mul = mul nsw i32 %x, 14
ret i32 %mul
@@ -484,12 +338,6 @@ define i32 @test15(i32 %x) {
; CHECK-NEXT: lsl w8, w0, #4
; CHECK-NEXT: sub w0, w8, w0
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test15:
-; GISEL: // %bb.0:
-; GISEL-NEXT: lsl w8, w0, #4
-; GISEL-NEXT: sub w0, w8, w0
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, 15
ret i32 %mul
@@ -500,62 +348,57 @@ define i32 @test16(i32 %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: lsl w0, w0, #4
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test16:
-; GISEL: // %bb.0:
-; GISEL-NEXT: lsl w0, w0, #4
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, 16
ret i32 %mul
}
define i32 @test25_fast_shift(i32 %x) "target-features"="+alu-lsl-fast" {
-; CHECK-LABEL: test25_fast_shift:
-; CHECK: // %bb.0:
-; CHECK-NEXT: add w8, w0, w0, lsl #2
-; CHECK-NEXT: add w0, w8, w8, lsl #2
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test25_fast_shift:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #25 // =0x19
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: test25_fast_shift:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: add w8, w0, w0, lsl #2
+; CHECK-SD-NEXT: add w0, w8, w8, lsl #2
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test25_fast_shift:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #25 // =0x19
+; CHECK-GI-NEXT: mul w0, w0, w8
+; CHECK-GI-NEXT: ret
%mul = mul nsw i32 %x, 25 ; 25 = (1+4)*(1+4)
ret i32 %mul
}
define i32 @test29_fast_shift(i32 %x) "target-features"="+alu-lsl-fast" {
-; CHECK-LABEL: test29_fast_shift:
-; CHECK: // %bb.0:
-; CHECK-NEXT: sub w8, w0, w0, lsl #3
-; CHECK-NEXT: sub w0, w0, w8, lsl #2
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test29_fast_shift:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #29 // =0x1d
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: test29_fast_shift:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sub w8, w0, w0, lsl #3
+; CHECK-SD-NEXT: sub w0, w0, w8, lsl #2
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test29_fast_shift:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #29 // =0x1d
+; CHECK-GI-NEXT: mul w0, w0, w8
+; CHECK-GI-NEXT: ret
%mul = mul nsw i32 %x, 29 ; 29 = 1 - (1-8) * 4
ret i32 %mul
}
define i32 @test45_fast_shift(i32 %x) "target-features"="+alu-lsl-fast" {
-; CHECK-LABEL: test45_fast_shift:
-; CHECK: // %bb.0:
-; CHECK-NEXT: add w8, w0, w0, lsl #2
-; CHECK-NEXT: add w0, w8, w8, lsl #3
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test45_fast_shift:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #45 // =0x2d
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: test45_fast_shift:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: add w8, w0, w0, lsl #2
+; CHECK-SD-NEXT: add w0, w8, w8, lsl #3
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test45_fast_shift:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #45 // =0x2d
+; CHECK-GI-NEXT: mul w0, w0, w8
+; CHECK-GI-NEXT: ret
%mul = mul nsw i32 %x, 45 ; 45 = (1+4)*(1+8)
ret i32 %mul
@@ -568,12 +411,6 @@ define i32 @test45(i32 %x) {
; CHECK-NEXT: mov w8, #45 // =0x2d
; CHECK-NEXT: mul w0, w0, w8
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test45:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #45 // =0x2d
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, 45 ; 45 = (1+4)*(1+8)
ret i32 %mul
@@ -586,29 +423,23 @@ define i32 @test67_fast_shift(i32 %x) "target-features"="+alu-lsl-fast" {
; CHECK-NEXT: mov w8, #67 // =0x43
; CHECK-NEXT: mul w0, w0, w8
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test67_fast_shift:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #67 // =0x43
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, 67 ; 67 = (((1<<5) + 1) << 1) + 1
ret i32 %mul
}
define i32 @test85_fast_shift(i32 %x) "target-features"="+alu-lsl-fast" {
-; CHECK-LABEL: test85_fast_shift:
-; CHECK: // %bb.0:
-; CHECK-NEXT: add w8, w0, w0, lsl #2
-; CHECK-NEXT: add w0, w8, w8, lsl #4
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test85_fast_shift:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #85 // =0x55
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: test85_fast_shift:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: add w8, w0, w0, lsl #2
+; CHECK-SD-NEXT: add w0, w8, w8, lsl #4
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test85_fast_shift:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #85 // =0x55
+; CHECK-GI-NEXT: mul w0, w0, w8
+; CHECK-GI-NEXT: ret
%mul = mul nsw i32 %x, 85 ; 85 = (1+4)*(1+16)
ret i32 %mul
@@ -621,12 +452,6 @@ define i32 @test97_fast_shift(i32 %x) "target-features"="+alu-lsl-fast" {
; CHECK-NEXT: mov w8, #97 // =0x61
; CHECK-NEXT: mul w0, w0, w8
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test97_fast_shift:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #97 // =0x61
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, 97 ; 97 = ((2 + 1) << 5) + 1
ret i32 %mul
@@ -639,12 +464,6 @@ define i32 @test125_fast_shift(i32 %x) "target-features"="+alu-lsl-fast" {
; CHECK-NEXT: mov w8, #125 // =0x7d
; CHECK-NEXT: mul w0, w0, w8
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test125_fast_shift:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #125 // =0x7d
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, 125 ; 125 = 1 - ((1-32) << 2)
ret i32 %mul
@@ -657,12 +476,6 @@ define i32 @test225_fast_shift(i32 %x) "target-features"="+alu-lsl-fast" {
; CHECK-NEXT: mov w8, #225 // =0xe1
; CHECK-NEXT: mul w0, w0, w8
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test225_fast_shift:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #225 // =0xe1
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, 225 ; 225 = (1-16)*(1-16)
ret i32 %mul
@@ -675,12 +488,6 @@ define i32 @test297_fast_shift(i32 %x) "target-features"="+alu-lsl-fast" {
; CHECK-NEXT: mov w8, #297 // =0x129
; CHECK-NEXT: mul w0, w0, w8
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test297_fast_shift:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #297 // =0x129
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, 297 ; 297 = (1+8)*(1+32)
ret i32 %mul
@@ -693,12 +500,6 @@ define i32 @test481_fast_shift(i32 %x) "target-features"="+alu-lsl-fast" {
; CHECK-NEXT: mov w8, #481 // =0x1e1
; CHECK-NEXT: mul w0, w0, w8
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test481_fast_shift:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #481 // =0x1e1
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, 481 ; 481 = 1 - ((1-16) << 5)
ret i32 %mul
@@ -709,16 +510,16 @@ define i32 @test481_fast_shift(i32 %x) "target-features"="+alu-lsl-fast" {
; Lowering other negative constants are not supported yet.
define i32 @ntest2(i32 %x) {
-; CHECK-LABEL: ntest2:
-; CHECK: // %bb.0:
-; CHECK-NEXT: neg w0, w0, lsl #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: ntest2:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: neg w0, w0, lsl #1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: ntest2:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #-2 // =0xfffffffe
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: ntest2:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #-2 // =0xfffffffe
+; CHECK-GI-NEXT: mul w0, w0, w8
+; CHECK-GI-NEXT: ret
%mul = mul nsw i32 %x, -2
ret i32 %mul
@@ -729,27 +530,22 @@ define i32 @ntest3(i32 %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: sub w0, w0, w0, lsl #2
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: ntest3:
-; GISEL: // %bb.0:
-; GISEL-NEXT: sub w0, w0, w0, lsl #2
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, -3
ret i32 %mul
}
define i32 @ntest4(i32 %x) {
-; CHECK-LABEL: ntest4:
-; CHECK: // %bb.0:
-; CHECK-NEXT: neg w0, w0, lsl #2
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: ntest4:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: neg w0, w0, lsl #2
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: ntest4:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #-4 // =0xfffffffc
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: ntest4:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #-4 // =0xfffffffc
+; CHECK-GI-NEXT: mul w0, w0, w8
+; CHECK-GI-NEXT: ret
%mul = mul nsw i32 %x, -4
ret i32 %mul
@@ -761,28 +557,22 @@ define i32 @ntest5(i32 %x) {
; CHECK-NEXT: add w8, w0, w0, lsl #2
; CHECK-NEXT: neg w0, w8
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: ntest5:
-; GISEL: // %bb.0:
-; GISEL-NEXT: add w8, w0, w0, lsl #2
-; GISEL-NEXT: neg w0, w8
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, -5
ret i32 %mul
}
define i32 @ntest6(i32 %x) {
-; CHECK-LABEL: ntest6:
-; CHECK: // %bb.0:
-; CHECK-NEXT: lsl w8, w0, #1
-; CHECK-NEXT: sub w0, w8, w0, lsl #3
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: ntest6:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #-6 // =0xfffffffa
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: ntest6:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: lsl w8, w0, #1
+; CHECK-SD-NEXT: sub w0, w8, w0, lsl #3
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ntest6:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #-6 // =0xfffffffa
+; CHECK-GI-NEXT: mul w0, w0, w8
+; CHECK-GI-NEXT: ret
%mul = mul nsw i32 %x, -6
ret i32 %mul
@@ -793,27 +583,22 @@ define i32 @ntest7(i32 %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: sub w0, w0, w0, lsl #3
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: ntest7:
-; GISEL: // %bb.0:
-; GISEL-NEXT: sub w0, w0, w0, lsl #3
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, -7
ret i32 %mul
}
define i32 @ntest8(i32 %x) {
-; CHECK-LABEL: ntest8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: neg w0, w0, lsl #3
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: ntest8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: neg w0, w0, lsl #3
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: ntest8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #-8 // =0xfffffff8
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: ntest8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #-8 // =0xfffffff8
+; CHECK-GI-NEXT: mul w0, w0, w8
+; CHECK-GI-NEXT: ret
%mul = mul nsw i32 %x, -8
ret i32 %mul
@@ -825,12 +610,6 @@ define i32 @ntest9(i32 %x) {
; CHECK-NEXT: add w8, w0, w0, lsl #3
; CHECK-NEXT: neg w0, w8
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: ntest9:
-; GISEL: // %bb.0:
-; GISEL-NEXT: add w8, w0, w0, lsl #3
-; GISEL-NEXT: neg w0, w8
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, -9
ret i32 %mul
@@ -842,12 +621,6 @@ define i32 @ntest10(i32 %x) {
; CHECK-NEXT: mov w8, #-10 // =0xfffffff6
; CHECK-NEXT: mul w0, w0, w8
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: ntest10:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #-10 // =0xfffffff6
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, -10
ret i32 %mul
@@ -859,29 +632,23 @@ define i32 @ntest11(i32 %x) {
; CHECK-NEXT: mov w8, #-11 // =0xfffffff5
; CHECK-NEXT: mul w0, w0, w8
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: ntest11:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #-11 // =0xfffffff5
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, -11
ret i32 %mul
}
define i32 @ntest12(i32 %x) {
-; CHECK-LABEL: ntest12:
-; CHECK: // %bb.0:
-; CHECK-NEXT: lsl w8, w0, #2
-; CHECK-NEXT: sub w0, w8, w0, lsl #4
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: ntest12:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #-12 // =0xfffffff4
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: ntest12:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: lsl w8, w0, #2
+; CHECK-SD-NEXT: sub w0, w8, w0, lsl #4
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ntest12:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #-12 // =0xfffffff4
+; CHECK-GI-NEXT: mul w0, w0, w8
+; CHECK-GI-NEXT: ret
%mul = mul nsw i32 %x, -12
ret i32 %mul
@@ -893,28 +660,22 @@ define i32 @ntest13(i32 %x) {
; CHECK-NEXT: mov w8, #-13 // =0xfffffff3
; CHECK-NEXT: mul w0, w0, w8
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: ntest13:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #-13 // =0xfffffff3
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, -13
ret i32 %mul
}
define i32 @ntest14(i32 %x) {
-; CHECK-LABEL: ntest14:
-; CHECK: // %bb.0:
-; CHECK-NEXT: lsl w8, w0, #1
-; CHECK-NEXT: sub w0, w8, w0, lsl #4
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: ntest14:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #-14 // =0xfffffff2
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: ntest14:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: lsl w8, w0, #1
+; CHECK-SD-NEXT: sub w0, w8, w0, lsl #4
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ntest14:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #-14 // =0xfffffff2
+; CHECK-GI-NEXT: mul w0, w0, w8
+; CHECK-GI-NEXT: ret
%mul = mul nsw i32 %x, -14
ret i32 %mul
@@ -925,45 +686,40 @@ define i32 @ntest15(i32 %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: sub w0, w0, w0, lsl #4
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: ntest15:
-; GISEL: // %bb.0:
-; GISEL-NEXT: sub w0, w0, w0, lsl #4
-; GISEL-NEXT: ret
%mul = mul nsw i32 %x, -15
ret i32 %mul
}
define i32 @ntest16(i32 %x) {
-; CHECK-LABEL: ntest16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: neg w0, w0, lsl #4
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: ntest16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: neg w0, w0, lsl #4
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: ntest16:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #-16 // =0xfffffff0
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: ntest16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #-16 // =0xfffffff0
+; CHECK-GI-NEXT: mul w0, w0, w8
+; CHECK-GI-NEXT: ret
%mul = mul nsw i32 %x, -16
ret i32 %mul
}
define i32 @muladd_demand(i32 %x, i32 %y) {
-; CHECK-LABEL: muladd_demand:
-; CHECK: // %bb.0:
-; CHECK-NEXT: sub w8, w1, w0, lsl #6
-; CHECK-NEXT: and w0, w8, #0x1ffc0
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: muladd_demand:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #131008 // =0x1ffc0
-; GISEL-NEXT: madd w8, w0, w8, w1
-; GISEL-NEXT: and w0, w8, #0x1ffc0
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: muladd_demand:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sub w8, w1, w0, lsl #6
+; CHECK-SD-NEXT: and w0, w8, #0x1ffc0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: muladd_demand:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #131008 // =0x1ffc0
+; CHECK-GI-NEXT: madd w8, w0, w8, w1
+; CHECK-GI-NEXT: and w0, w8, #0x1ffc0
+; CHECK-GI-NEXT: ret
%m = mul i32 %x, 131008 ; 0x0001ffc0
%a = add i32 %y, %m
%r = and i32 %a, 131008
@@ -971,22 +727,22 @@ define i32 @muladd_demand(i32 %x, i32 %y) {
}
define <4 x i32> @muladd_demand_commute(<4 x i32> %x, <4 x i32> %y) {
-; CHECK-LABEL: muladd_demand_commute:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shl v0.4s, v0.4s, #6
-; CHECK-NEXT: movi v2.4s, #1, msl #16
-; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s
-; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: muladd_demand_commute:
-; GISEL: // %bb.0:
-; GISEL-NEXT: adrp x8, .LCPI56_0
-; GISEL-NEXT: movi v3.4s, #1, msl #16
-; GISEL-NEXT: ldr q2, [x8, :lo12:.LCPI56_0]
-; GISEL-NEXT: mla v1.4s, v0.4s, v2.4s
-; GISEL-NEXT: and v0.16b, v1.16b, v3.16b
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: muladd_demand_commute:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shl v0.4s, v0.4s, #6
+; CHECK-SD-NEXT: movi v2.4s, #1, msl #16
+; CHECK-SD-NEXT: sub v0.4s, v1.4s, v0.4s
+; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: muladd_demand_commute:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI56_0
+; CHECK-GI-NEXT: movi v3.4s, #1, msl #16
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI56_0]
+; CHECK-GI-NEXT: mla v1.4s, v0.4s, v2.4s
+; CHECK-GI-NEXT: and v0.16b, v1.16b, v3.16b
+; CHECK-GI-NEXT: ret
%m = mul <4 x i32> %x, <i32 131008, i32 131008, i32 131008, i32 131008>
%a = add <4 x i32> %m, %y
%r = and <4 x i32> %a, <i32 131071, i32 131071, i32 131071, i32 131071>
@@ -1001,12 +757,6 @@ define i32 @shift_overflow(i32 %x) {
; CHECK-NEXT: mov w8, #-2147483648 // =0x80000000
; CHECK-NEXT: mul w0, w0, w8
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: shift_overflow:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #-2147483648 // =0x80000000
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
%const = bitcast i32 2147483648 to i32
%r = mul i32 %x, %const
ret i32 %r
@@ -1015,17 +765,17 @@ define i32 @shift_overflow(i32 %x) {
; Transforming `(mul x, -(2^(N-M) - 1) * 2^M)` to `(sub (shl x, M), (shl x, N))`
; will not cause overflow when N is 31 and M is 30.
define i32 @shift_no_overflow(i32 %x) {
-; CHECK-LABEL: shift_no_overflow:
-; CHECK: // %bb.0:
-; CHECK-NEXT: lsl w8, w0, #31
-; CHECK-NEXT: sub w0, w8, w0, lsl #30
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: shift_no_overflow:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov w8, #1073741824 // =0x40000000
-; GISEL-NEXT: mul w0, w0, w8
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: shift_no_overflow:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: lsl w8, w0, #31
+; CHECK-SD-NEXT: sub w0, w8, w0, lsl #30
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: shift_no_overflow:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1073741824 // =0x40000000
+; CHECK-GI-NEXT: mul w0, w0, w8
+; CHECK-GI-NEXT: ret
%const = bitcast i32 1073741824 to i32
%r = mul i32 %x, %const
ret i32 %r
diff --git a/llvm/test/CodeGen/AArch64/reduce-and.ll b/llvm/test/CodeGen/AArch64/reduce-and.ll
index 8ca521327c2e3..21696cf7325c9 100644
--- a/llvm/test/CodeGen/AArch64/reduce-and.ll
+++ b/llvm/test/CodeGen/AArch64/reduce-and.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -mattr=+neon | FileCheck %s
-; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=1 | FileCheck %s --check-prefix=GISEL
+; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define i1 @test_redand_v1i1(<1 x i1> %a) {
@@ -8,189 +8,184 @@ define i1 @test_redand_v1i1(<1 x i1> %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: and w0, w0, #0x1
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_redand_v1i1:
-; GISEL: // %bb.0:
-; GISEL-NEXT: and w0, w0, #0x1
-; GISEL-NEXT: ret
%or_result = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %a)
ret i1 %or_result
}
define i1 @test_redand_v2i1(<2 x i1> %a) {
-; CHECK-LABEL: test_redand_v2i1:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shl v0.2s, v0.2s, #31
-; CHECK-NEXT: cmlt v0.2s, v0.2s, #0
-; CHECK-NEXT: uminp v0.2s, v0.2s, v0.2s
-; CHECK-NEXT: fmov w8, s0
-; CHECK-NEXT: and w0, w8, #0x1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redand_v2i1:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shl v0.2s, v0.2s, #31
+; CHECK-SD-NEXT: cmlt v0.2s, v0.2s, #0
+; CHECK-SD-NEXT: uminp v0.2s, v0.2s, v0.2s
+; CHECK-SD-NEXT: fmov w8, s0
+; CHECK-SD-NEXT: and w0, w8, #0x1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redand_v2i1:
-; GISEL: // %bb.0:
-; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; GISEL-NEXT: mov w8, v0.s[1]
-; GISEL-NEXT: fmov w9, s0
-; GISEL-NEXT: and w8, w9, w8
-; GISEL-NEXT: and w0, w8, #0x1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redand_v2i1:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: mov w8, v0.s[1]
+; CHECK-GI-NEXT: fmov w9, s0
+; CHECK-GI-NEXT: and w8, w9, w8
+; CHECK-GI-NEXT: and w0, w8, #0x1
+; CHECK-GI-NEXT: ret
%or_result = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %a)
ret i1 %or_result
}
define i1 @test_redand_v4i1(<4 x i1> %a) {
-; CHECK-LABEL: test_redand_v4i1:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shl v0.4h, v0.4h, #15
-; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
-; CHECK-NEXT: uminv h0, v0.4h
-; CHECK-NEXT: fmov w8, s0
-; CHECK-NEXT: and w0, w8, #0x1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redand_v4i1:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shl v0.4h, v0.4h, #15
+; CHECK-SD-NEXT: cmlt v0.4h, v0.4h, #0
+; CHECK-SD-NEXT: uminv h0, v0.4h
+; CHECK-SD-NEXT: fmov w8, s0
+; CHECK-SD-NEXT: and w0, w8, #0x1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redand_v4i1:
-; GISEL: // %bb.0:
-; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; GISEL-NEXT: umov w8, v0.h[0]
-; GISEL-NEXT: umov w9, v0.h[1]
-; GISEL-NEXT: umov w10, v0.h[2]
-; GISEL-NEXT: umov w11, v0.h[3]
-; GISEL-NEXT: and w8, w8, w9
-; GISEL-NEXT: and w9, w10, w11
-; GISEL-NEXT: and w8, w8, w9
-; GISEL-NEXT: and w0, w8, #0x1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redand_v4i1:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: umov w8, v0.h[0]
+; CHECK-GI-NEXT: umov w9, v0.h[1]
+; CHECK-GI-NEXT: umov w10, v0.h[2]
+; CHECK-GI-NEXT: umov w11, v0.h[3]
+; CHECK-GI-NEXT: and w8, w8, w9
+; CHECK-GI-NEXT: and w9, w10, w11
+; CHECK-GI-NEXT: and w8, w8, w9
+; CHECK-GI-NEXT: and w0, w8, #0x1
+; CHECK-GI-NEXT: ret
%or_result = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %a)
ret i1 %or_result
}
define i1 @test_redand_v8i1(<8 x i1> %a) {
-; CHECK-LABEL: test_redand_v8i1:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shl v0.8b, v0.8b, #7
-; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
-; CHECK-NEXT: uminv b0, v0.8b
-; CHECK-NEXT: fmov w8, s0
-; CHECK-NEXT: and w0, w8, #0x1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redand_v8i1:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shl v0.8b, v0.8b, #7
+; CHECK-SD-NEXT: cmlt v0.8b, v0.8b, #0
+; CHECK-SD-NEXT: uminv b0, v0.8b
+; CHECK-SD-NEXT: fmov w8, s0
+; CHECK-SD-NEXT: and w0, w8, #0x1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redand_v8i1:
-; GISEL: // %bb.0:
-; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; GISEL-NEXT: umov w8, v0.b[0]
-; GISEL-NEXT: umov w9, v0.b[1]
-; GISEL-NEXT: umov w10, v0.b[2]
-; GISEL-NEXT: umov w11, v0.b[3]
-; GISEL-NEXT: umov w12, v0.b[4]
-; GISEL-NEXT: umov w13, v0.b[5]
-; GISEL-NEXT: umov w14, v0.b[6]
-; GISEL-NEXT: umov w15, v0.b[7]
-; GISEL-NEXT: and w8, w8, w9
-; GISEL-NEXT: and w9, w10, w11
-; GISEL-NEXT: and w10, w12, w13
-; GISEL-NEXT: and w11, w14, w15
-; GISEL-NEXT: and w8, w8, w9
-; GISEL-NEXT: and w9, w10, w11
-; GISEL-NEXT: and w8, w8, w9
-; GISEL-NEXT: and w0, w8, #0x1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redand_v8i1:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: umov w8, v0.b[0]
+; CHECK-GI-NEXT: umov w9, v0.b[1]
+; CHECK-GI-NEXT: umov w10, v0.b[2]
+; CHECK-GI-NEXT: umov w11, v0.b[3]
+; CHECK-GI-NEXT: umov w12, v0.b[4]
+; CHECK-GI-NEXT: umov w13, v0.b[5]
+; CHECK-GI-NEXT: umov w14, v0.b[6]
+; CHECK-GI-NEXT: umov w15, v0.b[7]
+; CHECK-GI-NEXT: and w8, w8, w9
+; CHECK-GI-NEXT: and w9, w10, w11
+; CHECK-GI-NEXT: and w10, w12, w13
+; CHECK-GI-NEXT: and w11, w14, w15
+; CHECK-GI-NEXT: and w8, w8, w9
+; CHECK-GI-NEXT: and w9, w10, w11
+; CHECK-GI-NEXT: and w8, w8, w9
+; CHECK-GI-NEXT: and w0, w8, #0x1
+; CHECK-GI-NEXT: ret
%or_result = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> %a)
ret i1 %or_result
}
define i1 @test_redand_v16i1(<16 x i1> %a) {
-; CHECK-LABEL: test_redand_v16i1:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shl v0.16b, v0.16b, #7
-; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
-; CHECK-NEXT: uminv b0, v0.16b
-; CHECK-NEXT: fmov w8, s0
-; CHECK-NEXT: and w0, w8, #0x1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redand_v16i1:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shl v0.16b, v0.16b, #7
+; CHECK-SD-NEXT: cmlt v0.16b, v0.16b, #0
+; CHECK-SD-NEXT: uminv b0, v0.16b
+; CHECK-SD-NEXT: fmov w8, s0
+; CHECK-SD-NEXT: and w0, w8, #0x1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redand_v16i1:
-; GISEL: // %bb.0:
-; GISEL-NEXT: umov w8, v0.b[0]
-; GISEL-NEXT: umov w9, v0.b[1]
-; GISEL-NEXT: umov w10, v0.b[2]
-; GISEL-NEXT: umov w11, v0.b[3]
-; GISEL-NEXT: umov w12, v0.b[4]
-; GISEL-NEXT: umov w13, v0.b[5]
-; GISEL-NEXT: umov w14, v0.b[6]
-; GISEL-NEXT: umov w15, v0.b[7]
-; GISEL-NEXT: umov w16, v0.b[8]
-; GISEL-NEXT: umov w17, v0.b[9]
-; GISEL-NEXT: umov w18, v0.b[10]
-; GISEL-NEXT: umov w0, v0.b[11]
-; GISEL-NEXT: and w8, w8, w9
-; GISEL-NEXT: umov w1, v0.b[12]
-; GISEL-NEXT: umov w2, v0.b[13]
-; GISEL-NEXT: and w9, w10, w11
-; GISEL-NEXT: and w10, w12, w13
-; GISEL-NEXT: umov w3, v0.b[14]
-; GISEL-NEXT: and w11, w14, w15
-; GISEL-NEXT: and w8, w8, w9
-; GISEL-NEXT: umov w4, v0.b[15]
-; GISEL-NEXT: and w12, w16, w17
-; GISEL-NEXT: and w13, w18, w0
-; GISEL-NEXT: and w9, w10, w11
-; GISEL-NEXT: and w14, w1, w2
-; GISEL-NEXT: and w10, w12, w13
-; GISEL-NEXT: and w8, w8, w9
-; GISEL-NEXT: and w15, w3, w4
-; GISEL-NEXT: and w11, w14, w15
-; GISEL-NEXT: and w9, w10, w11
-; GISEL-NEXT: and w8, w8, w9
-; GISEL-NEXT: and w0, w8, #0x1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redand_v16i1:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: umov w8, v0.b[0]
+; CHECK-GI-NEXT: umov w9, v0.b[1]
+; CHECK-GI-NEXT: umov w10, v0.b[2]
+; CHECK-GI-NEXT: umov w11, v0.b[3]
+; CHECK-GI-NEXT: umov w12, v0.b[4]
+; CHECK-GI-NEXT: umov w13, v0.b[5]
+; CHECK-GI-NEXT: umov w14, v0.b[6]
+; CHECK-GI-NEXT: umov w15, v0.b[7]
+; CHECK-GI-NEXT: umov w16, v0.b[8]
+; CHECK-GI-NEXT: umov w17, v0.b[9]
+; CHECK-GI-NEXT: umov w18, v0.b[10]
+; CHECK-GI-NEXT: umov w0, v0.b[11]
+; CHECK-GI-NEXT: and w8, w8, w9
+; CHECK-GI-NEXT: umov w1, v0.b[12]
+; CHECK-GI-NEXT: umov w2, v0.b[13]
+; CHECK-GI-NEXT: and w9, w10, w11
+; CHECK-GI-NEXT: and w10, w12, w13
+; CHECK-GI-NEXT: umov w3, v0.b[14]
+; CHECK-GI-NEXT: and w11, w14, w15
+; CHECK-GI-NEXT: and w8, w8, w9
+; CHECK-GI-NEXT: umov w4, v0.b[15]
+; CHECK-GI-NEXT: and w12, w16, w17
+; CHECK-GI-NEXT: and w13, w18, w0
+; CHECK-GI-NEXT: and w9, w10, w11
+; CHECK-GI-NEXT: and w14, w1, w2
+; CHECK-GI-NEXT: and w10, w12, w13
+; CHECK-GI-NEXT: and w8, w8, w9
+; CHECK-GI-NEXT: and w15, w3, w4
+; CHECK-GI-NEXT: and w11, w14, w15
+; CHECK-GI-NEXT: and w9, w10, w11
+; CHECK-GI-NEXT: and w8, w8, w9
+; CHECK-GI-NEXT: and w0, w8, #0x1
+; CHECK-GI-NEXT: ret
%or_result = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> %a)
ret i1 %or_result
}
define <16 x i1> @test_redand_ins_v16i1(<16 x i1> %a) {
-; CHECK-LABEL: test_redand_ins_v16i1:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shl v0.16b, v0.16b, #7
-; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
-; CHECK-NEXT: uminv b0, v0.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redand_ins_v16i1:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shl v0.16b, v0.16b, #7
+; CHECK-SD-NEXT: cmlt v0.16b, v0.16b, #0
+; CHECK-SD-NEXT: uminv b0, v0.16b
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redand_ins_v16i1:
-; GISEL: // %bb.0:
-; GISEL-NEXT: umov w8, v0.b[0]
-; GISEL-NEXT: umov w9, v0.b[1]
-; GISEL-NEXT: umov w10, v0.b[2]
-; GISEL-NEXT: umov w11, v0.b[3]
-; GISEL-NEXT: umov w12, v0.b[4]
-; GISEL-NEXT: umov w13, v0.b[5]
-; GISEL-NEXT: umov w14, v0.b[6]
-; GISEL-NEXT: umov w15, v0.b[7]
-; GISEL-NEXT: umov w16, v0.b[8]
-; GISEL-NEXT: umov w17, v0.b[9]
-; GISEL-NEXT: umov w18, v0.b[10]
-; GISEL-NEXT: umov w0, v0.b[11]
-; GISEL-NEXT: and w8, w8, w9
-; GISEL-NEXT: umov w1, v0.b[12]
-; GISEL-NEXT: umov w2, v0.b[13]
-; GISEL-NEXT: and w9, w10, w11
-; GISEL-NEXT: and w10, w12, w13
-; GISEL-NEXT: umov w3, v0.b[14]
-; GISEL-NEXT: and w11, w14, w15
-; GISEL-NEXT: and w8, w8, w9
-; GISEL-NEXT: umov w4, v0.b[15]
-; GISEL-NEXT: and w12, w16, w17
-; GISEL-NEXT: and w13, w18, w0
-; GISEL-NEXT: and w9, w10, w11
-; GISEL-NEXT: and w14, w1, w2
-; GISEL-NEXT: and w10, w12, w13
-; GISEL-NEXT: and w8, w8, w9
-; GISEL-NEXT: and w15, w3, w4
-; GISEL-NEXT: and w11, w14, w15
-; GISEL-NEXT: and w9, w10, w11
-; GISEL-NEXT: and w8, w8, w9
-; GISEL-NEXT: fmov s0, w8
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redand_ins_v16i1:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: umov w8, v0.b[0]
+; CHECK-GI-NEXT: umov w9, v0.b[1]
+; CHECK-GI-NEXT: umov w10, v0.b[2]
+; CHECK-GI-NEXT: umov w11, v0.b[3]
+; CHECK-GI-NEXT: umov w12, v0.b[4]
+; CHECK-GI-NEXT: umov w13, v0.b[5]
+; CHECK-GI-NEXT: umov w14, v0.b[6]
+; CHECK-GI-NEXT: umov w15, v0.b[7]
+; CHECK-GI-NEXT: umov w16, v0.b[8]
+; CHECK-GI-NEXT: umov w17, v0.b[9]
+; CHECK-GI-NEXT: umov w18, v0.b[10]
+; CHECK-GI-NEXT: umov w0, v0.b[11]
+; CHECK-GI-NEXT: and w8, w8, w9
+; CHECK-GI-NEXT: umov w1, v0.b[12]
+; CHECK-GI-NEXT: umov w2, v0.b[13]
+; CHECK-GI-NEXT: and w9, w10, w11
+; CHECK-GI-NEXT: and w10, w12, w13
+; CHECK-GI-NEXT: umov w3, v0.b[14]
+; CHECK-GI-NEXT: and w11, w14, w15
+; CHECK-GI-NEXT: and w8, w8, w9
+; CHECK-GI-NEXT: umov w4, v0.b[15]
+; CHECK-GI-NEXT: and w12, w16, w17
+; CHECK-GI-NEXT: and w13, w18, w0
+; CHECK-GI-NEXT: and w9, w10, w11
+; CHECK-GI-NEXT: and w14, w1, w2
+; CHECK-GI-NEXT: and w10, w12, w13
+; CHECK-GI-NEXT: and w8, w8, w9
+; CHECK-GI-NEXT: and w15, w3, w4
+; CHECK-GI-NEXT: and w11, w14, w15
+; CHECK-GI-NEXT: and w9, w10, w11
+; CHECK-GI-NEXT: and w8, w8, w9
+; CHECK-GI-NEXT: fmov s0, w8
+; CHECK-GI-NEXT: ret
%and_result = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> %a)
%ins = insertelement <16 x i1> poison, i1 %and_result, i64 0
ret <16 x i1> %ins
@@ -202,348 +197,342 @@ define i8 @test_redand_v1i8(<1 x i8> %a) {
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w0, v0.b[0]
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_redand_v1i8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; GISEL-NEXT: umov w0, v0.b[0]
-; GISEL-NEXT: ret
%and_result = call i8 @llvm.vector.reduce.and.v1i8(<1 x i8> %a)
ret i8 %and_result
}
define i8 @test_redand_v3i8(<3 x i8> %a) {
-; CHECK-LABEL: test_redand_v3i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi d0, #0xff00ff00ff00ff
-; CHECK-NEXT: mov v0.h[0], w0
-; CHECK-NEXT: mov v0.h[1], w1
-; CHECK-NEXT: mov v0.h[2], w2
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: and x8, x8, x8, lsr #32
-; CHECK-NEXT: lsr x9, x8, #16
-; CHECK-NEXT: and w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redand_v3i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi d0, #0xff00ff00ff00ff
+; CHECK-SD-NEXT: mov v0.h[0], w0
+; CHECK-SD-NEXT: mov v0.h[1], w1
+; CHECK-SD-NEXT: mov v0.h[2], w2
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: and x8, x8, x8, lsr #32
+; CHECK-SD-NEXT: lsr x9, x8, #16
+; CHECK-SD-NEXT: and w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redand_v3i8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: and w8, w0, w1
-; GISEL-NEXT: and w0, w8, w2
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redand_v3i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: and w8, w0, w1
+; CHECK-GI-NEXT: and w0, w8, w2
+; CHECK-GI-NEXT: ret
%and_result = call i8 @llvm.vector.reduce.and.v3i8(<3 x i8> %a)
ret i8 %and_result
}
define i8 @test_redand_v4i8(<4 x i8> %a) {
-; CHECK-LABEL: test_redand_v4i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: and x8, x8, x8, lsr #32
-; CHECK-NEXT: lsr x9, x8, #16
-; CHECK-NEXT: and w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redand_v4i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: and x8, x8, x8, lsr #32
+; CHECK-SD-NEXT: lsr x9, x8, #16
+; CHECK-SD-NEXT: and w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redand_v4i8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; GISEL-NEXT: umov w8, v0.h[0]
-; GISEL-NEXT: umov w9, v0.h[1]
-; GISEL-NEXT: umov w10, v0.h[2]
-; GISEL-NEXT: umov w11, v0.h[3]
-; GISEL-NEXT: and w8, w8, w9
-; GISEL-NEXT: and w9, w10, w11
-; GISEL-NEXT: and w0, w8, w9
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redand_v4i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: umov w8, v0.h[0]
+; CHECK-GI-NEXT: umov w9, v0.h[1]
+; CHECK-GI-NEXT: umov w10, v0.h[2]
+; CHECK-GI-NEXT: umov w11, v0.h[3]
+; CHECK-GI-NEXT: and w8, w8, w9
+; CHECK-GI-NEXT: and w9, w10, w11
+; CHECK-GI-NEXT: and w0, w8, w9
+; CHECK-GI-NEXT: ret
%and_result = call i8 @llvm.vector.reduce.and.v4i8(<4 x i8> %a)
ret i8 %and_result
}
define i8 @test_redand_v8i8(<8 x i8> %a) {
-; CHECK-LABEL: test_redand_v8i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: and x8, x8, x8, lsr #32
-; CHECK-NEXT: and x8, x8, x8, lsr #16
-; CHECK-NEXT: lsr x9, x8, #8
-; CHECK-NEXT: and w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redand_v8i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: and x8, x8, x8, lsr #32
+; CHECK-SD-NEXT: and x8, x8, x8, lsr #16
+; CHECK-SD-NEXT: lsr x9, x8, #8
+; CHECK-SD-NEXT: and w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redand_v8i8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; GISEL-NEXT: umov w8, v0.b[0]
-; GISEL-NEXT: umov w9, v0.b[1]
-; GISEL-NEXT: umov w10, v0.b[2]
-; GISEL-NEXT: umov w11, v0.b[3]
-; GISEL-NEXT: umov w12, v0.b[4]
-; GISEL-NEXT: umov w13, v0.b[5]
-; GISEL-NEXT: umov w14, v0.b[6]
-; GISEL-NEXT: umov w15, v0.b[7]
-; GISEL-NEXT: and w8, w8, w9
-; GISEL-NEXT: and w9, w10, w11
-; GISEL-NEXT: and w10, w12, w13
-; GISEL-NEXT: and w11, w14, w15
-; GISEL-NEXT: and w8, w8, w9
-; GISEL-NEXT: and w9, w10, w11
-; GISEL-NEXT: and w0, w8, w9
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redand_v8i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: umov w8, v0.b[0]
+; CHECK-GI-NEXT: umov w9, v0.b[1]
+; CHECK-GI-NEXT: umov w10, v0.b[2]
+; CHECK-GI-NEXT: umov w11, v0.b[3]
+; CHECK-GI-NEXT: umov w12, v0.b[4]
+; CHECK-GI-NEXT: umov w13, v0.b[5]
+; CHECK-GI-NEXT: umov w14, v0.b[6]
+; CHECK-GI-NEXT: umov w15, v0.b[7]
+; CHECK-GI-NEXT: and w8, w8, w9
+; CHECK-GI-NEXT: and w9, w10, w11
+; CHECK-GI-NEXT: and w10, w12, w13
+; CHECK-GI-NEXT: and w11, w14, w15
+; CHECK-GI-NEXT: and w8, w8, w9
+; CHECK-GI-NEXT: and w9, w10, w11
+; CHECK-GI-NEXT: and w0, w8, w9
+; CHECK-GI-NEXT: ret
%and_result = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> %a)
ret i8 %and_result
}
define i8 @test_redand_v16i8(<16 x i8> %a) {
-; CHECK-LABEL: test_redand_v16i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: and x8, x8, x8, lsr #32
-; CHECK-NEXT: and x8, x8, x8, lsr #16
-; CHECK-NEXT: lsr x9, x8, #8
-; CHECK-NEXT: and w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redand_v16i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: and x8, x8, x8, lsr #32
+; CHECK-SD-NEXT: and x8, x8, x8, lsr #16
+; CHECK-SD-NEXT: lsr x9, x8, #8
+; CHECK-SD-NEXT: and w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redand_v16i8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov d1, v0.d[1]
-; GISEL-NEXT: and v0.8b, v0.8b, v1.8b
-; GISEL-NEXT: umov w8, v0.b[0]
-; GISEL-NEXT: umov w9, v0.b[1]
-; GISEL-NEXT: umov w10, v0.b[2]
-; GISEL-NEXT: umov w11, v0.b[3]
-; GISEL-NEXT: umov w12, v0.b[4]
-; GISEL-NEXT: umov w13, v0.b[5]
-; GISEL-NEXT: umov w14, v0.b[6]
-; GISEL-NEXT: umov w15, v0.b[7]
-; GISEL-NEXT: and w8, w8, w9
-; GISEL-NEXT: and w9, w10, w11
-; GISEL-NEXT: and w10, w12, w13
-; GISEL-NEXT: and w11, w14, w15
-; GISEL-NEXT: and w8, w8, w9
-; GISEL-NEXT: and w9, w10, w11
-; GISEL-NEXT: and w0, w8, w9
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redand_v16i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: umov w8, v0.b[0]
+; CHECK-GI-NEXT: umov w9, v0.b[1]
+; CHECK-GI-NEXT: umov w10, v0.b[2]
+; CHECK-GI-NEXT: umov w11, v0.b[3]
+; CHECK-GI-NEXT: umov w12, v0.b[4]
+; CHECK-GI-NEXT: umov w13, v0.b[5]
+; CHECK-GI-NEXT: umov w14, v0.b[6]
+; CHECK-GI-NEXT: umov w15, v0.b[7]
+; CHECK-GI-NEXT: and w8, w8, w9
+; CHECK-GI-NEXT: and w9, w10, w11
+; CHECK-GI-NEXT: and w10, w12, w13
+; CHECK-GI-NEXT: and w11, w14, w15
+; CHECK-GI-NEXT: and w8, w8, w9
+; CHECK-GI-NEXT: and w9, w10, w11
+; CHECK-GI-NEXT: and w0, w8, w9
+; CHECK-GI-NEXT: ret
%and_result = call i8 @llvm.vector.reduce.and.v16i8(<16 x i8> %a)
ret i8 %and_result
}
define i8 @test_redand_v32i8(<32 x i8> %a) {
-; CHECK-LABEL: test_redand_v32i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: and x8, x8, x8, lsr #32
-; CHECK-NEXT: and x8, x8, x8, lsr #16
-; CHECK-NEXT: lsr x9, x8, #8
-; CHECK-NEXT: and w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redand_v32i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: and x8, x8, x8, lsr #32
+; CHECK-SD-NEXT: and x8, x8, x8, lsr #16
+; CHECK-SD-NEXT: lsr x9, x8, #8
+; CHECK-SD-NEXT: and w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redand_v32i8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: and v0.16b, v0.16b, v1.16b
-; GISEL-NEXT: mov d1, v0.d[1]
-; GISEL-NEXT: and v0.8b, v0.8b, v1.8b
-; GISEL-NEXT: umov w8, v0.b[0]
-; GISEL-NEXT: umov w9, v0.b[1]
-; GISEL-NEXT: umov w10, v0.b[2]
-; GISEL-NEXT: umov w11, v0.b[3]
-; GISEL-NEXT: umov w12, v0.b[4]
-; GISEL-NEXT: umov w13, v0.b[5]
-; GISEL-NEXT: umov w14, v0.b[6]
-; GISEL-NEXT: umov w15, v0.b[7]
-; GISEL-NEXT: and w8, w8, w9
-; GISEL-NEXT: and w9, w10, w11
-; GISEL-NEXT: and w10, w12, w13
-; GISEL-NEXT: and w11, w14, w15
-; GISEL-NEXT: and w8, w8, w9
-; GISEL-NEXT: and w9, w10, w11
-; GISEL-NEXT: and w0, w8, w9
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redand_v32i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: umov w8, v0.b[0]
+; CHECK-GI-NEXT: umov w9, v0.b[1]
+; CHECK-GI-NEXT: umov w10, v0.b[2]
+; CHECK-GI-NEXT: umov w11, v0.b[3]
+; CHECK-GI-NEXT: umov w12, v0.b[4]
+; CHECK-GI-NEXT: umov w13, v0.b[5]
+; CHECK-GI-NEXT: umov w14, v0.b[6]
+; CHECK-GI-NEXT: umov w15, v0.b[7]
+; CHECK-GI-NEXT: and w8, w8, w9
+; CHECK-GI-NEXT: and w9, w10, w11
+; CHECK-GI-NEXT: and w10, w12, w13
+; CHECK-GI-NEXT: and w11, w14, w15
+; CHECK-GI-NEXT: and w8, w8, w9
+; CHECK-GI-NEXT: and w9, w10, w11
+; CHECK-GI-NEXT: and w0, w8, w9
+; CHECK-GI-NEXT: ret
%and_result = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> %a)
ret i8 %and_result
}
define i16 @test_redand_v4i16(<4 x i16> %a) {
-; CHECK-LABEL: test_redand_v4i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: and x8, x8, x8, lsr #32
-; CHECK-NEXT: lsr x9, x8, #16
-; CHECK-NEXT: and w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redand_v4i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: and x8, x8, x8, lsr #32
+; CHECK-SD-NEXT: lsr x9, x8, #16
+; CHECK-SD-NEXT: and w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redand_v4i16:
-; GISEL: // %bb.0:
-; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; GISEL-NEXT: umov w8, v0.h[0]
-; GISEL-NEXT: umov w9, v0.h[1]
-; GISEL-NEXT: umov w10, v0.h[2]
-; GISEL-NEXT: umov w11, v0.h[3]
-; GISEL-NEXT: and w8, w8, w9
-; GISEL-NEXT: and w9, w10, w11
-; GISEL-NEXT: and w0, w8, w9
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redand_v4i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: umov w8, v0.h[0]
+; CHECK-GI-NEXT: umov w9, v0.h[1]
+; CHECK-GI-NEXT: umov w10, v0.h[2]
+; CHECK-GI-NEXT: umov w11, v0.h[3]
+; CHECK-GI-NEXT: and w8, w8, w9
+; CHECK-GI-NEXT: and w9, w10, w11
+; CHECK-GI-NEXT: and w0, w8, w9
+; CHECK-GI-NEXT: ret
%and_result = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> %a)
ret i16 %and_result
}
define i16 @test_redand_v8i16(<8 x i16> %a) {
-; CHECK-LABEL: test_redand_v8i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: and x8, x8, x8, lsr #32
-; CHECK-NEXT: lsr x9, x8, #16
-; CHECK-NEXT: and w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redand_v8i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: and x8, x8, x8, lsr #32
+; CHECK-SD-NEXT: lsr x9, x8, #16
+; CHECK-SD-NEXT: and w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redand_v8i16:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov d1, v0.d[1]
-; GISEL-NEXT: and v0.8b, v0.8b, v1.8b
-; GISEL-NEXT: umov w8, v0.h[0]
-; GISEL-NEXT: umov w9, v0.h[1]
-; GISEL-NEXT: umov w10, v0.h[2]
-; GISEL-NEXT: umov w11, v0.h[3]
-; GISEL-NEXT: and w8, w8, w9
-; GISEL-NEXT: and w9, w10, w11
-; GISEL-NEXT: and w0, w8, w9
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redand_v8i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: umov w8, v0.h[0]
+; CHECK-GI-NEXT: umov w9, v0.h[1]
+; CHECK-GI-NEXT: umov w10, v0.h[2]
+; CHECK-GI-NEXT: umov w11, v0.h[3]
+; CHECK-GI-NEXT: and w8, w8, w9
+; CHECK-GI-NEXT: and w9, w10, w11
+; CHECK-GI-NEXT: and w0, w8, w9
+; CHECK-GI-NEXT: ret
%and_result = call i16 @llvm.vector.reduce.and.v8i16(<8 x i16> %a)
ret i16 %and_result
}
define i16 @test_redand_v16i16(<16 x i16> %a) {
-; CHECK-LABEL: test_redand_v16i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: and x8, x8, x8, lsr #32
-; CHECK-NEXT: lsr x9, x8, #16
-; CHECK-NEXT: and w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redand_v16i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: and x8, x8, x8, lsr #32
+; CHECK-SD-NEXT: lsr x9, x8, #16
+; CHECK-SD-NEXT: and w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redand_v16i16:
-; GISEL: // %bb.0:
-; GISEL-NEXT: and v0.16b, v0.16b, v1.16b
-; GISEL-NEXT: mov d1, v0.d[1]
-; GISEL-NEXT: and v0.8b, v0.8b, v1.8b
-; GISEL-NEXT: umov w8, v0.h[0]
-; GISEL-NEXT: umov w9, v0.h[1]
-; GISEL-NEXT: umov w10, v0.h[2]
-; GISEL-NEXT: umov w11, v0.h[3]
-; GISEL-NEXT: and w8, w8, w9
-; GISEL-NEXT: and w9, w10, w11
-; GISEL-NEXT: and w0, w8, w9
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redand_v16i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: umov w8, v0.h[0]
+; CHECK-GI-NEXT: umov w9, v0.h[1]
+; CHECK-GI-NEXT: umov w10, v0.h[2]
+; CHECK-GI-NEXT: umov w11, v0.h[3]
+; CHECK-GI-NEXT: and w8, w8, w9
+; CHECK-GI-NEXT: and w9, w10, w11
+; CHECK-GI-NEXT: and w0, w8, w9
+; CHECK-GI-NEXT: ret
%and_result = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %a)
ret i16 %and_result
}
define i32 @test_redand_v2i32(<2 x i32> %a) {
-; CHECK-LABEL: test_redand_v2i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: lsr x9, x8, #32
-; CHECK-NEXT: and w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redand_v2i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: lsr x9, x8, #32
+; CHECK-SD-NEXT: and w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redand_v2i32:
-; GISEL: // %bb.0:
-; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; GISEL-NEXT: mov w8, v0.s[1]
-; GISEL-NEXT: fmov w9, s0
-; GISEL-NEXT: and w0, w9, w8
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redand_v2i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: mov w8, v0.s[1]
+; CHECK-GI-NEXT: fmov w9, s0
+; CHECK-GI-NEXT: and w0, w9, w8
+; CHECK-GI-NEXT: ret
%and_result = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> %a)
ret i32 %and_result
}
define i32 @test_redand_v4i32(<4 x i32> %a) {
-; CHECK-LABEL: test_redand_v4i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: lsr x9, x8, #32
-; CHECK-NEXT: and w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redand_v4i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: lsr x9, x8, #32
+; CHECK-SD-NEXT: and w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redand_v4i32:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov d1, v0.d[1]
-; GISEL-NEXT: and v0.8b, v0.8b, v1.8b
-; GISEL-NEXT: mov w8, v0.s[1]
-; GISEL-NEXT: fmov w9, s0
-; GISEL-NEXT: and w0, w9, w8
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redand_v4i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: mov w8, v0.s[1]
+; CHECK-GI-NEXT: fmov w9, s0
+; CHECK-GI-NEXT: and w0, w9, w8
+; CHECK-GI-NEXT: ret
%and_result = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %a)
ret i32 %and_result
}
define i32 @test_redand_v8i32(<8 x i32> %a) {
-; CHECK-LABEL: test_redand_v8i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: lsr x9, x8, #32
-; CHECK-NEXT: and w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redand_v8i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: lsr x9, x8, #32
+; CHECK-SD-NEXT: and w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redand_v8i32:
-; GISEL: // %bb.0:
-; GISEL-NEXT: and v0.16b, v0.16b, v1.16b
-; GISEL-NEXT: mov d1, v0.d[1]
-; GISEL-NEXT: and v0.8b, v0.8b, v1.8b
-; GISEL-NEXT: mov w8, v0.s[1]
-; GISEL-NEXT: fmov w9, s0
-; GISEL-NEXT: and w0, w9, w8
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redand_v8i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: mov w8, v0.s[1]
+; CHECK-GI-NEXT: fmov w9, s0
+; CHECK-GI-NEXT: and w0, w9, w8
+; CHECK-GI-NEXT: ret
%and_result = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %a)
ret i32 %and_result
}
define i64 @test_redand_v2i64(<2 x i64> %a) {
-; CHECK-LABEL: test_redand_v2i64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redand_v2i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redand_v2i64:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov x8, v0.d[1]
-; GISEL-NEXT: fmov x9, d0
-; GISEL-NEXT: and x0, x9, x8
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redand_v2i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: fmov x9, d0
+; CHECK-GI-NEXT: and x0, x9, x8
+; CHECK-GI-NEXT: ret
%and_result = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> %a)
ret i64 %and_result
}
define i64 @test_redand_v4i64(<4 x i64> %a) {
-; CHECK-LABEL: test_redand_v4i64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redand_v4i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redand_v4i64:
-; GISEL: // %bb.0:
-; GISEL-NEXT: and v0.16b, v0.16b, v1.16b
-; GISEL-NEXT: mov x8, v0.d[1]
-; GISEL-NEXT: fmov x9, d0
-; GISEL-NEXT: and x0, x9, x8
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redand_v4i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: fmov x9, d0
+; CHECK-GI-NEXT: and x0, x9, x8
+; CHECK-GI-NEXT: ret
%and_result = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %a)
ret i64 %and_result
}
diff --git a/llvm/test/CodeGen/AArch64/reduce-or.ll b/llvm/test/CodeGen/AArch64/reduce-or.ll
index f5291f5debb40..c52c5e5d34f1d 100644
--- a/llvm/test/CodeGen/AArch64/reduce-or.ll
+++ b/llvm/test/CodeGen/AArch64/reduce-or.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
-; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=1 | FileCheck %s --check-prefix=GISEL
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define i1 @test_redor_v1i1(<1 x i1> %a) {
@@ -8,189 +8,184 @@ define i1 @test_redor_v1i1(<1 x i1> %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: and w0, w0, #0x1
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_redor_v1i1:
-; GISEL: // %bb.0:
-; GISEL-NEXT: and w0, w0, #0x1
-; GISEL-NEXT: ret
%or_result = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> %a)
ret i1 %or_result
}
define i1 @test_redor_v2i1(<2 x i1> %a) {
-; CHECK-LABEL: test_redor_v2i1:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shl v0.2s, v0.2s, #31
-; CHECK-NEXT: cmlt v0.2s, v0.2s, #0
-; CHECK-NEXT: umaxp v0.2s, v0.2s, v0.2s
-; CHECK-NEXT: fmov w8, s0
-; CHECK-NEXT: and w0, w8, #0x1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redor_v2i1:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shl v0.2s, v0.2s, #31
+; CHECK-SD-NEXT: cmlt v0.2s, v0.2s, #0
+; CHECK-SD-NEXT: umaxp v0.2s, v0.2s, v0.2s
+; CHECK-SD-NEXT: fmov w8, s0
+; CHECK-SD-NEXT: and w0, w8, #0x1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redor_v2i1:
-; GISEL: // %bb.0:
-; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; GISEL-NEXT: mov w8, v0.s[1]
-; GISEL-NEXT: fmov w9, s0
-; GISEL-NEXT: orr w8, w9, w8
-; GISEL-NEXT: and w0, w8, #0x1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redor_v2i1:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: mov w8, v0.s[1]
+; CHECK-GI-NEXT: fmov w9, s0
+; CHECK-GI-NEXT: orr w8, w9, w8
+; CHECK-GI-NEXT: and w0, w8, #0x1
+; CHECK-GI-NEXT: ret
%or_result = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %a)
ret i1 %or_result
}
define i1 @test_redor_v4i1(<4 x i1> %a) {
-; CHECK-LABEL: test_redor_v4i1:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shl v0.4h, v0.4h, #15
-; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
-; CHECK-NEXT: umaxv h0, v0.4h
-; CHECK-NEXT: fmov w8, s0
-; CHECK-NEXT: and w0, w8, #0x1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redor_v4i1:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shl v0.4h, v0.4h, #15
+; CHECK-SD-NEXT: cmlt v0.4h, v0.4h, #0
+; CHECK-SD-NEXT: umaxv h0, v0.4h
+; CHECK-SD-NEXT: fmov w8, s0
+; CHECK-SD-NEXT: and w0, w8, #0x1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redor_v4i1:
-; GISEL: // %bb.0:
-; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; GISEL-NEXT: umov w8, v0.h[0]
-; GISEL-NEXT: umov w9, v0.h[1]
-; GISEL-NEXT: umov w10, v0.h[2]
-; GISEL-NEXT: umov w11, v0.h[3]
-; GISEL-NEXT: orr w8, w8, w9
-; GISEL-NEXT: orr w9, w10, w11
-; GISEL-NEXT: orr w8, w8, w9
-; GISEL-NEXT: and w0, w8, #0x1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redor_v4i1:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: umov w8, v0.h[0]
+; CHECK-GI-NEXT: umov w9, v0.h[1]
+; CHECK-GI-NEXT: umov w10, v0.h[2]
+; CHECK-GI-NEXT: umov w11, v0.h[3]
+; CHECK-GI-NEXT: orr w8, w8, w9
+; CHECK-GI-NEXT: orr w9, w10, w11
+; CHECK-GI-NEXT: orr w8, w8, w9
+; CHECK-GI-NEXT: and w0, w8, #0x1
+; CHECK-GI-NEXT: ret
%or_result = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> %a)
ret i1 %or_result
}
define i1 @test_redor_v8i1(<8 x i1> %a) {
-; CHECK-LABEL: test_redor_v8i1:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shl v0.8b, v0.8b, #7
-; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
-; CHECK-NEXT: umaxv b0, v0.8b
-; CHECK-NEXT: fmov w8, s0
-; CHECK-NEXT: and w0, w8, #0x1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redor_v8i1:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shl v0.8b, v0.8b, #7
+; CHECK-SD-NEXT: cmlt v0.8b, v0.8b, #0
+; CHECK-SD-NEXT: umaxv b0, v0.8b
+; CHECK-SD-NEXT: fmov w8, s0
+; CHECK-SD-NEXT: and w0, w8, #0x1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redor_v8i1:
-; GISEL: // %bb.0:
-; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; GISEL-NEXT: umov w8, v0.b[0]
-; GISEL-NEXT: umov w9, v0.b[1]
-; GISEL-NEXT: umov w10, v0.b[2]
-; GISEL-NEXT: umov w11, v0.b[3]
-; GISEL-NEXT: umov w12, v0.b[4]
-; GISEL-NEXT: umov w13, v0.b[5]
-; GISEL-NEXT: umov w14, v0.b[6]
-; GISEL-NEXT: umov w15, v0.b[7]
-; GISEL-NEXT: orr w8, w8, w9
-; GISEL-NEXT: orr w9, w10, w11
-; GISEL-NEXT: orr w10, w12, w13
-; GISEL-NEXT: orr w11, w14, w15
-; GISEL-NEXT: orr w8, w8, w9
-; GISEL-NEXT: orr w9, w10, w11
-; GISEL-NEXT: orr w8, w8, w9
-; GISEL-NEXT: and w0, w8, #0x1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redor_v8i1:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: umov w8, v0.b[0]
+; CHECK-GI-NEXT: umov w9, v0.b[1]
+; CHECK-GI-NEXT: umov w10, v0.b[2]
+; CHECK-GI-NEXT: umov w11, v0.b[3]
+; CHECK-GI-NEXT: umov w12, v0.b[4]
+; CHECK-GI-NEXT: umov w13, v0.b[5]
+; CHECK-GI-NEXT: umov w14, v0.b[6]
+; CHECK-GI-NEXT: umov w15, v0.b[7]
+; CHECK-GI-NEXT: orr w8, w8, w9
+; CHECK-GI-NEXT: orr w9, w10, w11
+; CHECK-GI-NEXT: orr w10, w12, w13
+; CHECK-GI-NEXT: orr w11, w14, w15
+; CHECK-GI-NEXT: orr w8, w8, w9
+; CHECK-GI-NEXT: orr w9, w10, w11
+; CHECK-GI-NEXT: orr w8, w8, w9
+; CHECK-GI-NEXT: and w0, w8, #0x1
+; CHECK-GI-NEXT: ret
%or_result = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> %a)
ret i1 %or_result
}
define i1 @test_redor_v16i1(<16 x i1> %a) {
-; CHECK-LABEL: test_redor_v16i1:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shl v0.16b, v0.16b, #7
-; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
-; CHECK-NEXT: umaxv b0, v0.16b
-; CHECK-NEXT: fmov w8, s0
-; CHECK-NEXT: and w0, w8, #0x1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redor_v16i1:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shl v0.16b, v0.16b, #7
+; CHECK-SD-NEXT: cmlt v0.16b, v0.16b, #0
+; CHECK-SD-NEXT: umaxv b0, v0.16b
+; CHECK-SD-NEXT: fmov w8, s0
+; CHECK-SD-NEXT: and w0, w8, #0x1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redor_v16i1:
-; GISEL: // %bb.0:
-; GISEL-NEXT: umov w8, v0.b[0]
-; GISEL-NEXT: umov w9, v0.b[1]
-; GISEL-NEXT: umov w10, v0.b[2]
-; GISEL-NEXT: umov w11, v0.b[3]
-; GISEL-NEXT: umov w12, v0.b[4]
-; GISEL-NEXT: umov w13, v0.b[5]
-; GISEL-NEXT: umov w14, v0.b[6]
-; GISEL-NEXT: umov w15, v0.b[7]
-; GISEL-NEXT: umov w16, v0.b[8]
-; GISEL-NEXT: umov w17, v0.b[9]
-; GISEL-NEXT: umov w18, v0.b[10]
-; GISEL-NEXT: umov w0, v0.b[11]
-; GISEL-NEXT: orr w8, w8, w9
-; GISEL-NEXT: umov w1, v0.b[12]
-; GISEL-NEXT: umov w2, v0.b[13]
-; GISEL-NEXT: orr w9, w10, w11
-; GISEL-NEXT: orr w10, w12, w13
-; GISEL-NEXT: umov w3, v0.b[14]
-; GISEL-NEXT: orr w11, w14, w15
-; GISEL-NEXT: orr w8, w8, w9
-; GISEL-NEXT: umov w4, v0.b[15]
-; GISEL-NEXT: orr w12, w16, w17
-; GISEL-NEXT: orr w13, w18, w0
-; GISEL-NEXT: orr w9, w10, w11
-; GISEL-NEXT: orr w14, w1, w2
-; GISEL-NEXT: orr w10, w12, w13
-; GISEL-NEXT: orr w8, w8, w9
-; GISEL-NEXT: orr w15, w3, w4
-; GISEL-NEXT: orr w11, w14, w15
-; GISEL-NEXT: orr w9, w10, w11
-; GISEL-NEXT: orr w8, w8, w9
-; GISEL-NEXT: and w0, w8, #0x1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redor_v16i1:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: umov w8, v0.b[0]
+; CHECK-GI-NEXT: umov w9, v0.b[1]
+; CHECK-GI-NEXT: umov w10, v0.b[2]
+; CHECK-GI-NEXT: umov w11, v0.b[3]
+; CHECK-GI-NEXT: umov w12, v0.b[4]
+; CHECK-GI-NEXT: umov w13, v0.b[5]
+; CHECK-GI-NEXT: umov w14, v0.b[6]
+; CHECK-GI-NEXT: umov w15, v0.b[7]
+; CHECK-GI-NEXT: umov w16, v0.b[8]
+; CHECK-GI-NEXT: umov w17, v0.b[9]
+; CHECK-GI-NEXT: umov w18, v0.b[10]
+; CHECK-GI-NEXT: umov w0, v0.b[11]
+; CHECK-GI-NEXT: orr w8, w8, w9
+; CHECK-GI-NEXT: umov w1, v0.b[12]
+; CHECK-GI-NEXT: umov w2, v0.b[13]
+; CHECK-GI-NEXT: orr w9, w10, w11
+; CHECK-GI-NEXT: orr w10, w12, w13
+; CHECK-GI-NEXT: umov w3, v0.b[14]
+; CHECK-GI-NEXT: orr w11, w14, w15
+; CHECK-GI-NEXT: orr w8, w8, w9
+; CHECK-GI-NEXT: umov w4, v0.b[15]
+; CHECK-GI-NEXT: orr w12, w16, w17
+; CHECK-GI-NEXT: orr w13, w18, w0
+; CHECK-GI-NEXT: orr w9, w10, w11
+; CHECK-GI-NEXT: orr w14, w1, w2
+; CHECK-GI-NEXT: orr w10, w12, w13
+; CHECK-GI-NEXT: orr w8, w8, w9
+; CHECK-GI-NEXT: orr w15, w3, w4
+; CHECK-GI-NEXT: orr w11, w14, w15
+; CHECK-GI-NEXT: orr w9, w10, w11
+; CHECK-GI-NEXT: orr w8, w8, w9
+; CHECK-GI-NEXT: and w0, w8, #0x1
+; CHECK-GI-NEXT: ret
%or_result = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> %a)
ret i1 %or_result
}
define <16 x i1> @test_redor_ins_v16i1(<16 x i1> %a) {
-; CHECK-LABEL: test_redor_ins_v16i1:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shl v0.16b, v0.16b, #7
-; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
-; CHECK-NEXT: umaxv b0, v0.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redor_ins_v16i1:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shl v0.16b, v0.16b, #7
+; CHECK-SD-NEXT: cmlt v0.16b, v0.16b, #0
+; CHECK-SD-NEXT: umaxv b0, v0.16b
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redor_ins_v16i1:
-; GISEL: // %bb.0:
-; GISEL-NEXT: umov w8, v0.b[0]
-; GISEL-NEXT: umov w9, v0.b[1]
-; GISEL-NEXT: umov w10, v0.b[2]
-; GISEL-NEXT: umov w11, v0.b[3]
-; GISEL-NEXT: umov w12, v0.b[4]
-; GISEL-NEXT: umov w13, v0.b[5]
-; GISEL-NEXT: umov w14, v0.b[6]
-; GISEL-NEXT: umov w15, v0.b[7]
-; GISEL-NEXT: umov w16, v0.b[8]
-; GISEL-NEXT: umov w17, v0.b[9]
-; GISEL-NEXT: umov w18, v0.b[10]
-; GISEL-NEXT: umov w0, v0.b[11]
-; GISEL-NEXT: orr w8, w8, w9
-; GISEL-NEXT: umov w1, v0.b[12]
-; GISEL-NEXT: umov w2, v0.b[13]
-; GISEL-NEXT: orr w9, w10, w11
-; GISEL-NEXT: orr w10, w12, w13
-; GISEL-NEXT: umov w3, v0.b[14]
-; GISEL-NEXT: orr w11, w14, w15
-; GISEL-NEXT: orr w8, w8, w9
-; GISEL-NEXT: umov w4, v0.b[15]
-; GISEL-NEXT: orr w12, w16, w17
-; GISEL-NEXT: orr w13, w18, w0
-; GISEL-NEXT: orr w9, w10, w11
-; GISEL-NEXT: orr w14, w1, w2
-; GISEL-NEXT: orr w10, w12, w13
-; GISEL-NEXT: orr w8, w8, w9
-; GISEL-NEXT: orr w15, w3, w4
-; GISEL-NEXT: orr w11, w14, w15
-; GISEL-NEXT: orr w9, w10, w11
-; GISEL-NEXT: orr w8, w8, w9
-; GISEL-NEXT: fmov s0, w8
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redor_ins_v16i1:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: umov w8, v0.b[0]
+; CHECK-GI-NEXT: umov w9, v0.b[1]
+; CHECK-GI-NEXT: umov w10, v0.b[2]
+; CHECK-GI-NEXT: umov w11, v0.b[3]
+; CHECK-GI-NEXT: umov w12, v0.b[4]
+; CHECK-GI-NEXT: umov w13, v0.b[5]
+; CHECK-GI-NEXT: umov w14, v0.b[6]
+; CHECK-GI-NEXT: umov w15, v0.b[7]
+; CHECK-GI-NEXT: umov w16, v0.b[8]
+; CHECK-GI-NEXT: umov w17, v0.b[9]
+; CHECK-GI-NEXT: umov w18, v0.b[10]
+; CHECK-GI-NEXT: umov w0, v0.b[11]
+; CHECK-GI-NEXT: orr w8, w8, w9
+; CHECK-GI-NEXT: umov w1, v0.b[12]
+; CHECK-GI-NEXT: umov w2, v0.b[13]
+; CHECK-GI-NEXT: orr w9, w10, w11
+; CHECK-GI-NEXT: orr w10, w12, w13
+; CHECK-GI-NEXT: umov w3, v0.b[14]
+; CHECK-GI-NEXT: orr w11, w14, w15
+; CHECK-GI-NEXT: orr w8, w8, w9
+; CHECK-GI-NEXT: umov w4, v0.b[15]
+; CHECK-GI-NEXT: orr w12, w16, w17
+; CHECK-GI-NEXT: orr w13, w18, w0
+; CHECK-GI-NEXT: orr w9, w10, w11
+; CHECK-GI-NEXT: orr w14, w1, w2
+; CHECK-GI-NEXT: orr w10, w12, w13
+; CHECK-GI-NEXT: orr w8, w8, w9
+; CHECK-GI-NEXT: orr w15, w3, w4
+; CHECK-GI-NEXT: orr w11, w14, w15
+; CHECK-GI-NEXT: orr w9, w10, w11
+; CHECK-GI-NEXT: orr w8, w8, w9
+; CHECK-GI-NEXT: fmov s0, w8
+; CHECK-GI-NEXT: ret
%or_result = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> %a)
%ins = insertelement <16 x i1> poison, i1 %or_result, i64 0
ret <16 x i1> %ins
@@ -202,349 +197,343 @@ define i8 @test_redor_v1i8(<1 x i8> %a) {
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w0, v0.b[0]
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_redor_v1i8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; GISEL-NEXT: umov w0, v0.b[0]
-; GISEL-NEXT: ret
%or_result = call i8 @llvm.vector.reduce.or.v1i8(<1 x i8> %a)
ret i8 %or_result
}
define i8 @test_redor_v3i8(<3 x i8> %a) {
-; CHECK-LABEL: test_redor_v3i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v0.2d, #0000000000000000
-; CHECK-NEXT: mov v0.h[0], w0
-; CHECK-NEXT: mov v0.h[1], w1
-; CHECK-NEXT: mov v0.h[2], w2
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: lsr x9, x8, #32
-; CHECK-NEXT: lsr x10, x8, #16
-; CHECK-NEXT: orr w8, w8, w9
-; CHECK-NEXT: orr w0, w8, w10
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redor_v3i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v0.2d, #0000000000000000
+; CHECK-SD-NEXT: mov v0.h[0], w0
+; CHECK-SD-NEXT: mov v0.h[1], w1
+; CHECK-SD-NEXT: mov v0.h[2], w2
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: lsr x9, x8, #32
+; CHECK-SD-NEXT: lsr x10, x8, #16
+; CHECK-SD-NEXT: orr w8, w8, w9
+; CHECK-SD-NEXT: orr w0, w8, w10
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redor_v3i8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: orr w8, w0, w1
-; GISEL-NEXT: orr w0, w8, w2
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redor_v3i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: orr w8, w0, w1
+; CHECK-GI-NEXT: orr w0, w8, w2
+; CHECK-GI-NEXT: ret
%or_result = call i8 @llvm.vector.reduce.or.v3i8(<3 x i8> %a)
ret i8 %or_result
}
define i8 @test_redor_v4i8(<4 x i8> %a) {
-; CHECK-LABEL: test_redor_v4i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: orr x8, x8, x8, lsr #32
-; CHECK-NEXT: lsr x9, x8, #16
-; CHECK-NEXT: orr w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redor_v4i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: orr x8, x8, x8, lsr #32
+; CHECK-SD-NEXT: lsr x9, x8, #16
+; CHECK-SD-NEXT: orr w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redor_v4i8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; GISEL-NEXT: umov w8, v0.h[0]
-; GISEL-NEXT: umov w9, v0.h[1]
-; GISEL-NEXT: umov w10, v0.h[2]
-; GISEL-NEXT: umov w11, v0.h[3]
-; GISEL-NEXT: orr w8, w8, w9
-; GISEL-NEXT: orr w9, w10, w11
-; GISEL-NEXT: orr w0, w8, w9
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redor_v4i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: umov w8, v0.h[0]
+; CHECK-GI-NEXT: umov w9, v0.h[1]
+; CHECK-GI-NEXT: umov w10, v0.h[2]
+; CHECK-GI-NEXT: umov w11, v0.h[3]
+; CHECK-GI-NEXT: orr w8, w8, w9
+; CHECK-GI-NEXT: orr w9, w10, w11
+; CHECK-GI-NEXT: orr w0, w8, w9
+; CHECK-GI-NEXT: ret
%or_result = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> %a)
ret i8 %or_result
}
define i8 @test_redor_v8i8(<8 x i8> %a) {
-; CHECK-LABEL: test_redor_v8i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: orr x8, x8, x8, lsr #32
-; CHECK-NEXT: orr x8, x8, x8, lsr #16
-; CHECK-NEXT: lsr x9, x8, #8
-; CHECK-NEXT: orr w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redor_v8i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: orr x8, x8, x8, lsr #32
+; CHECK-SD-NEXT: orr x8, x8, x8, lsr #16
+; CHECK-SD-NEXT: lsr x9, x8, #8
+; CHECK-SD-NEXT: orr w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redor_v8i8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; GISEL-NEXT: umov w8, v0.b[0]
-; GISEL-NEXT: umov w9, v0.b[1]
-; GISEL-NEXT: umov w10, v0.b[2]
-; GISEL-NEXT: umov w11, v0.b[3]
-; GISEL-NEXT: umov w12, v0.b[4]
-; GISEL-NEXT: umov w13, v0.b[5]
-; GISEL-NEXT: umov w14, v0.b[6]
-; GISEL-NEXT: umov w15, v0.b[7]
-; GISEL-NEXT: orr w8, w8, w9
-; GISEL-NEXT: orr w9, w10, w11
-; GISEL-NEXT: orr w10, w12, w13
-; GISEL-NEXT: orr w11, w14, w15
-; GISEL-NEXT: orr w8, w8, w9
-; GISEL-NEXT: orr w9, w10, w11
-; GISEL-NEXT: orr w0, w8, w9
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redor_v8i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: umov w8, v0.b[0]
+; CHECK-GI-NEXT: umov w9, v0.b[1]
+; CHECK-GI-NEXT: umov w10, v0.b[2]
+; CHECK-GI-NEXT: umov w11, v0.b[3]
+; CHECK-GI-NEXT: umov w12, v0.b[4]
+; CHECK-GI-NEXT: umov w13, v0.b[5]
+; CHECK-GI-NEXT: umov w14, v0.b[6]
+; CHECK-GI-NEXT: umov w15, v0.b[7]
+; CHECK-GI-NEXT: orr w8, w8, w9
+; CHECK-GI-NEXT: orr w9, w10, w11
+; CHECK-GI-NEXT: orr w10, w12, w13
+; CHECK-GI-NEXT: orr w11, w14, w15
+; CHECK-GI-NEXT: orr w8, w8, w9
+; CHECK-GI-NEXT: orr w9, w10, w11
+; CHECK-GI-NEXT: orr w0, w8, w9
+; CHECK-GI-NEXT: ret
%or_result = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> %a)
ret i8 %or_result
}
define i8 @test_redor_v16i8(<16 x i8> %a) {
-; CHECK-LABEL: test_redor_v16i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: orr x8, x8, x8, lsr #32
-; CHECK-NEXT: orr x8, x8, x8, lsr #16
-; CHECK-NEXT: lsr x9, x8, #8
-; CHECK-NEXT: orr w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redor_v16i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: orr x8, x8, x8, lsr #32
+; CHECK-SD-NEXT: orr x8, x8, x8, lsr #16
+; CHECK-SD-NEXT: lsr x9, x8, #8
+; CHECK-SD-NEXT: orr w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redor_v16i8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov d1, v0.d[1]
-; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b
-; GISEL-NEXT: umov w8, v0.b[0]
-; GISEL-NEXT: umov w9, v0.b[1]
-; GISEL-NEXT: umov w10, v0.b[2]
-; GISEL-NEXT: umov w11, v0.b[3]
-; GISEL-NEXT: umov w12, v0.b[4]
-; GISEL-NEXT: umov w13, v0.b[5]
-; GISEL-NEXT: umov w14, v0.b[6]
-; GISEL-NEXT: umov w15, v0.b[7]
-; GISEL-NEXT: orr w8, w8, w9
-; GISEL-NEXT: orr w9, w10, w11
-; GISEL-NEXT: orr w10, w12, w13
-; GISEL-NEXT: orr w11, w14, w15
-; GISEL-NEXT: orr w8, w8, w9
-; GISEL-NEXT: orr w9, w10, w11
-; GISEL-NEXT: orr w0, w8, w9
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redor_v16i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: umov w8, v0.b[0]
+; CHECK-GI-NEXT: umov w9, v0.b[1]
+; CHECK-GI-NEXT: umov w10, v0.b[2]
+; CHECK-GI-NEXT: umov w11, v0.b[3]
+; CHECK-GI-NEXT: umov w12, v0.b[4]
+; CHECK-GI-NEXT: umov w13, v0.b[5]
+; CHECK-GI-NEXT: umov w14, v0.b[6]
+; CHECK-GI-NEXT: umov w15, v0.b[7]
+; CHECK-GI-NEXT: orr w8, w8, w9
+; CHECK-GI-NEXT: orr w9, w10, w11
+; CHECK-GI-NEXT: orr w10, w12, w13
+; CHECK-GI-NEXT: orr w11, w14, w15
+; CHECK-GI-NEXT: orr w8, w8, w9
+; CHECK-GI-NEXT: orr w9, w10, w11
+; CHECK-GI-NEXT: orr w0, w8, w9
+; CHECK-GI-NEXT: ret
%or_result = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> %a)
ret i8 %or_result
}
define i8 @test_redor_v32i8(<32 x i8> %a) {
-; CHECK-LABEL: test_redor_v32i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: orr x8, x8, x8, lsr #32
-; CHECK-NEXT: orr x8, x8, x8, lsr #16
-; CHECK-NEXT: lsr x9, x8, #8
-; CHECK-NEXT: orr w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redor_v32i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: orr x8, x8, x8, lsr #32
+; CHECK-SD-NEXT: orr x8, x8, x8, lsr #16
+; CHECK-SD-NEXT: lsr x9, x8, #8
+; CHECK-SD-NEXT: orr w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redor_v32i8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: orr v0.16b, v0.16b, v1.16b
-; GISEL-NEXT: mov d1, v0.d[1]
-; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b
-; GISEL-NEXT: umov w8, v0.b[0]
-; GISEL-NEXT: umov w9, v0.b[1]
-; GISEL-NEXT: umov w10, v0.b[2]
-; GISEL-NEXT: umov w11, v0.b[3]
-; GISEL-NEXT: umov w12, v0.b[4]
-; GISEL-NEXT: umov w13, v0.b[5]
-; GISEL-NEXT: umov w14, v0.b[6]
-; GISEL-NEXT: umov w15, v0.b[7]
-; GISEL-NEXT: orr w8, w8, w9
-; GISEL-NEXT: orr w9, w10, w11
-; GISEL-NEXT: orr w10, w12, w13
-; GISEL-NEXT: orr w11, w14, w15
-; GISEL-NEXT: orr w8, w8, w9
-; GISEL-NEXT: orr w9, w10, w11
-; GISEL-NEXT: orr w0, w8, w9
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redor_v32i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: umov w8, v0.b[0]
+; CHECK-GI-NEXT: umov w9, v0.b[1]
+; CHECK-GI-NEXT: umov w10, v0.b[2]
+; CHECK-GI-NEXT: umov w11, v0.b[3]
+; CHECK-GI-NEXT: umov w12, v0.b[4]
+; CHECK-GI-NEXT: umov w13, v0.b[5]
+; CHECK-GI-NEXT: umov w14, v0.b[6]
+; CHECK-GI-NEXT: umov w15, v0.b[7]
+; CHECK-GI-NEXT: orr w8, w8, w9
+; CHECK-GI-NEXT: orr w9, w10, w11
+; CHECK-GI-NEXT: orr w10, w12, w13
+; CHECK-GI-NEXT: orr w11, w14, w15
+; CHECK-GI-NEXT: orr w8, w8, w9
+; CHECK-GI-NEXT: orr w9, w10, w11
+; CHECK-GI-NEXT: orr w0, w8, w9
+; CHECK-GI-NEXT: ret
%or_result = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> %a)
ret i8 %or_result
}
define i16 @test_redor_v4i16(<4 x i16> %a) {
-; CHECK-LABEL: test_redor_v4i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: orr x8, x8, x8, lsr #32
-; CHECK-NEXT: lsr x9, x8, #16
-; CHECK-NEXT: orr w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redor_v4i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: orr x8, x8, x8, lsr #32
+; CHECK-SD-NEXT: lsr x9, x8, #16
+; CHECK-SD-NEXT: orr w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redor_v4i16:
-; GISEL: // %bb.0:
-; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; GISEL-NEXT: umov w8, v0.h[0]
-; GISEL-NEXT: umov w9, v0.h[1]
-; GISEL-NEXT: umov w10, v0.h[2]
-; GISEL-NEXT: umov w11, v0.h[3]
-; GISEL-NEXT: orr w8, w8, w9
-; GISEL-NEXT: orr w9, w10, w11
-; GISEL-NEXT: orr w0, w8, w9
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redor_v4i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: umov w8, v0.h[0]
+; CHECK-GI-NEXT: umov w9, v0.h[1]
+; CHECK-GI-NEXT: umov w10, v0.h[2]
+; CHECK-GI-NEXT: umov w11, v0.h[3]
+; CHECK-GI-NEXT: orr w8, w8, w9
+; CHECK-GI-NEXT: orr w9, w10, w11
+; CHECK-GI-NEXT: orr w0, w8, w9
+; CHECK-GI-NEXT: ret
%or_result = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> %a)
ret i16 %or_result
}
define i16 @test_redor_v8i16(<8 x i16> %a) {
-; CHECK-LABEL: test_redor_v8i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: orr x8, x8, x8, lsr #32
-; CHECK-NEXT: lsr x9, x8, #16
-; CHECK-NEXT: orr w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redor_v8i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: orr x8, x8, x8, lsr #32
+; CHECK-SD-NEXT: lsr x9, x8, #16
+; CHECK-SD-NEXT: orr w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redor_v8i16:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov d1, v0.d[1]
-; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b
-; GISEL-NEXT: umov w8, v0.h[0]
-; GISEL-NEXT: umov w9, v0.h[1]
-; GISEL-NEXT: umov w10, v0.h[2]
-; GISEL-NEXT: umov w11, v0.h[3]
-; GISEL-NEXT: orr w8, w8, w9
-; GISEL-NEXT: orr w9, w10, w11
-; GISEL-NEXT: orr w0, w8, w9
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redor_v8i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: umov w8, v0.h[0]
+; CHECK-GI-NEXT: umov w9, v0.h[1]
+; CHECK-GI-NEXT: umov w10, v0.h[2]
+; CHECK-GI-NEXT: umov w11, v0.h[3]
+; CHECK-GI-NEXT: orr w8, w8, w9
+; CHECK-GI-NEXT: orr w9, w10, w11
+; CHECK-GI-NEXT: orr w0, w8, w9
+; CHECK-GI-NEXT: ret
%or_result = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> %a)
ret i16 %or_result
}
define i16 @test_redor_v16i16(<16 x i16> %a) {
-; CHECK-LABEL: test_redor_v16i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: orr x8, x8, x8, lsr #32
-; CHECK-NEXT: lsr x9, x8, #16
-; CHECK-NEXT: orr w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redor_v16i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: orr x8, x8, x8, lsr #32
+; CHECK-SD-NEXT: lsr x9, x8, #16
+; CHECK-SD-NEXT: orr w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redor_v16i16:
-; GISEL: // %bb.0:
-; GISEL-NEXT: orr v0.16b, v0.16b, v1.16b
-; GISEL-NEXT: mov d1, v0.d[1]
-; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b
-; GISEL-NEXT: umov w8, v0.h[0]
-; GISEL-NEXT: umov w9, v0.h[1]
-; GISEL-NEXT: umov w10, v0.h[2]
-; GISEL-NEXT: umov w11, v0.h[3]
-; GISEL-NEXT: orr w8, w8, w9
-; GISEL-NEXT: orr w9, w10, w11
-; GISEL-NEXT: orr w0, w8, w9
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redor_v16i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: umov w8, v0.h[0]
+; CHECK-GI-NEXT: umov w9, v0.h[1]
+; CHECK-GI-NEXT: umov w10, v0.h[2]
+; CHECK-GI-NEXT: umov w11, v0.h[3]
+; CHECK-GI-NEXT: orr w8, w8, w9
+; CHECK-GI-NEXT: orr w9, w10, w11
+; CHECK-GI-NEXT: orr w0, w8, w9
+; CHECK-GI-NEXT: ret
%or_result = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %a)
ret i16 %or_result
}
define i32 @test_redor_v2i32(<2 x i32> %a) {
-; CHECK-LABEL: test_redor_v2i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: lsr x9, x8, #32
-; CHECK-NEXT: orr w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redor_v2i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: lsr x9, x8, #32
+; CHECK-SD-NEXT: orr w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redor_v2i32:
-; GISEL: // %bb.0:
-; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; GISEL-NEXT: mov w8, v0.s[1]
-; GISEL-NEXT: fmov w9, s0
-; GISEL-NEXT: orr w0, w9, w8
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redor_v2i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: mov w8, v0.s[1]
+; CHECK-GI-NEXT: fmov w9, s0
+; CHECK-GI-NEXT: orr w0, w9, w8
+; CHECK-GI-NEXT: ret
%or_result = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> %a)
ret i32 %or_result
}
define i32 @test_redor_v4i32(<4 x i32> %a) {
-; CHECK-LABEL: test_redor_v4i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: lsr x9, x8, #32
-; CHECK-NEXT: orr w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redor_v4i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: lsr x9, x8, #32
+; CHECK-SD-NEXT: orr w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redor_v4i32:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov d1, v0.d[1]
-; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b
-; GISEL-NEXT: mov w8, v0.s[1]
-; GISEL-NEXT: fmov w9, s0
-; GISEL-NEXT: orr w0, w9, w8
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redor_v4i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: mov w8, v0.s[1]
+; CHECK-GI-NEXT: fmov w9, s0
+; CHECK-GI-NEXT: orr w0, w9, w8
+; CHECK-GI-NEXT: ret
%or_result = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %a)
ret i32 %or_result
}
define i32 @test_redor_v8i32(<8 x i32> %a) {
-; CHECK-LABEL: test_redor_v8i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: lsr x9, x8, #32
-; CHECK-NEXT: orr w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redor_v8i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: lsr x9, x8, #32
+; CHECK-SD-NEXT: orr w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redor_v8i32:
-; GISEL: // %bb.0:
-; GISEL-NEXT: orr v0.16b, v0.16b, v1.16b
-; GISEL-NEXT: mov d1, v0.d[1]
-; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b
-; GISEL-NEXT: mov w8, v0.s[1]
-; GISEL-NEXT: fmov w9, s0
-; GISEL-NEXT: orr w0, w9, w8
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redor_v8i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: mov w8, v0.s[1]
+; CHECK-GI-NEXT: fmov w9, s0
+; CHECK-GI-NEXT: orr w0, w9, w8
+; CHECK-GI-NEXT: ret
%or_result = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %a)
ret i32 %or_result
}
define i64 @test_redor_v2i64(<2 x i64> %a) {
-; CHECK-LABEL: test_redor_v2i64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redor_v2i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redor_v2i64:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov x8, v0.d[1]
-; GISEL-NEXT: fmov x9, d0
-; GISEL-NEXT: orr x0, x9, x8
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redor_v2i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: fmov x9, d0
+; CHECK-GI-NEXT: orr x0, x9, x8
+; CHECK-GI-NEXT: ret
%or_result = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %a)
ret i64 %or_result
}
define i64 @test_redor_v4i64(<4 x i64> %a) {
-; CHECK-LABEL: test_redor_v4i64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redor_v4i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redor_v4i64:
-; GISEL: // %bb.0:
-; GISEL-NEXT: orr v0.16b, v0.16b, v1.16b
-; GISEL-NEXT: mov x8, v0.d[1]
-; GISEL-NEXT: fmov x9, d0
-; GISEL-NEXT: orr x0, x9, x8
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redor_v4i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: fmov x9, d0
+; CHECK-GI-NEXT: orr x0, x9, x8
+; CHECK-GI-NEXT: ret
%or_result = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %a)
ret i64 %or_result
}
diff --git a/llvm/test/CodeGen/AArch64/reduce-xor.ll b/llvm/test/CodeGen/AArch64/reduce-xor.ll
index df8485b91468f..50cc845f2756b 100644
--- a/llvm/test/CodeGen/AArch64/reduce-xor.ll
+++ b/llvm/test/CodeGen/AArch64/reduce-xor.ll
@@ -1,185 +1,180 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -mattr=+neon | FileCheck %s
-; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=1 | FileCheck %s --check-prefix=GISEL
+; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define i1 @test_redxor_v1i1(<1 x i1> %a) {
; CHECK-LABEL: test_redxor_v1i1:
; CHECK: // %bb.0:
; CHECK-NEXT: and w0, w0, #0x1
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_redxor_v1i1:
-; GISEL: // %bb.0:
-; GISEL-NEXT: and w0, w0, #0x1
-; GISEL-NEXT: ret
%or_result = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> %a)
ret i1 %or_result
}
define i1 @test_redxor_v2i1(<2 x i1> %a) {
-; CHECK-LABEL: test_redxor_v2i1:
-; CHECK: // %bb.0:
-; CHECK-NEXT: addp v0.2s, v0.2s, v0.2s
-; CHECK-NEXT: fmov w8, s0
-; CHECK-NEXT: and w0, w8, #0x1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redxor_v2i1:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: addp v0.2s, v0.2s, v0.2s
+; CHECK-SD-NEXT: fmov w8, s0
+; CHECK-SD-NEXT: and w0, w8, #0x1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redxor_v2i1:
-; GISEL: // %bb.0:
-; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; GISEL-NEXT: mov w8, v0.s[1]
-; GISEL-NEXT: fmov w9, s0
-; GISEL-NEXT: eor w8, w9, w8
-; GISEL-NEXT: and w0, w8, #0x1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redxor_v2i1:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: mov w8, v0.s[1]
+; CHECK-GI-NEXT: fmov w9, s0
+; CHECK-GI-NEXT: eor w8, w9, w8
+; CHECK-GI-NEXT: and w0, w8, #0x1
+; CHECK-GI-NEXT: ret
%or_result = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> %a)
ret i1 %or_result
}
define i1 @test_redxor_v4i1(<4 x i1> %a) {
-; CHECK-LABEL: test_redxor_v4i1:
-; CHECK: // %bb.0:
-; CHECK-NEXT: addv h0, v0.4h
-; CHECK-NEXT: fmov w8, s0
-; CHECK-NEXT: and w0, w8, #0x1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redxor_v4i1:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: addv h0, v0.4h
+; CHECK-SD-NEXT: fmov w8, s0
+; CHECK-SD-NEXT: and w0, w8, #0x1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redxor_v4i1:
-; GISEL: // %bb.0:
-; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; GISEL-NEXT: umov w8, v0.h[0]
-; GISEL-NEXT: umov w9, v0.h[1]
-; GISEL-NEXT: umov w10, v0.h[2]
-; GISEL-NEXT: umov w11, v0.h[3]
-; GISEL-NEXT: eor w8, w8, w9
-; GISEL-NEXT: eor w9, w10, w11
-; GISEL-NEXT: eor w8, w8, w9
-; GISEL-NEXT: and w0, w8, #0x1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redxor_v4i1:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: umov w8, v0.h[0]
+; CHECK-GI-NEXT: umov w9, v0.h[1]
+; CHECK-GI-NEXT: umov w10, v0.h[2]
+; CHECK-GI-NEXT: umov w11, v0.h[3]
+; CHECK-GI-NEXT: eor w8, w8, w9
+; CHECK-GI-NEXT: eor w9, w10, w11
+; CHECK-GI-NEXT: eor w8, w8, w9
+; CHECK-GI-NEXT: and w0, w8, #0x1
+; CHECK-GI-NEXT: ret
%or_result = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> %a)
ret i1 %or_result
}
define i1 @test_redxor_v8i1(<8 x i1> %a) {
-; CHECK-LABEL: test_redxor_v8i1:
-; CHECK: // %bb.0:
-; CHECK-NEXT: addv b0, v0.8b
-; CHECK-NEXT: fmov w8, s0
-; CHECK-NEXT: and w0, w8, #0x1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redxor_v8i1:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: addv b0, v0.8b
+; CHECK-SD-NEXT: fmov w8, s0
+; CHECK-SD-NEXT: and w0, w8, #0x1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redxor_v8i1:
-; GISEL: // %bb.0:
-; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; GISEL-NEXT: umov w8, v0.b[0]
-; GISEL-NEXT: umov w9, v0.b[1]
-; GISEL-NEXT: umov w10, v0.b[2]
-; GISEL-NEXT: umov w11, v0.b[3]
-; GISEL-NEXT: umov w12, v0.b[4]
-; GISEL-NEXT: umov w13, v0.b[5]
-; GISEL-NEXT: umov w14, v0.b[6]
-; GISEL-NEXT: umov w15, v0.b[7]
-; GISEL-NEXT: eor w8, w8, w9
-; GISEL-NEXT: eor w9, w10, w11
-; GISEL-NEXT: eor w10, w12, w13
-; GISEL-NEXT: eor w11, w14, w15
-; GISEL-NEXT: eor w8, w8, w9
-; GISEL-NEXT: eor w9, w10, w11
-; GISEL-NEXT: eor w8, w8, w9
-; GISEL-NEXT: and w0, w8, #0x1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redxor_v8i1:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: umov w8, v0.b[0]
+; CHECK-GI-NEXT: umov w9, v0.b[1]
+; CHECK-GI-NEXT: umov w10, v0.b[2]
+; CHECK-GI-NEXT: umov w11, v0.b[3]
+; CHECK-GI-NEXT: umov w12, v0.b[4]
+; CHECK-GI-NEXT: umov w13, v0.b[5]
+; CHECK-GI-NEXT: umov w14, v0.b[6]
+; CHECK-GI-NEXT: umov w15, v0.b[7]
+; CHECK-GI-NEXT: eor w8, w8, w9
+; CHECK-GI-NEXT: eor w9, w10, w11
+; CHECK-GI-NEXT: eor w10, w12, w13
+; CHECK-GI-NEXT: eor w11, w14, w15
+; CHECK-GI-NEXT: eor w8, w8, w9
+; CHECK-GI-NEXT: eor w9, w10, w11
+; CHECK-GI-NEXT: eor w8, w8, w9
+; CHECK-GI-NEXT: and w0, w8, #0x1
+; CHECK-GI-NEXT: ret
%or_result = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> %a)
ret i1 %or_result
}
define i1 @test_redxor_v16i1(<16 x i1> %a) {
-; CHECK-LABEL: test_redxor_v16i1:
-; CHECK: // %bb.0:
-; CHECK-NEXT: addv b0, v0.16b
-; CHECK-NEXT: fmov w8, s0
-; CHECK-NEXT: and w0, w8, #0x1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redxor_v16i1:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: addv b0, v0.16b
+; CHECK-SD-NEXT: fmov w8, s0
+; CHECK-SD-NEXT: and w0, w8, #0x1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redxor_v16i1:
-; GISEL: // %bb.0:
-; GISEL-NEXT: umov w8, v0.b[0]
-; GISEL-NEXT: umov w9, v0.b[1]
-; GISEL-NEXT: umov w10, v0.b[2]
-; GISEL-NEXT: umov w11, v0.b[3]
-; GISEL-NEXT: umov w12, v0.b[4]
-; GISEL-NEXT: umov w13, v0.b[5]
-; GISEL-NEXT: umov w14, v0.b[6]
-; GISEL-NEXT: umov w15, v0.b[7]
-; GISEL-NEXT: umov w16, v0.b[8]
-; GISEL-NEXT: umov w17, v0.b[9]
-; GISEL-NEXT: umov w18, v0.b[10]
-; GISEL-NEXT: umov w0, v0.b[11]
-; GISEL-NEXT: eor w8, w8, w9
-; GISEL-NEXT: umov w1, v0.b[12]
-; GISEL-NEXT: umov w2, v0.b[13]
-; GISEL-NEXT: eor w9, w10, w11
-; GISEL-NEXT: eor w10, w12, w13
-; GISEL-NEXT: umov w3, v0.b[14]
-; GISEL-NEXT: eor w11, w14, w15
-; GISEL-NEXT: eor w8, w8, w9
-; GISEL-NEXT: umov w4, v0.b[15]
-; GISEL-NEXT: eor w12, w16, w17
-; GISEL-NEXT: eor w13, w18, w0
-; GISEL-NEXT: eor w9, w10, w11
-; GISEL-NEXT: eor w14, w1, w2
-; GISEL-NEXT: eor w10, w12, w13
-; GISEL-NEXT: eor w8, w8, w9
-; GISEL-NEXT: eor w15, w3, w4
-; GISEL-NEXT: eor w11, w14, w15
-; GISEL-NEXT: eor w9, w10, w11
-; GISEL-NEXT: eor w8, w8, w9
-; GISEL-NEXT: and w0, w8, #0x1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redxor_v16i1:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: umov w8, v0.b[0]
+; CHECK-GI-NEXT: umov w9, v0.b[1]
+; CHECK-GI-NEXT: umov w10, v0.b[2]
+; CHECK-GI-NEXT: umov w11, v0.b[3]
+; CHECK-GI-NEXT: umov w12, v0.b[4]
+; CHECK-GI-NEXT: umov w13, v0.b[5]
+; CHECK-GI-NEXT: umov w14, v0.b[6]
+; CHECK-GI-NEXT: umov w15, v0.b[7]
+; CHECK-GI-NEXT: umov w16, v0.b[8]
+; CHECK-GI-NEXT: umov w17, v0.b[9]
+; CHECK-GI-NEXT: umov w18, v0.b[10]
+; CHECK-GI-NEXT: umov w0, v0.b[11]
+; CHECK-GI-NEXT: eor w8, w8, w9
+; CHECK-GI-NEXT: umov w1, v0.b[12]
+; CHECK-GI-NEXT: umov w2, v0.b[13]
+; CHECK-GI-NEXT: eor w9, w10, w11
+; CHECK-GI-NEXT: eor w10, w12, w13
+; CHECK-GI-NEXT: umov w3, v0.b[14]
+; CHECK-GI-NEXT: eor w11, w14, w15
+; CHECK-GI-NEXT: eor w8, w8, w9
+; CHECK-GI-NEXT: umov w4, v0.b[15]
+; CHECK-GI-NEXT: eor w12, w16, w17
+; CHECK-GI-NEXT: eor w13, w18, w0
+; CHECK-GI-NEXT: eor w9, w10, w11
+; CHECK-GI-NEXT: eor w14, w1, w2
+; CHECK-GI-NEXT: eor w10, w12, w13
+; CHECK-GI-NEXT: eor w8, w8, w9
+; CHECK-GI-NEXT: eor w15, w3, w4
+; CHECK-GI-NEXT: eor w11, w14, w15
+; CHECK-GI-NEXT: eor w9, w10, w11
+; CHECK-GI-NEXT: eor w8, w8, w9
+; CHECK-GI-NEXT: and w0, w8, #0x1
+; CHECK-GI-NEXT: ret
%or_result = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> %a)
ret i1 %or_result
}
define <16 x i1> @test_redxor_ins_v16i1(<16 x i1> %a) {
-; CHECK-LABEL: test_redxor_ins_v16i1:
-; CHECK: // %bb.0:
-; CHECK-NEXT: addv b0, v0.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redxor_ins_v16i1:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: addv b0, v0.16b
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redxor_ins_v16i1:
-; GISEL: // %bb.0:
-; GISEL-NEXT: umov w8, v0.b[0]
-; GISEL-NEXT: umov w9, v0.b[1]
-; GISEL-NEXT: umov w10, v0.b[2]
-; GISEL-NEXT: umov w11, v0.b[3]
-; GISEL-NEXT: umov w12, v0.b[4]
-; GISEL-NEXT: umov w13, v0.b[5]
-; GISEL-NEXT: umov w14, v0.b[6]
-; GISEL-NEXT: umov w15, v0.b[7]
-; GISEL-NEXT: umov w16, v0.b[8]
-; GISEL-NEXT: umov w17, v0.b[9]
-; GISEL-NEXT: umov w18, v0.b[10]
-; GISEL-NEXT: umov w0, v0.b[11]
-; GISEL-NEXT: eor w8, w8, w9
-; GISEL-NEXT: umov w1, v0.b[12]
-; GISEL-NEXT: umov w2, v0.b[13]
-; GISEL-NEXT: eor w9, w10, w11
-; GISEL-NEXT: eor w10, w12, w13
-; GISEL-NEXT: umov w3, v0.b[14]
-; GISEL-NEXT: eor w11, w14, w15
-; GISEL-NEXT: eor w8, w8, w9
-; GISEL-NEXT: umov w4, v0.b[15]
-; GISEL-NEXT: eor w12, w16, w17
-; GISEL-NEXT: eor w13, w18, w0
-; GISEL-NEXT: eor w9, w10, w11
-; GISEL-NEXT: eor w14, w1, w2
-; GISEL-NEXT: eor w10, w12, w13
-; GISEL-NEXT: eor w8, w8, w9
-; GISEL-NEXT: eor w15, w3, w4
-; GISEL-NEXT: eor w11, w14, w15
-; GISEL-NEXT: eor w9, w10, w11
-; GISEL-NEXT: eor w8, w8, w9
-; GISEL-NEXT: fmov s0, w8
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redxor_ins_v16i1:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: umov w8, v0.b[0]
+; CHECK-GI-NEXT: umov w9, v0.b[1]
+; CHECK-GI-NEXT: umov w10, v0.b[2]
+; CHECK-GI-NEXT: umov w11, v0.b[3]
+; CHECK-GI-NEXT: umov w12, v0.b[4]
+; CHECK-GI-NEXT: umov w13, v0.b[5]
+; CHECK-GI-NEXT: umov w14, v0.b[6]
+; CHECK-GI-NEXT: umov w15, v0.b[7]
+; CHECK-GI-NEXT: umov w16, v0.b[8]
+; CHECK-GI-NEXT: umov w17, v0.b[9]
+; CHECK-GI-NEXT: umov w18, v0.b[10]
+; CHECK-GI-NEXT: umov w0, v0.b[11]
+; CHECK-GI-NEXT: eor w8, w8, w9
+; CHECK-GI-NEXT: umov w1, v0.b[12]
+; CHECK-GI-NEXT: umov w2, v0.b[13]
+; CHECK-GI-NEXT: eor w9, w10, w11
+; CHECK-GI-NEXT: eor w10, w12, w13
+; CHECK-GI-NEXT: umov w3, v0.b[14]
+; CHECK-GI-NEXT: eor w11, w14, w15
+; CHECK-GI-NEXT: eor w8, w8, w9
+; CHECK-GI-NEXT: umov w4, v0.b[15]
+; CHECK-GI-NEXT: eor w12, w16, w17
+; CHECK-GI-NEXT: eor w13, w18, w0
+; CHECK-GI-NEXT: eor w9, w10, w11
+; CHECK-GI-NEXT: eor w14, w1, w2
+; CHECK-GI-NEXT: eor w10, w12, w13
+; CHECK-GI-NEXT: eor w8, w8, w9
+; CHECK-GI-NEXT: eor w15, w3, w4
+; CHECK-GI-NEXT: eor w11, w14, w15
+; CHECK-GI-NEXT: eor w9, w10, w11
+; CHECK-GI-NEXT: eor w8, w8, w9
+; CHECK-GI-NEXT: fmov s0, w8
+; CHECK-GI-NEXT: ret
%xor_result = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> %a)
%ins = insertelement <16 x i1> poison, i1 %xor_result, i64 0
ret <16 x i1> %ins
@@ -191,349 +186,343 @@ define i8 @test_redxor_v1i8(<1 x i8> %a) {
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w0, v0.b[0]
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_redxor_v1i8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; GISEL-NEXT: umov w0, v0.b[0]
-; GISEL-NEXT: ret
%xor_result = call i8 @llvm.vector.reduce.xor.v1i8(<1 x i8> %a)
ret i8 %xor_result
}
define i8 @test_redxor_v3i8(<3 x i8> %a) {
-; CHECK-LABEL: test_redxor_v3i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v0.2d, #0000000000000000
-; CHECK-NEXT: mov v0.h[0], w0
-; CHECK-NEXT: mov v0.h[1], w1
-; CHECK-NEXT: mov v0.h[2], w2
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: lsr x9, x8, #32
-; CHECK-NEXT: lsr x10, x8, #16
-; CHECK-NEXT: eor w8, w8, w9
-; CHECK-NEXT: eor w0, w8, w10
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redxor_v3i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v0.2d, #0000000000000000
+; CHECK-SD-NEXT: mov v0.h[0], w0
+; CHECK-SD-NEXT: mov v0.h[1], w1
+; CHECK-SD-NEXT: mov v0.h[2], w2
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: lsr x9, x8, #32
+; CHECK-SD-NEXT: lsr x10, x8, #16
+; CHECK-SD-NEXT: eor w8, w8, w9
+; CHECK-SD-NEXT: eor w0, w8, w10
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redxor_v3i8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: eor w8, w0, w1
-; GISEL-NEXT: eor w0, w8, w2
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redxor_v3i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: eor w8, w0, w1
+; CHECK-GI-NEXT: eor w0, w8, w2
+; CHECK-GI-NEXT: ret
%xor_result = call i8 @llvm.vector.reduce.xor.v3i8(<3 x i8> %a)
ret i8 %xor_result
}
define i8 @test_redxor_v4i8(<4 x i8> %a) {
-; CHECK-LABEL: test_redxor_v4i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: eor x8, x8, x8, lsr #32
-; CHECK-NEXT: lsr x9, x8, #16
-; CHECK-NEXT: eor w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redxor_v4i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: eor x8, x8, x8, lsr #32
+; CHECK-SD-NEXT: lsr x9, x8, #16
+; CHECK-SD-NEXT: eor w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redxor_v4i8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; GISEL-NEXT: umov w8, v0.h[0]
-; GISEL-NEXT: umov w9, v0.h[1]
-; GISEL-NEXT: umov w10, v0.h[2]
-; GISEL-NEXT: umov w11, v0.h[3]
-; GISEL-NEXT: eor w8, w8, w9
-; GISEL-NEXT: eor w9, w10, w11
-; GISEL-NEXT: eor w0, w8, w9
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redxor_v4i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: umov w8, v0.h[0]
+; CHECK-GI-NEXT: umov w9, v0.h[1]
+; CHECK-GI-NEXT: umov w10, v0.h[2]
+; CHECK-GI-NEXT: umov w11, v0.h[3]
+; CHECK-GI-NEXT: eor w8, w8, w9
+; CHECK-GI-NEXT: eor w9, w10, w11
+; CHECK-GI-NEXT: eor w0, w8, w9
+; CHECK-GI-NEXT: ret
%xor_result = call i8 @llvm.vector.reduce.xor.v4i8(<4 x i8> %a)
ret i8 %xor_result
}
define i8 @test_redxor_v8i8(<8 x i8> %a) {
-; CHECK-LABEL: test_redxor_v8i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: eor x8, x8, x8, lsr #32
-; CHECK-NEXT: eor x8, x8, x8, lsr #16
-; CHECK-NEXT: lsr x9, x8, #8
-; CHECK-NEXT: eor w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redxor_v8i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: eor x8, x8, x8, lsr #32
+; CHECK-SD-NEXT: eor x8, x8, x8, lsr #16
+; CHECK-SD-NEXT: lsr x9, x8, #8
+; CHECK-SD-NEXT: eor w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redxor_v8i8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; GISEL-NEXT: umov w8, v0.b[0]
-; GISEL-NEXT: umov w9, v0.b[1]
-; GISEL-NEXT: umov w10, v0.b[2]
-; GISEL-NEXT: umov w11, v0.b[3]
-; GISEL-NEXT: umov w12, v0.b[4]
-; GISEL-NEXT: umov w13, v0.b[5]
-; GISEL-NEXT: umov w14, v0.b[6]
-; GISEL-NEXT: umov w15, v0.b[7]
-; GISEL-NEXT: eor w8, w8, w9
-; GISEL-NEXT: eor w9, w10, w11
-; GISEL-NEXT: eor w10, w12, w13
-; GISEL-NEXT: eor w11, w14, w15
-; GISEL-NEXT: eor w8, w8, w9
-; GISEL-NEXT: eor w9, w10, w11
-; GISEL-NEXT: eor w0, w8, w9
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redxor_v8i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: umov w8, v0.b[0]
+; CHECK-GI-NEXT: umov w9, v0.b[1]
+; CHECK-GI-NEXT: umov w10, v0.b[2]
+; CHECK-GI-NEXT: umov w11, v0.b[3]
+; CHECK-GI-NEXT: umov w12, v0.b[4]
+; CHECK-GI-NEXT: umov w13, v0.b[5]
+; CHECK-GI-NEXT: umov w14, v0.b[6]
+; CHECK-GI-NEXT: umov w15, v0.b[7]
+; CHECK-GI-NEXT: eor w8, w8, w9
+; CHECK-GI-NEXT: eor w9, w10, w11
+; CHECK-GI-NEXT: eor w10, w12, w13
+; CHECK-GI-NEXT: eor w11, w14, w15
+; CHECK-GI-NEXT: eor w8, w8, w9
+; CHECK-GI-NEXT: eor w9, w10, w11
+; CHECK-GI-NEXT: eor w0, w8, w9
+; CHECK-GI-NEXT: ret
%xor_result = call i8 @llvm.vector.reduce.xor.v8i8(<8 x i8> %a)
ret i8 %xor_result
}
define i8 @test_redxor_v16i8(<16 x i8> %a) {
-; CHECK-LABEL: test_redxor_v16i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: eor x8, x8, x8, lsr #32
-; CHECK-NEXT: eor x8, x8, x8, lsr #16
-; CHECK-NEXT: lsr x9, x8, #8
-; CHECK-NEXT: eor w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redxor_v16i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: eor x8, x8, x8, lsr #32
+; CHECK-SD-NEXT: eor x8, x8, x8, lsr #16
+; CHECK-SD-NEXT: lsr x9, x8, #8
+; CHECK-SD-NEXT: eor w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redxor_v16i8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov d1, v0.d[1]
-; GISEL-NEXT: eor v0.8b, v0.8b, v1.8b
-; GISEL-NEXT: umov w8, v0.b[0]
-; GISEL-NEXT: umov w9, v0.b[1]
-; GISEL-NEXT: umov w10, v0.b[2]
-; GISEL-NEXT: umov w11, v0.b[3]
-; GISEL-NEXT: umov w12, v0.b[4]
-; GISEL-NEXT: umov w13, v0.b[5]
-; GISEL-NEXT: umov w14, v0.b[6]
-; GISEL-NEXT: umov w15, v0.b[7]
-; GISEL-NEXT: eor w8, w8, w9
-; GISEL-NEXT: eor w9, w10, w11
-; GISEL-NEXT: eor w10, w12, w13
-; GISEL-NEXT: eor w11, w14, w15
-; GISEL-NEXT: eor w8, w8, w9
-; GISEL-NEXT: eor w9, w10, w11
-; GISEL-NEXT: eor w0, w8, w9
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redxor_v16i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: umov w8, v0.b[0]
+; CHECK-GI-NEXT: umov w9, v0.b[1]
+; CHECK-GI-NEXT: umov w10, v0.b[2]
+; CHECK-GI-NEXT: umov w11, v0.b[3]
+; CHECK-GI-NEXT: umov w12, v0.b[4]
+; CHECK-GI-NEXT: umov w13, v0.b[5]
+; CHECK-GI-NEXT: umov w14, v0.b[6]
+; CHECK-GI-NEXT: umov w15, v0.b[7]
+; CHECK-GI-NEXT: eor w8, w8, w9
+; CHECK-GI-NEXT: eor w9, w10, w11
+; CHECK-GI-NEXT: eor w10, w12, w13
+; CHECK-GI-NEXT: eor w11, w14, w15
+; CHECK-GI-NEXT: eor w8, w8, w9
+; CHECK-GI-NEXT: eor w9, w10, w11
+; CHECK-GI-NEXT: eor w0, w8, w9
+; CHECK-GI-NEXT: ret
%xor_result = call i8 @llvm.vector.reduce.xor.v16i8(<16 x i8> %a)
ret i8 %xor_result
}
define i8 @test_redxor_v32i8(<32 x i8> %a) {
-; CHECK-LABEL: test_redxor_v32i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: eor x8, x8, x8, lsr #32
-; CHECK-NEXT: eor x8, x8, x8, lsr #16
-; CHECK-NEXT: lsr x9, x8, #8
-; CHECK-NEXT: eor w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redxor_v32i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: eor v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: eor x8, x8, x8, lsr #32
+; CHECK-SD-NEXT: eor x8, x8, x8, lsr #16
+; CHECK-SD-NEXT: lsr x9, x8, #8
+; CHECK-SD-NEXT: eor w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redxor_v32i8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: eor v0.16b, v0.16b, v1.16b
-; GISEL-NEXT: mov d1, v0.d[1]
-; GISEL-NEXT: eor v0.8b, v0.8b, v1.8b
-; GISEL-NEXT: umov w8, v0.b[0]
-; GISEL-NEXT: umov w9, v0.b[1]
-; GISEL-NEXT: umov w10, v0.b[2]
-; GISEL-NEXT: umov w11, v0.b[3]
-; GISEL-NEXT: umov w12, v0.b[4]
-; GISEL-NEXT: umov w13, v0.b[5]
-; GISEL-NEXT: umov w14, v0.b[6]
-; GISEL-NEXT: umov w15, v0.b[7]
-; GISEL-NEXT: eor w8, w8, w9
-; GISEL-NEXT: eor w9, w10, w11
-; GISEL-NEXT: eor w10, w12, w13
-; GISEL-NEXT: eor w11, w14, w15
-; GISEL-NEXT: eor w8, w8, w9
-; GISEL-NEXT: eor w9, w10, w11
-; GISEL-NEXT: eor w0, w8, w9
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redxor_v32i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: eor v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: umov w8, v0.b[0]
+; CHECK-GI-NEXT: umov w9, v0.b[1]
+; CHECK-GI-NEXT: umov w10, v0.b[2]
+; CHECK-GI-NEXT: umov w11, v0.b[3]
+; CHECK-GI-NEXT: umov w12, v0.b[4]
+; CHECK-GI-NEXT: umov w13, v0.b[5]
+; CHECK-GI-NEXT: umov w14, v0.b[6]
+; CHECK-GI-NEXT: umov w15, v0.b[7]
+; CHECK-GI-NEXT: eor w8, w8, w9
+; CHECK-GI-NEXT: eor w9, w10, w11
+; CHECK-GI-NEXT: eor w10, w12, w13
+; CHECK-GI-NEXT: eor w11, w14, w15
+; CHECK-GI-NEXT: eor w8, w8, w9
+; CHECK-GI-NEXT: eor w9, w10, w11
+; CHECK-GI-NEXT: eor w0, w8, w9
+; CHECK-GI-NEXT: ret
%xor_result = call i8 @llvm.vector.reduce.xor.v32i8(<32 x i8> %a)
ret i8 %xor_result
}
define i16 @test_redxor_v4i16(<4 x i16> %a) {
-; CHECK-LABEL: test_redxor_v4i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: eor x8, x8, x8, lsr #32
-; CHECK-NEXT: lsr x9, x8, #16
-; CHECK-NEXT: eor w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redxor_v4i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: eor x8, x8, x8, lsr #32
+; CHECK-SD-NEXT: lsr x9, x8, #16
+; CHECK-SD-NEXT: eor w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redxor_v4i16:
-; GISEL: // %bb.0:
-; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; GISEL-NEXT: umov w8, v0.h[0]
-; GISEL-NEXT: umov w9, v0.h[1]
-; GISEL-NEXT: umov w10, v0.h[2]
-; GISEL-NEXT: umov w11, v0.h[3]
-; GISEL-NEXT: eor w8, w8, w9
-; GISEL-NEXT: eor w9, w10, w11
-; GISEL-NEXT: eor w0, w8, w9
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redxor_v4i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: umov w8, v0.h[0]
+; CHECK-GI-NEXT: umov w9, v0.h[1]
+; CHECK-GI-NEXT: umov w10, v0.h[2]
+; CHECK-GI-NEXT: umov w11, v0.h[3]
+; CHECK-GI-NEXT: eor w8, w8, w9
+; CHECK-GI-NEXT: eor w9, w10, w11
+; CHECK-GI-NEXT: eor w0, w8, w9
+; CHECK-GI-NEXT: ret
%xor_result = call i16 @llvm.vector.reduce.xor.v4i16(<4 x i16> %a)
ret i16 %xor_result
}
define i16 @test_redxor_v8i16(<8 x i16> %a) {
-; CHECK-LABEL: test_redxor_v8i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: eor x8, x8, x8, lsr #32
-; CHECK-NEXT: lsr x9, x8, #16
-; CHECK-NEXT: eor w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redxor_v8i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: eor x8, x8, x8, lsr #32
+; CHECK-SD-NEXT: lsr x9, x8, #16
+; CHECK-SD-NEXT: eor w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redxor_v8i16:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov d1, v0.d[1]
-; GISEL-NEXT: eor v0.8b, v0.8b, v1.8b
-; GISEL-NEXT: umov w8, v0.h[0]
-; GISEL-NEXT: umov w9, v0.h[1]
-; GISEL-NEXT: umov w10, v0.h[2]
-; GISEL-NEXT: umov w11, v0.h[3]
-; GISEL-NEXT: eor w8, w8, w9
-; GISEL-NEXT: eor w9, w10, w11
-; GISEL-NEXT: eor w0, w8, w9
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redxor_v8i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: umov w8, v0.h[0]
+; CHECK-GI-NEXT: umov w9, v0.h[1]
+; CHECK-GI-NEXT: umov w10, v0.h[2]
+; CHECK-GI-NEXT: umov w11, v0.h[3]
+; CHECK-GI-NEXT: eor w8, w8, w9
+; CHECK-GI-NEXT: eor w9, w10, w11
+; CHECK-GI-NEXT: eor w0, w8, w9
+; CHECK-GI-NEXT: ret
%xor_result = call i16 @llvm.vector.reduce.xor.v8i16(<8 x i16> %a)
ret i16 %xor_result
}
define i16 @test_redxor_v16i16(<16 x i16> %a) {
-; CHECK-LABEL: test_redxor_v16i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: eor x8, x8, x8, lsr #32
-; CHECK-NEXT: lsr x9, x8, #16
-; CHECK-NEXT: eor w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redxor_v16i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: eor v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: eor x8, x8, x8, lsr #32
+; CHECK-SD-NEXT: lsr x9, x8, #16
+; CHECK-SD-NEXT: eor w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redxor_v16i16:
-; GISEL: // %bb.0:
-; GISEL-NEXT: eor v0.16b, v0.16b, v1.16b
-; GISEL-NEXT: mov d1, v0.d[1]
-; GISEL-NEXT: eor v0.8b, v0.8b, v1.8b
-; GISEL-NEXT: umov w8, v0.h[0]
-; GISEL-NEXT: umov w9, v0.h[1]
-; GISEL-NEXT: umov w10, v0.h[2]
-; GISEL-NEXT: umov w11, v0.h[3]
-; GISEL-NEXT: eor w8, w8, w9
-; GISEL-NEXT: eor w9, w10, w11
-; GISEL-NEXT: eor w0, w8, w9
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redxor_v16i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: eor v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: umov w8, v0.h[0]
+; CHECK-GI-NEXT: umov w9, v0.h[1]
+; CHECK-GI-NEXT: umov w10, v0.h[2]
+; CHECK-GI-NEXT: umov w11, v0.h[3]
+; CHECK-GI-NEXT: eor w8, w8, w9
+; CHECK-GI-NEXT: eor w9, w10, w11
+; CHECK-GI-NEXT: eor w0, w8, w9
+; CHECK-GI-NEXT: ret
%xor_result = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> %a)
ret i16 %xor_result
}
define i32 @test_redxor_v2i32(<2 x i32> %a) {
-; CHECK-LABEL: test_redxor_v2i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: lsr x9, x8, #32
-; CHECK-NEXT: eor w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redxor_v2i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: lsr x9, x8, #32
+; CHECK-SD-NEXT: eor w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redxor_v2i32:
-; GISEL: // %bb.0:
-; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; GISEL-NEXT: mov w8, v0.s[1]
-; GISEL-NEXT: fmov w9, s0
-; GISEL-NEXT: eor w0, w9, w8
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redxor_v2i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: mov w8, v0.s[1]
+; CHECK-GI-NEXT: fmov w9, s0
+; CHECK-GI-NEXT: eor w0, w9, w8
+; CHECK-GI-NEXT: ret
%xor_result = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> %a)
ret i32 %xor_result
}
define i32 @test_redxor_v4i32(<4 x i32> %a) {
-; CHECK-LABEL: test_redxor_v4i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: lsr x9, x8, #32
-; CHECK-NEXT: eor w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redxor_v4i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: lsr x9, x8, #32
+; CHECK-SD-NEXT: eor w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redxor_v4i32:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov d1, v0.d[1]
-; GISEL-NEXT: eor v0.8b, v0.8b, v1.8b
-; GISEL-NEXT: mov w8, v0.s[1]
-; GISEL-NEXT: fmov w9, s0
-; GISEL-NEXT: eor w0, w9, w8
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redxor_v4i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: mov w8, v0.s[1]
+; CHECK-GI-NEXT: fmov w9, s0
+; CHECK-GI-NEXT: eor w0, w9, w8
+; CHECK-GI-NEXT: ret
%xor_result = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %a)
ret i32 %xor_result
}
define i32 @test_redxor_v8i32(<8 x i32> %a) {
-; CHECK-LABEL: test_redxor_v8i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: lsr x9, x8, #32
-; CHECK-NEXT: eor w0, w8, w9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redxor_v8i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: eor v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: lsr x9, x8, #32
+; CHECK-SD-NEXT: eor w0, w8, w9
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redxor_v8i32:
-; GISEL: // %bb.0:
-; GISEL-NEXT: eor v0.16b, v0.16b, v1.16b
-; GISEL-NEXT: mov d1, v0.d[1]
-; GISEL-NEXT: eor v0.8b, v0.8b, v1.8b
-; GISEL-NEXT: mov w8, v0.s[1]
-; GISEL-NEXT: fmov w9, s0
-; GISEL-NEXT: eor w0, w9, w8
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redxor_v8i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: eor v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: mov w8, v0.s[1]
+; CHECK-GI-NEXT: fmov w9, s0
+; CHECK-GI-NEXT: eor w0, w9, w8
+; CHECK-GI-NEXT: ret
%xor_result = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %a)
ret i32 %xor_result
}
define i64 @test_redxor_v2i64(<2 x i64> %a) {
-; CHECK-LABEL: test_redxor_v2i64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redxor_v2i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redxor_v2i64:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mov x8, v0.d[1]
-; GISEL-NEXT: fmov x9, d0
-; GISEL-NEXT: eor x0, x9, x8
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redxor_v2i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: fmov x9, d0
+; CHECK-GI-NEXT: eor x0, x9, x8
+; CHECK-GI-NEXT: ret
%xor_result = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> %a)
ret i64 %xor_result
}
define i64 @test_redxor_v4i64(<4 x i64> %a) {
-; CHECK-LABEL: test_redxor_v4i64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_redxor_v4i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: eor v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_redxor_v4i64:
-; GISEL: // %bb.0:
-; GISEL-NEXT: eor v0.16b, v0.16b, v1.16b
-; GISEL-NEXT: mov x8, v0.d[1]
-; GISEL-NEXT: fmov x9, d0
-; GISEL-NEXT: eor x0, x9, x8
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_redxor_v4i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: eor v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: mov x8, v0.d[1]
+; CHECK-GI-NEXT: fmov x9, d0
+; CHECK-GI-NEXT: eor x0, x9, x8
+; CHECK-GI-NEXT: ret
%xor_result = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %a)
ret i64 %xor_result
}
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