[lldb] [llvm] [AArch64][llvm] Tighten SYSP parsing; don't disassemble invalid encodings (PR #182410)

[via llvm-commits]

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@@ -813,6 +813,13 @@ def XSeqPairsClass   : RegisterClass<"AArch64", [untyped], 64,
                                      (add XSeqPairs)>{
   let Size = 128;
 }
+def SyspPairsClass   : RegisterClass<"AArch64", [untyped], 64,
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CarolineConcatto wrote:

 `SYSPxt` appears to be MC-only, but `SyspPairsClass` is a real RegisterClass mixing `XSeqPairs` and
  `XZR`. That causes TableGen to emit register-bank/subregister/allocation-order metadata such as
  `SyspPairsClass_and_GPR64`, even though this operand is only used for SYSP assembly/disassembly.

  Could this be modeled with a custom operand/parser/decoder/printer while keeping the underlying register
  class as `XSeqPairsClass` plus an explicit `XZR` case, instead of introducing a new physical register
  class?
If not, can you add a comment why this needs to be a register class

https://github.com/llvm/llvm-project/pull/182410