[llvm] [AArch64][GlobalISel] Add pre-legalizer combines for AVGFLOOR and AVGCEIL (PR #192866)

[Matt Arsenault via llvm-commits]

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@@ -8697,3 +8697,110 @@ bool CombinerHelper::matchCtls(MachineInstr &CtlzMI,
 
   return true;
 }
+
+static bool matchAnySExt(MachineRegisterInfo &MRI, Register Reg,
+                         Register &ExtSrc) {
+  if (mi_match(Reg, MRI, m_GSExt(m_Reg(ExtSrc))))
+    return true;
+
+  MachineInstr *ExtInst = MRI.getVRegDef(Reg);
+  if (ExtInst && ExtInst->getOpcode() == TargetOpcode::G_SEXT_INREG) {
+    ExtSrc = ExtInst->getOperand(1).getReg();
+    return true;
+  }
+  return false;
+}
+
+// Fold shr ( add ( ext X, ext Y ), 1 ) -> avgfloor ( x, y )
+bool CombinerHelper::matchAVGFloor(MachineInstr &MI, Register X, Register Y,
+                                   bool IsSigned,
+                                   MachineRegisterInfo &MRI) const {
+  assert((MI.getOpcode() == TargetOpcode::G_LSHR ||
+          MI.getOpcode() == TargetOpcode::G_ASHR) &&
+         "Expected G_LSHR/G_ASHR");
+
+  LLT XTy = MRI.getType(X);
+  LLT YTy = MRI.getType(Y);
+
+  if (XTy != YTy)
+    return false;
+
+  Register Dst = MI.getOperand(0).getReg();
+  LLT DstTy = MRI.getType(Dst);
+
+  unsigned TargetOpc =
+      IsSigned ? TargetOpcode::G_SAVGFLOOR : TargetOpcode::G_UAVGFLOOR;
+  if (!isLegal({TargetOpc, {DstTy}}))
+    return false;
+
+  return true;
+}
+
+// Fold shr ( add ( ext X, ext Y, 1 ), 1 ) -> avgceil ( x, y )
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arsenm wrote:

Should be able to pull more of this into tablegen? 

https://github.com/llvm/llvm-project/pull/192866