[llvm] [AMDGPU] Mark WAIT_ASYNCMARK as zero-size instruction (PR #195107)

[Zhewen Yu via llvm-commits]

https://github.com/Yu-Zhewen updated https://github.com/llvm/llvm-project/pull/195107

>From f527cdc7bcef239423f6485fadb0bd33e8edb030 Mon Sep 17 00:00:00 2001
From: Yu-Zhewen <zhewenyu at amd.com>
Date: Thu, 30 Apr 2026 15:15:29 +0000
Subject: [PATCH 1/2] zero size

Signed-off-by: Yu-Zhewen <zhewenyu at amd.com>
---
 llvm/lib/Target/AMDGPU/SOPInstructions.td | 1 +
 1 file changed, 1 insertion(+)

diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index eb7ad8bcb04ce..e0bdcf61440f3 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -1736,6 +1736,7 @@ def ASYNCMARK : SPseudoInstSI<(outs), (ins),
 def WAIT_ASYNCMARK : SOPP_Pseudo <"", (ins s16imm:$simm16), "$simm16",
     [(int_amdgcn_wait_asyncmark timm:$simm16)]> {
     let maybeAtomic = 0;
+    let Size = 0;
     let isMeta = 1;
 }
 }

>From 7af4e87323b9a8960d0c9af002b7b68b4710ec87 Mon Sep 17 00:00:00 2001
From: Yu-Zhewen <zhewenyu at amd.com>
Date: Thu, 30 Apr 2026 15:50:05 +0000
Subject: [PATCH 2/2] add test

Signed-off-by: Yu-Zhewen <zhewenyu at amd.com>
---
 llvm/test/CodeGen/AMDGPU/code-size-estimate.mir | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/llvm/test/CodeGen/AMDGPU/code-size-estimate.mir b/llvm/test/CodeGen/AMDGPU/code-size-estimate.mir
index 9ae536af6f0e9..3ad963b0f723c 100644
--- a/llvm/test/CodeGen/AMDGPU/code-size-estimate.mir
+++ b/llvm/test/CodeGen/AMDGPU/code-size-estimate.mir
@@ -32,6 +32,21 @@ body:             |
   WAVE_BARRIER
 ...
 
+# WAIT_ASYNCMARK is a meta instruction that emits zero bytes.
+# codeLenInByte = s_waitcnt (4) + WAIT_ASYNCMARK (0) = 4.
+# CHECK: wait_asyncmark_meta:                    ; @wait_asyncmark_meta
+# CHECK: ; wait_asyncmark(1)
+# CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
+# CHECK: ; codeLenInByte = 4
+---
+name:            wait_asyncmark_meta
+tracksRegLiveness: true
+body:             |
+  bb.0:
+
+  WAIT_ASYNCMARK 1
+...
+
 # CHECK: align4:                                 ; @align4
 # CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
 # CHECK: s_cbranch_scc1 .LBB{{[0-9_]+}}          ; encoding: [A,A,0x85,0xbf]