[llvm] [CodeGen][NFC] Refactor inline asm constraint determination (PR #195104)

[Matt Arsenault via llvm-commits]

================
@@ -10320,66 +10312,55 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
              "Can only indirectify direct input operands!");
 
       // Memory operands really want the address of the value.
-      Chain = getAddressForMemoryInput(Chain, getCurSDLoc(), OpInfo, DAG);
+      Info.Chain = getAddressForMemoryInput(Info.Chain, Builder.getCurSDLoc(),
+                                            OpInfo, DAG);
 
       // There is no longer a Value* corresponding to this operand.
       OpInfo.CallOperandVal = nullptr;
 
       // It is now an indirect operand.
       OpInfo.isIndirect = true;
     }
-
   }
+}
 
-  // AsmNodeOperands - The operands for the ISD::INLINEASM node.
-  std::vector<SDValue> AsmNodeOperands;
-  AsmNodeOperands.push_back(SDValue());  // reserve space for input chain
-  AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
-      IA->getAsmString().data(), TLI.getProgramPointerTy(DAG.getDataLayout())));
-
-  // If we have a !srcloc metadata node associated with it, we want to attach
-  // this to the ultimately generated inline asm machineinstr.  To do this, we
-  // pass in the third operand as this (potentially null) inline asm MDNode.
-  const MDNode *SrcLoc = Call.getMetadata("srcloc");
-  AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
-
-  // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
-  // bits as operand 3.
-  AsmNodeOperands.push_back(DAG.getTargetConstant(
-      ExtraInfo.get(), getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
-
-  // Third pass: Loop over operands to prepare DAG-level operands.. As part of
-  // this, assign virtual and physical registers for inputs and otput.
-  for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) {
+/// Prepare DAG-level operands. As part of this, assign virtual and physical
+/// registers for inputs and output.
+static bool PrepareDAGLevelOperands(ConstraintDecisionInfo &Info,
+                                    const CallBase &Call,
+                                    SelectionDAGBuilder &Builder,
+                                    const TargetLowering &TLI,
+                                    SelectionDAG &DAG) {
+  SDLoc DL = Builder.getCurSDLoc();
+  for (SDISelAsmOperandInfo &OpInfo : Info.ConstraintOperands) {
     // Assign Registers.
     SDISelAsmOperandInfo &RefOpInfo =
         OpInfo.isMatchingInputConstraint()
-            ? ConstraintOperands[OpInfo.getMatchedOperand()]
+            ? Info.ConstraintOperands[OpInfo.getMatchedOperand()]
             : OpInfo;
-    const auto RegError =
-        getRegistersForValue(DAG, getCurSDLoc(), OpInfo, RefOpInfo);
+    const auto RegError = getRegistersForValue(DAG, DL, OpInfo, RefOpInfo);
     if (RegError) {
       const MachineFunction &MF = DAG.getMachineFunction();
       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
       const char *RegName = TRI.getName(*RegError);
-      emitInlineAsmError(Call, "register '" + Twine(RegName) +
-                                   "' allocated for constraint '" +
-                                   Twine(OpInfo.ConstraintCode) +
-                                   "' does not match required type");
-      return;
+      Info.ErrorMsg << "register '" << RegName << "' allocated for constraint '"
+                    << OpInfo.ConstraintCode
+                    << "' does not match required type";
+      return true;
     }
 
     auto DetectWriteToReservedRegister = [&]() {
       const MachineFunction &MF = DAG.getMachineFunction();
       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
+
       for (Register Reg : OpInfo.AssignedRegs.Regs) {
         if (Reg.isPhysical() && TRI.isInlineAsmReadOnlyReg(MF, Reg)) {
-          const char *RegName = TRI.getName(Reg);
-          emitInlineAsmError(Call, "write to reserved register '" +
-                                       Twine(RegName) + "'");
+          Info.ErrorMsg << "write to reserved register '" << TRI.getName(Reg)
----------------
arsenm wrote:

This probably should have been getRegAsmName

https://github.com/llvm/llvm-project/pull/195104