[llvm] [RegisterCoalescer] Fix incorrect VNInfo deletion condition in pruneSubRegValues (PR #195023)

[via llvm-commits]

https://github.com/mkovacevic99 updated https://github.com/llvm/llvm-project/pull/195023

>From cf6a86cbce62a93fac28aa5a9d501ecaee730c7a Mon Sep 17 00:00:00 2001
From: Milica Kovacevic <mkovacevic at baylibre.com>
Date: Thu, 30 Apr 2026 09:05:40 +0200
Subject: [PATCH] [RegisterCoalescer] Fix incorrect VNInfo deletion condition
 in pruneSubRegValues

---
 llvm/lib/CodeGen/RegisterCoalescer.cpp        |  3 +-
 .../RISCV/rvv/regcoal-liveinterval-pruning.ll | 61 +++++++++++++++++++
 2 files changed, 63 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/regcoal-liveinterval-pruning.ll

diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index 586c27b7e3baf..a8405f8a729c8 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -3421,7 +3421,8 @@ void JoinVals::pruneSubRegValues(LiveInterval &LI, LaneBitmask &ShrinkMask) {
         LIS->pruneValue(S, Def, &EndPoints);
         DidPrune = true;
         // Mark value number as unused.
-        ValueOut->markUnused();
+        if (ValueOut->def == Def)
+          ValueOut->markUnused();
 
         if (V.Identical && S.Query(OtherDef).valueOutOrDead()) {
           // If V is identical to V.OtherVNI (and S was live at OtherDef),
diff --git a/llvm/test/CodeGen/RISCV/rvv/regcoal-liveinterval-pruning.ll b/llvm/test/CodeGen/RISCV/rvv/regcoal-liveinterval-pruning.ll
new file mode 100644
index 0000000000000..0547b68a77653
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/regcoal-liveinterval-pruning.ll
@@ -0,0 +1,61 @@
+; RUN: llc -mtriple=riscv64 -O1 < %s | FileCheck %s
+
+
+define <8 x i64> @ID156249() #0 {
+; CHECK-LABEL: ID156249:
+
+; Entry setup
+; CHECK:       vsetivli {{.*}} e64
+; CHECK-NEXT:  vmv.v.i
+
+entry:
+  br label %ac
+
+ac:
+  %e.2 = phi <8 x i64> [ zeroinitializer, %entry ], [ %vecins, %ac ], [ %vecins4, %asm.fallthrough3 ], [ %vecins2, %asm.fallthrough ]
+  %vecins = insertelement <8 x i64> %e.2, i64 0, i64 0
+
+; First scalar insert
+; CHECK:       vsetivli {{.*}} e64
+; CHECK-NEXT:  vmv.s.x
+
+  callbr void asm sideeffect "", "!i"()
+          to label %asm.fallthrough [label %ac]
+
+asm.fallthrough:
+  %vecins2 = shufflevector <8 x i64> %vecins, <8 x i64> splat (i64 1),
+                             <8 x i32> <i32 0, i32 1, i32 2, i32 10, i32 4, i32 5, i32 6, i32 7>
+
+; Shuffle lowering sequence
+; CHECK:       vsetivli {{.*}} e8
+; CHECK-NEXT:  vmv.v.i
+; CHECK-NEXT:  vsetivli {{.*}} e64
+; CHECK-NEXT:  vmv.v.i
+; CHECK-NEXT:  vslideup.vi
+; CHECK-NEXT:  vmv.v.v
+
+  callbr void asm sideeffect "", "!i"()
+          to label %asm.fallthrough3 [label %ac]
+
+asm.fallthrough3:
+  %vecins4 = insertelement <8 x i64> %vecins2, i64 0, i64 0
+
+; Second scalar insert
+; CHECK:       vsetivli {{.*}} e64
+; CHECK-NEXT:  vmv.s.x
+
+  callbr void asm sideeffect "", "!i"()
+          to label %asm.fallthrough5 [label %ac]
+
+asm.fallthrough5:
+  %or = or <8 x i64> %vecins2, %vecins4
+
+; Final combine + return
+; CHECK:       vsetivli {{.*}} e64
+; CHECK-NEXT:  vor.vv
+; CHECK-NEXT:  ret
+
+  ret <8 x i64> %or
+}
+
+attributes #0 = { "target-features"="+v" }