[llvm] 2d8f233 - [AMDGPU][GlobalISel] Add RegBankLegalize rules for amdgcn_sqrt (#194231)
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Thu Apr 30 06:25:01 PDT 2026
Author: Mahmoud Naderi
Date: 2026-04-30T13:24:55Z
New Revision: 2d8f233b30c325a57cc596cb72f025d7137da150
URL: https://github.com/llvm/llvm-project/commit/2d8f233b30c325a57cc596cb72f025d7137da150
DIFF: https://github.com/llvm/llvm-project/commit/2d8f233b30c325a57cc596cb72f025d7137da150.diff
LOG: [AMDGPU][GlobalISel] Add RegBankLegalize rules for amdgcn_sqrt (#194231)
The new rule matches the existing uniform/divergent behavior used for
pseudo-scalar transcendental intrinsics
issue #192497
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 8f9f9cc3f2663..ae8a4c951a7a7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1921,6 +1921,16 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(S32, {{Sgpr32}, {IntrId, Sgpr32}}, hasPST)
.Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32}}, !hasPST);
+ addRulesForIOpcs({amdgcn_sqrt}, Standard)
+ .Div(S16, {{Vgpr16}, {IntrId, Vgpr16}})
+ .Uni(S16, {{Sgpr16}, {IntrId, Sgpr16}}, hasPST)
+ .Uni(S16, {{UniInVgprS16}, {IntrId, Vgpr16}}, !hasPST)
+ .Div(S32, {{Vgpr32}, {IntrId, Vgpr32}})
+ .Uni(S32, {{Sgpr32}, {IntrId, Sgpr32}}, hasPST)
+ .Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32}}, !hasPST)
+ .Div(S64, {{Vgpr64}, {IntrId, Vgpr64}})
+ .Uni(S64, {{UniInVgprS64}, {IntrId, Vgpr64}});
+
addRulesForIOpcs({amdgcn_ds_atomic_async_barrier_arrive_b64})
.Any({{}, {{}, {IntrId, VgprP3}}});
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir
index af0db8a692775..33c14b9ef530c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir
@@ -199,7 +199,80 @@ body: |
%2:_(s16) = G_FSQRT %1
%3:_(s32) = G_ANYEXT %2(s16)
$vgpr0 = COPY %3(s32)
+...
+---
+name: v_amdgcn_sqrt_f64_divergent
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: v_amdgcn_sqrt_f64_divergent
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), [[COPY]](s64)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[INT]](s64)
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), %0(s64)
+ $vgpr0_vgpr1 = COPY %1(s64)
+...
+---
+name: v_amdgcn_sqrt_f32_divergent
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: v_amdgcn_sqrt_f32_divergent
+ ; CHECK: liveins: $vgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), [[COPY]](s32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), %0(s32)
+ $vgpr0 = COPY %1(s32)
+
+...
+---
+name: v_amdgcn_sqrt_f16_divergent
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: v_amdgcn_sqrt_f16_divergent
+ ; CHECK: liveins: $vgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), [[TRUNC]](s16)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[INT]](s16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s16) = G_TRUNC %0(s32)
+ %2:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), %1(s16)
+ %3:_(s32) = G_ANYEXT %2(s16)
+ $vgpr0 = COPY %3(s32)
+...
+---
+name: v_amdgcn_sqrt_f64
+legalized: true
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+ ; CHECK-LABEL: name: v_amdgcn_sqrt_f64
+ ; CHECK: liveins: $sgpr0_sgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
+ ; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), [[COPY1]](s64)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[INT]](s64)
+ %0:_(s64) = COPY $sgpr0_sgpr1
+ %1:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), %0(s64)
+ $vgpr0_vgpr1 = COPY %1(s64)
...
---
name: v_amdgcn_sqrt_f32
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.ll
index 0257a3d111421..dfc4ce7903b01 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.ll
@@ -3,6 +3,7 @@
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s
define float @v_sqrt_f32(float %src) {
; GCN-LABEL: v_sqrt_f32:
@@ -70,6 +71,15 @@ define double @v_fneg_fabs_sqrt_f64(double %src) {
ret double %sqrt
}
+define double @s_sqrt_f64(double inreg %src) {
+; GFX12-LABEL: s_sqrt_f64:
+; GFX12: ; %bb.0:
+; GFX12: v_sqrt_f64_e32 v[0:1], s[0:1]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %sqrt = call double @llvm.amdgcn.sqrt.f64(double %src)
+ ret double %sqrt
+}
+
declare float @llvm.amdgcn.sqrt.f32(float) #0
declare double @llvm.amdgcn.sqrt.f64(double) #0
declare float @llvm.fabs.f32(float) #0
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