[clang] [llvm] [RISCV][MC] Support experimental Zvdota Family instructions (PR #195069)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 30 05:46:15 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Liao Chunyu (ChunyuLiao)
<details>
<summary>Changes</summary>
Zvbdota Family, I will create another pr.
Spec: https://github.com/aswaterman/riscv-misc/blob/main/isa/ldot-bdot/ldot-bdot.adoc
---
Patch is 20.96 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/195069.diff
13 Files Affected:
- (modified) clang/test/Driver/print-supported-extensions-riscv.c (+4)
- (modified) clang/test/Preprocessor/riscv-target-features.c (+36)
- (modified) llvm/docs/RISCVUsage.rst (+3)
- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp (+5-1)
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+30)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+1)
- (added) llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td (+42)
- (modified) llvm/test/CodeGen/RISCV/attributes.ll (+8)
- (modified) llvm/test/CodeGen/RISCV/features-info.ll (+5-1)
- (added) llvm/test/MC/RISCV/rvv/zvfqwdota8f.s (+40)
- (added) llvm/test/MC/RISCV/rvv/zvfwdota16bf.s (+27)
- (added) llvm/test/MC/RISCV/rvv/zvqwdotai8i16.s (+28)
- (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+4)
``````````diff
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 1a832451ed7bc..3a9f3ce5e549c 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -252,7 +252,11 @@
// CHECK-NEXT: zvdot4a8i 0.1 'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers)
// CHECK-NEXT: zvfbfa 0.1 'Zvfbfa' (Additional BF16 vector compute support)
// CHECK-NEXT: zvfofp8min 0.2 'Zvfofp8min' (Vector OFP8 Converts)
+// CHECK-NEXT: zvfqwdota8f 0.2 'Zvfqwdota8f' (OCP FP8 Dot-Product)
+// CHECK-NEXT: zvfwdota16bf 0.2 'Zvfwdota16bf' (BF16 Dot-Product)
// CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)
+// CHECK-NEXT: zvqwdota16i 0.2 'Zvqwdota16i' (16-bit Integer Dot-Product)
+// CHECK-NEXT: zvqwdota8i 0.2 'Zvqwdota8i' (8-bit Integer Dot-Product)
// CHECK-NEXT: zvzip 0.1 'Zvzip' (Vector Reordering Structured Data)
// CHECK-NEXT: smpmpmt 0.6 'Smpmpmt' (PMP-based Memory Types Extension)
// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 3882f2889eb59..5dadb9cc3dc1f 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -148,6 +148,10 @@
// CHECK-NOT: __riscv_zve64d {{.*$}}
// CHECK-NOT: __riscv_zve64f {{.*$}}
// CHECK-NOT: __riscv_zve64x {{.*$}}
+// CHECK-NOT: __riscv_zvqwdota8i {{.*$}}
+// CHECK-NOT: __riscv_zvqwdota16i {{.*$}}
+// CHECK-NOT: __riscv_zvfqwdota8f {{.*$}}
+// CHECK-NOT: __riscv_zvfwdota16bf {{.*$}}
// CHECK-NOT: __riscv_zvfbfmin {{.*$}}
// CHECK-NOT: __riscv_zvfbfwma {{.*$}}
// CHECK-NOT: __riscv_zvfh {{.*$}}
@@ -1673,6 +1677,38 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVDOT4A8I-EXT %s
// CHECK-ZVDOT4A8I-EXT: __riscv_zvdot4a8i 1000{{$}}
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve32x_zvqwdota8i0p2 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVQWDOTA8I-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve32x_zvqwdota8i0p2 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVQWDOTA8I-EXT %s
+// CHECK-ZVQWDOTA8I-EXT: __riscv_zvqwdota8i 2000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve32x_zvqwdota16i0p2 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVQWDOTA16I-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve32x_zvqwdota16i0p2 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVQWDOTA16I-EXT %s
+// CHECK-ZVQWDOTA16I-EXT: __riscv_zvqwdota16i 2000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve32x_zvfqwdota8f0p2 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFQWDOTA8F-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve32x_zvfqwdota8f0p2 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFQWDOTA8F-EXT %s
+// CHECK-ZVFQWDOTA8F-EXT: __riscv_zvfqwdota8f 2000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve32x_zvfwdota16bf0p2 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFWDOTA16BF-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve32x_zvfwdota16bf0p2 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFWDOTA16BF-EXT %s
+// CHECK-ZVFWDOTA16BF-EXT: __riscv_zvfwdota16bf 2000{{$}}
+
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_zve32x_zvzip0p1 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVZVIP-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index bfc7d0afa008b..cc68a4e01001e 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -353,6 +353,9 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-zvdot4a8i``
LLVM implements the `0.1 draft specification <https://github.com/riscv/riscv-isa-manual/pull/2576>`__.
+``experimental-zvqwdota8i``, ``experimental-zvqwdota16i``, ``experimental-zvfwdota16bf``, ``experimental-zvvfqwdota8f``
+ LLVM implements the `0.2 draft specification <https://github.com/aswaterman/riscv-misc/blob/main/isa/ldot-bdot/ldot-bdot.adoc>`__.
+
``experimental-smpmpmt``
LLVM implements the `0.6 draft specification <https://github.com/riscv/riscv-isa-manual/blob/smpmpmt/src/smpmpmt.adoc>`__.
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
index b381b8f7147fc..456f119440aba 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -225,7 +225,11 @@ void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
// above.
if (!RISCVVType::isValidVType(Imm) ||
(RISCVVType::isAltFmt(Imm) &&
- !(STI.hasFeature(RISCV::FeatureStdExtZvfbfa) ||
+ !(STI.hasFeature(RISCV::FeatureStdExtZvqwdota8i) ||
+ STI.hasFeature(RISCV::FeatureStdExtZvqwdota16i) ||
+ STI.hasFeature(RISCV::FeatureStdExtZvfwdota16bf) ||
+ STI.hasFeature(RISCV::FeatureStdExtZvfqwdota8f) ||
+ STI.hasFeature(RISCV::FeatureStdExtZvfbfa) ||
STI.hasFeature(RISCV::FeatureStdExtZvfofp8min) ||
STI.hasFeature(RISCV::FeatureVendorXSfvfbfexp16e))) ||
(Imm >> 9) != 0) {
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 825c78509519d..a248acccb845b 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -690,6 +690,36 @@ def HasStdExtZvabd : Predicate<"Subtarget->hasStdExtZvabd()">,
AssemblerPredicate<(all_of FeatureStdExtZvabd),
"'Zvabd' (Vector Absolute Difference)">;
+def FeatureStdExtZvqwdota8i
+ : RISCVExperimentalExtension<0, 2, "8-bit Integer Dot-Product", [FeatureStdExtZve32x]>;
+def HasStdExtZvqwdota8i : Predicate<"Subtarget->hasStdExtZvqwdota8i()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvqwdota8i),
+ "'Zvqwdota8i' (8-bit Integer Dot-Product)">;
+
+def FeatureStdExtZvqwdota16i
+ : RISCVExperimentalExtension<0, 2, "16-bit Integer Dot-Product", [FeatureStdExtZve64x]>;
+def HasStdExtZvqwdota16i : Predicate<"Subtarget->hasStdExtZvqwdota16i()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvqwdota16i),
+ "'Zvqwdota16i' (16-bit Integer Dot-Product)">;
+
+def HasStdExtZvqwdota8iOrZvqwdota16i
+ : Predicate<"Subtarget->hasStdExtZvqwdota8i() || Subtarget->hasStdExtZvqwdota16i() ">,
+ AssemblerPredicate<(any_of FeatureStdExtZvqwdota8i, FeatureStdExtZvqwdota16i),
+ "'Zvqwdota8i' (8-bit Integer Dot-Product) or "
+ "'Zvqwdota16i' (16-bit Integer Dot-Product)">;
+
+def FeatureStdExtZvfwdota16bf
+ : RISCVExperimentalExtension<0, 2, "BF16 Dot-Product", [FeatureStdExtZve32f]>;
+def HasStdExtZvfwdota16bf : Predicate<"Subtarget->hasStdExtZvfwdota16bf()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvfwdota16bf),
+ "'Zvfwdota16bf' (BF16 Dot-Product)">;
+
+def FeatureStdExtZvfqwdota8f
+ : RISCVExperimentalExtension<0, 2, "OCP FP8 Dot-Product", [FeatureStdExtZve32f]>;
+def HasStdExtZvfqwdota8f : Predicate<"Subtarget->hasStdExtZvfqwdota8f()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvfqwdota8f),
+ "'Zvfqwdota8f' (OCP FP8 Dot-Product)">;
+
def FeatureStdExtZvfbfa
: RISCVExperimentalExtension<0, 1, "Additional BF16 vector compute support",
[FeatureStdExtZve32f, FeatureStdExtZfbfmin]>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 18a04857cc5b2..701d32fb9e73f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2352,6 +2352,7 @@ include "RISCVInstrInfoZk.td"
// Vector
include "RISCVInstrInfoV.td"
include "RISCVInstrInfoZvabd.td"
+include "RISCVInstrInfoZvdota.td"
include "RISCVInstrInfoZvk.td"
include "RISCVInstrInfoZvdot4a8i.td"
include "RISCVInstrInfoZvfofp8min.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td
new file mode 100644
index 0000000000000..69bb4025fa065
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td
@@ -0,0 +1,42 @@
+//===-- RISCVInstrInfoZvqwdotZvbdot.td - 'ZvqwdotZvbdot' instructions ------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// This file describes the RISC-V instructions for 'ZvqwdotZvbdot'.
+///
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instruction Definitions
+//===----------------------------------------------------------------------===//
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+// op vd, vs2, vs1, vm
+class ZvdotVALUVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+ : RVInstVV<funct6, opv, (outs VR:$vd),
+ (ins VR:$vs2, VR:$vs1, VMaskOp:$vm),
+ opcodestr, "$vd, $vs2, $vs1$vm"> {
+ let Inst{6-0} = OPC_OP_VE.Value;
+}
+}
+let Predicates = [HasStdExtZvqwdota8iOrZvqwdota16i],
+ Constraints = "@earlyclobber $vd", DestEEW = EEWSEWx4 in {
+ def VQWDOTAU_VV : ZvdotVALUVV<0b100110, OPIVV, "vqwdotau.vv">;
+ def VQWDOTAS_VV : ZvdotVALUVV<0b100111, OPIVV, "vqwdotas.vv">;
+} // Predicates = [HasStdExtZvqwdota8iOrZvqwdota16i]
+
+let Predicates = [HasStdExtZvfqwdota8f],
+ Constraints = "@earlyclobber $vd",
+ mayRaiseFPException = true, DestEEW = EEWSEWx4 in {
+ def VFQWDOTA_VV : ZvdotVALUVV<0b010110, OPFVV, "vfqwdota.vv">;
+ def VFQWDOTA_ALT_VV : ZvdotVALUVV<0b010111, OPFVV, "vfqwdota.alt.vv">;
+} // Predicates = [HasStdExtZvfqwdota8f]
+
+let Predicates = [HasStdExtZvfwdota16bf],
+ Constraints = "@earlyclobber $vd",
+ mayRaiseFPException = true, DestEEW = EEWSEWx2 in {
+ def VFWDOTA_VV : ZvdotVALUVV<0b010100, OPFVV, "vfwdota.vv">;
+} // Predicates = [HasStdExtZvfwdota16bf]
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 9da6766692e99..234088444323d 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -267,6 +267,10 @@
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV64ZVKT %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvdot4a8i %s -o - | FileCheck --check-prefix=RV64ZVDOT4A8I %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvqwdota8i %s -o - | FileCheck --check-prefix=RV64ZVQWDOTA8I %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvqwdota16i %s -o - | FileCheck --check-prefix=RV64ZVQWDOTA16I %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvfwdota16bf %s -o - | FileCheck --check-prefix=RV64ZVFWDOTA16BF %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvfqwdota8f %s -o - | FileCheck --check-prefix=RV64ZVFQWDOTA8F %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvzip %s -o - | FileCheck --check-prefix=RV64ZVZIP %s
; RUN: llc -mtriple=riscv64 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV64ZVFH %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvabd %s -o - | FileCheck --check-prefix=RV64ZVABD %s
@@ -588,6 +592,10 @@
; RV64ZVKSH: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksh1p0_zvl32b1p0"
; RV64ZVKT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0"
; RV64ZVDOT4A8I: .attribute 5, "rv64i2p1_zicsr2p0_zvdot4a8i0p1_zve32x1p0_zvl32b1p0"
+; RV64ZVQWDOTA8I: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvqwdota8i0p2"
+; RV64ZVQWDOTA16I: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_zvqwdota16i0p2"
+; RV64ZVFWDOTA16BF: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfwdota16bf0p2_zvl32b1p0"
+; RV64ZVFQWDOTA8F: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfqwdota8f0p2_zvl32b1p0"
; RV64ZVZIP: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvzip0p1"
; RV64ZVFH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0"
; RV64ZVABD: .attribute 5, "rv64i2p1_zicsr2p0_zvabd0p7_zve32x1p0_zvl32b1p0"
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index 9f3cfb5a181f2..107ca1da8860a 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -38,7 +38,11 @@
; CHECK-NEXT: experimental-zvdot4a8i - 'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers).
; CHECK-NEXT: experimental-zvfbfa - 'Zvfbfa' (Additional BF16 vector compute support).
; CHECK-NEXT: experimental-zvfofp8min - 'Zvfofp8min' (Vector OFP8 Converts).
-; CHECK-NEXT: experimental-zvkgs - 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography).
+; CHECK-NEXT: experimental-zvfqwdota8f - 'Zvfqwdota8f' (OCP FP8 Dot-Product).
+; CHECK-NEXT: experimental-zvfwdota16bf - 'Zvfwdota16bf' (BF16 Dot-Product).
+; CHECK-NEXT: experimental-zvkgs - 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography).
+; CHECK-NEXT: experimental-zvqwdota16i - 'Zvqwdota16i' (16-bit Integer Dot-Product).
+; CHECK-NEXT: experimental-zvqwdota8i - 'Zvqwdota8i' (8-bit Integer Dot-Product).
; CHECK-NEXT: experimental-zvzip - 'Zvzip' (Vector Reordering Structured Data).
; CHECK-NEXT: f - 'F' (Single-Precision Floating-Point).
; CHECK-NEXT: forced-atomics - Assume that lock-free native-width atomics are available.
diff --git a/llvm/test/MC/RISCV/rvv/zvfqwdota8f.s b/llvm/test/MC/RISCV/rvv/zvfqwdota8f.s
new file mode 100644
index 0000000000000..818b50ed0bd55
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/zvfqwdota8f.s
@@ -0,0 +1,40 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+v --mattr=+experimental-zvfqwdota8f %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvfqwdota8f %s \
+# RUN: | llvm-objdump -d --mattr=+v --mattr=+experimental-zvfqwdota8f --no-print-imm-hex - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvfqwdota8f %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsetvli a2, a0, e8alt, m1, ta, ma
+# CHECK-INST: vsetvli a2, a0, e8alt, m1, ta, ma
+# CHECK-ENCODING: [0x57,0x76,0x05,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
+# CHECK-UNKNOWN: 1c057657 <unknown>
+
+vfqwdota.vv v10, v9, v8
+# CHECK-INST: vfqwdota.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x15,0x94,0x5a]
+# CHECK-ERROR: instruction requires the following: 'Zvfqwdota8f' (OCP FP8 Dot-Product)
+# CHECK-UNKNOWN: 5a941577 <unknown>
+
+vfqwdota.vv v10, v9, v8, v0.t
+# CHECK-INST: vfqwdota.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x77,0x15,0x94,0x58]
+# CHECK-ERROR: instruction requires the following: 'Zvfqwdota8f' (OCP FP8 Dot-Product)
+# CHECK-UNKNOWN: 58941577 <unknown>
+
+vfqwdota.alt.vv v10, v9, v8
+# CHECK-INST: vfqwdota.alt.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x15,0x94,0x5e]
+# CHECK-ERROR: instruction requires the following: 'Zvfqwdota8f' (OCP FP8 Dot-Product)
+# CHECK-UNKNOWN: 5e941577 <unknown>
+
+vfqwdota.alt.vv v10, v9, v8, v0.t
+# CHECK-INST: vfqwdota.alt.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x77,0x15,0x94,0x5c]
+# CHECK-ERROR: instruction requires the following: 'Zvfqwdota8f' (OCP FP8 Dot-Product)
+# CHECK-UNKNOWN: 5c941577 <unknown>
+
diff --git a/llvm/test/MC/RISCV/rvv/zvfwdota16bf.s b/llvm/test/MC/RISCV/rvv/zvfwdota16bf.s
new file mode 100644
index 0000000000000..354f7a6a94f82
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/zvfwdota16bf.s
@@ -0,0 +1,27 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+v --mattr=+experimental-zvfwdota16bf %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvfwdota16bf %s \
+# RUN: | llvm-objdump -d --mattr=+v --mattr=+experimental-zvfwdota16bf --no-print-imm-hex - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvfwdota16bf %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsetvli a2, a0, e8alt, m1, ta, ma
+# CHECK-INST: vsetvli a2, a0, e8alt, m1, ta, ma
+# CHECK-ENCODING: [0x57,0x76,0x05,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
+# CHECK-UNKNOWN: 1c057657 <unknown>
+
+vfwdota.vv v10, v9, v8
+# CHECK-INST: vfwdota.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x15,0x94,0x52]
+# CHECK-ERROR: instruction requires the following: 'Zvfwdota16bf' (BF16 Dot-Product)
+# CHECK-UNKNOWN: 52941577 <unknown>
+
+vfwdota.vv v10, v9, v8, v0.t
+# CHECK-INST: vfwdota.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x77,0x15,0x94,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zvfwdota16bf' (BF16 Dot-Product)
+# CHECK-UNKNOWN: 50941577 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/zvqwdotai8i16.s b/llvm/test/MC/RISCV/rvv/zvqwdotai8i16.s
new file mode 100644
index 0000000000000..0a2636bacc5b7
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/zvqwdotai8i16.s
@@ -0,0 +1,28 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+v --mattr=+experimental-zvqwdota8i %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvqwdota8i %s \
+# RUN: | llvm-objdump -d --mattr=+v --mattr=+experimental-zvqwdota8i --no-print-imm-hex - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvqwdota8i %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsetvli a2, a0, e8alt, m1, ta, ma
+# CHECK-INST: vsetvli a2, a0, e8alt, m1, ta, ma
+# CHECK-ENCODING: [0x57,0x76,0x05,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
+# CHECK-UNKNOWN: 1c057657 <unknown>
+
+vqwdotau.vv v10, v9, v8
+# CHECK-INST: vqwdotau.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x05,0x94,0x9a]
+# CHECK-ERROR: instruction requires the following: 'Zvqwdota8i' (8-bit Integer Dot-Product) or 'Zvqwdota16i' (16-bit Integer Dot-Pro...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/195069
More information about the llvm-commits
mailing list