[llvm] [GlobalISel][KnownBits] Use KnownBits::urem for G_UREM (PR #193455)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 30 04:56:26 PDT 2026
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/193455
>From f5423e2512eb342a0335103b81eb4e6a923e0647 Mon Sep 17 00:00:00 2001
From: Tejas Gaikwad <tgaikwad966 at gmail.com>
Date: Fri, 27 Mar 2026 18:47:17 +0000
Subject: [PATCH 01/11] [GlobalISel][AArch64] - Add G_UREM computeKnownBits
---
.../CodeGen/GlobalISel/GISelValueTracking.cpp | 33 +++++++++++++++++
.../AArch64/GlobalISel/knownbits-urem.mir | 35 +++++++++++++++++++
2 files changed, 68 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index 32b533d93fb31..896350954c684 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -285,6 +285,7 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
}
break;
}
+<<<<<<< HEAD
case TargetOpcode::G_STEP_VECTOR: {
APInt Step = MI.getOperand(1).getCImm()->getValue();
@@ -309,6 +310,38 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
Known.Zero.setHighBits(MaxValue.countl_zero());
break;
}
+=======
+ case TargetOpcode::G_UREM: {
+ KnownBits LHSKnown(Known.getBitWidth());
+ KnownBits RHSKnown(Known.getBitWidth());
+
+ computeKnownBitsImpl(MI.getOperand(1).getReg(), LHSKnown, DemandedElts,
+ Depth + 1);
+ computeKnownBitsImpl(MI.getOperand(2).getReg(), RHSKnown, DemandedElts,
+ Depth + 1);
+
+ APInt MaxRHS = RHSKnown.getMaxValue();
+
+ if (MaxRHS.isPowerOf2()) {
+ unsigned LowBits = MaxRHS.logBase2();
+ // Upper bits are zero
+ Known.Zero.setBitsFrom(LowBits);
+ // Mask for lower bits
+ APInt Mask = APInt::getLowBitsSet(Known.getBitWidth(), LowBits);
+ // Propagate known bits from LHS for lower bits
+ Known.One |= (LHSKnown.One & Mask);
+ Known.Zero |= (LHSKnown.Zero & Mask);
+ break;
+ }
+ if (!MaxRHS.isZero()) {
+ unsigned LeadingZeros = MaxRHS.countLeadingZeros();
+ Known.Zero.setHighBits(LeadingZeros);
+ }
+
+ break;
+ }
+
+>>>>>>> 4d20a64c45fc ([GlobalISel][AArch64] - Add G_UREM computeKnownBits)
case TargetOpcode::G_CONSTANT: {
Known = KnownBits::makeConstant(MI.getOperand(1).getCImm()->getValue());
break;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
new file mode 100644
index 0000000000000..f164d32a11bd3
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
@@ -0,0 +1,35 @@
+# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple aarch64 -passes="print<gisel-value-tracking>" %s -filetype=null 2>&1 | FileCheck %s
+
+--- |
+ ; ModuleID = 'urem_aarch64_gisel_test.ll'
+ source_filename = "urem_aarch64_gisel_test.ll"
+ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
+ target triple = "aarch64"
+
+ define i32 @urem_pow2(i32 %x) {
+ %y = urem i32 %x, 8
+ ret i32 %y
+ }
+...
+---
+name: urem_pow2
+
+body: |
+ bb.1 (%ir-block.0):
+
+ ; CHECK-LABEL: name: @urem_pow2
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:00000000000000000000000000001000 SignBits:28
+ ; CHECK-NEXT: %2:_ KnownBits:00000000000000000000000000000??? SignBits:29
+
+ liveins: $w0
+
+ %0:_(s32) = COPY $w0
+ %1:_(s32) = G_CONSTANT i32 8
+ %2:_(s32) = G_UREM %0, %1
+ $w0 = COPY %2(s32)
+ RET_ReallyLR implicit $w0
+...
+## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+# CHECK: {{.*}}
>From 3aef1a28dd0d3dba72af9e42aa6591ec230db127 Mon Sep 17 00:00:00 2001
From: Tejas Gaikwad <tgaikwad966 at gmail.com>
Date: Sun, 29 Mar 2026 17:35:49 +0000
Subject: [PATCH 02/11] resolving comments
---
.../CodeGen/GlobalISel/GISelValueTracking.cpp | 8 ++++----
.../AArch64/GlobalISel/knownbits-urem.mir | 17 +----------------
2 files changed, 5 insertions(+), 20 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index 896350954c684..65148b7bedd1c 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -327,10 +327,10 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
// Upper bits are zero
Known.Zero.setBitsFrom(LowBits);
// Mask for lower bits
- APInt Mask = APInt::getLowBitsSet(Known.getBitWidth(), LowBits);
- // Propagate known bits from LHS for lower bits
- Known.One |= (LHSKnown.One & Mask);
- Known.Zero |= (LHSKnown.Zero & Mask);
+ KnownBits TruncLHS = LHSKnown.trunc(LowBits).zext(Known.getBitWidth());
+
+ Known.One |= TruncLHS.One;
+ Known.Zero |= TruncLHS.Zero;
break;
}
if (!MaxRHS.isZero()) {
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
index f164d32a11bd3..b5c70f46a35cc 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
@@ -1,22 +1,10 @@
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple aarch64 -passes="print<gisel-value-tracking>" %s -filetype=null 2>&1 | FileCheck %s
---- |
- ; ModuleID = 'urem_aarch64_gisel_test.ll'
- source_filename = "urem_aarch64_gisel_test.ll"
- target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
- target triple = "aarch64"
-
- define i32 @urem_pow2(i32 %x) {
- %y = urem i32 %x, 8
- ret i32 %y
- }
-...
----
name: urem_pow2
body: |
- bb.1 (%ir-block.0):
+ bb.1:
; CHECK-LABEL: name: @urem_pow2
; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
@@ -30,6 +18,3 @@ body: |
%2:_(s32) = G_UREM %0, %1
$w0 = COPY %2(s32)
RET_ReallyLR implicit $w0
-...
-## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-# CHECK: {{.*}}
>From 247ac2c5d4a681ce804b0a6ff46686cd0ca86738 Mon Sep 17 00:00:00 2001
From: Tejas Gaikwad <tgaikwad966 at gmail.com>
Date: Wed, 22 Apr 2026 10:08:01 +0000
Subject: [PATCH 03/11] [GlobalISel][KnownBits] Use KnownBits::urem for G_UREM
---
.../CodeGen/GlobalISel/GISelValueTracking.cpp | 25 +++++--------------
1 file changed, 6 insertions(+), 19 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index 65148b7bedd1c..3d78edd4f7d6a 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -285,7 +285,7 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
}
break;
}
-<<<<<<< HEAD
+
case TargetOpcode::G_STEP_VECTOR: {
APInt Step = MI.getOperand(1).getCImm()->getValue();
@@ -310,7 +310,9 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
Known.Zero.setHighBits(MaxValue.countl_zero());
break;
}
-=======
+
+
+>>>>>>> d6326def9f85 ([GlobalISel][KnownBits] Use KnownBits::urem for G_UREM)
case TargetOpcode::G_UREM: {
KnownBits LHSKnown(Known.getBitWidth());
KnownBits RHSKnown(Known.getBitWidth());
@@ -320,24 +322,9 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
computeKnownBitsImpl(MI.getOperand(2).getReg(), RHSKnown, DemandedElts,
Depth + 1);
- APInt MaxRHS = RHSKnown.getMaxValue();
-
- if (MaxRHS.isPowerOf2()) {
- unsigned LowBits = MaxRHS.logBase2();
- // Upper bits are zero
- Known.Zero.setBitsFrom(LowBits);
- // Mask for lower bits
- KnownBits TruncLHS = LHSKnown.trunc(LowBits).zext(Known.getBitWidth());
-
- Known.One |= TruncLHS.One;
- Known.Zero |= TruncLHS.Zero;
- break;
- }
- if (!MaxRHS.isZero()) {
- unsigned LeadingZeros = MaxRHS.countLeadingZeros();
- Known.Zero.setHighBits(LeadingZeros);
- }
+ KnownBits Res = KnownBits::urem(LHSKnown, RHSKnown);
+ Known = Res;
break;
}
>From 17ea14401181e51448915171b139407c8ba13244 Mon Sep 17 00:00:00 2001
From: Tejas Gaikwad <150573693+tejasgaikwad04 at users.noreply.github.com>
Date: Fri, 24 Apr 2026 22:47:31 +0530
Subject: [PATCH 04/11] Apply suggestion from @arsenm
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
---
llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index 3d78edd4f7d6a..f9f13fa1cc323 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -324,7 +324,7 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
KnownBits Res = KnownBits::urem(LHSKnown, RHSKnown);
- Known = Res;
+ Known = KnownBits::urem(LHSKnown, RHSKnown);
break;
}
>From a1c8b8ec1ab36cf92cb2112b51dde72a814340b1 Mon Sep 17 00:00:00 2001
From: Tejas Gaikwad <tgaikwad966 at gmail.com>
Date: Mon, 27 Apr 2026 18:05:15 +0000
Subject: [PATCH 05/11] Addressing comments
---
llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp | 4 ----
1 file changed, 4 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index f9f13fa1cc323..d05f248e33833 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -311,8 +311,6 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
break;
}
-
->>>>>>> d6326def9f85 ([GlobalISel][KnownBits] Use KnownBits::urem for G_UREM)
case TargetOpcode::G_UREM: {
KnownBits LHSKnown(Known.getBitWidth());
KnownBits RHSKnown(Known.getBitWidth());
@@ -323,12 +321,10 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
Depth + 1);
KnownBits Res = KnownBits::urem(LHSKnown, RHSKnown);
-
Known = KnownBits::urem(LHSKnown, RHSKnown);
break;
}
->>>>>>> 4d20a64c45fc ([GlobalISel][AArch64] - Add G_UREM computeKnownBits)
case TargetOpcode::G_CONSTANT: {
Known = KnownBits::makeConstant(MI.getOperand(1).getCImm()->getValue());
break;
>From bb163df607aba0efc75a0893a7b25cf8a4c531f8 Mon Sep 17 00:00:00 2001
From: Tejas Gaikwad <tgaikwad966 at gmail.com>
Date: Mon, 27 Apr 2026 18:33:07 +0000
Subject: [PATCH 06/11] Addressing spaces
---
llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp | 3 ---
1 file changed, 3 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index d05f248e33833..a3c5aaeea2a2d 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -285,7 +285,6 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
}
break;
}
-
case TargetOpcode::G_STEP_VECTOR: {
APInt Step = MI.getOperand(1).getCImm()->getValue();
@@ -310,7 +309,6 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
Known.Zero.setHighBits(MaxValue.countl_zero());
break;
}
-
case TargetOpcode::G_UREM: {
KnownBits LHSKnown(Known.getBitWidth());
KnownBits RHSKnown(Known.getBitWidth());
@@ -324,7 +322,6 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
Known = KnownBits::urem(LHSKnown, RHSKnown);
break;
}
-
case TargetOpcode::G_CONSTANT: {
Known = KnownBits::makeConstant(MI.getOperand(1).getCImm()->getValue());
break;
>From 2938adc72933b4effd84c808ce96408c68dd3d68 Mon Sep 17 00:00:00 2001
From: Tejas Gaikwad <150573693+tejasgaikwad04 at users.noreply.github.com>
Date: Tue, 28 Apr 2026 00:05:24 +0530
Subject: [PATCH 07/11] Apply suggestion from @arsenm
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
---
llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index a3c5aaeea2a2d..47d00e5ab3763 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -318,7 +318,6 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
computeKnownBitsImpl(MI.getOperand(2).getReg(), RHSKnown, DemandedElts,
Depth + 1);
- KnownBits Res = KnownBits::urem(LHSKnown, RHSKnown);
Known = KnownBits::urem(LHSKnown, RHSKnown);
break;
}
>From a611847988eb21f9456776cac633a691df663c37 Mon Sep 17 00:00:00 2001
From: Tejas Gaikwad <150573693+tejasgaikwad04 at users.noreply.github.com>
Date: Tue, 28 Apr 2026 00:08:08 +0530
Subject: [PATCH 08/11] Apply suggestion from @arsenm
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
---
llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
index b5c70f46a35cc..cbbb6e8d4a821 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
@@ -2,7 +2,6 @@
# RUN: llc -mtriple aarch64 -passes="print<gisel-value-tracking>" %s -filetype=null 2>&1 | FileCheck %s
name: urem_pow2
-
body: |
bb.1:
>From 82655dfb9a35c60464c56296b3f250f6bcc999b3 Mon Sep 17 00:00:00 2001
From: Tejas Gaikwad <150573693+tejasgaikwad04 at users.noreply.github.com>
Date: Tue, 28 Apr 2026 00:08:22 +0530
Subject: [PATCH 09/11] Apply suggestion from @arsenm
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
---
llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
index cbbb6e8d4a821..cd42608fce6c7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
@@ -3,7 +3,7 @@
name: urem_pow2
body: |
- bb.1:
+ bb.0:
; CHECK-LABEL: name: @urem_pow2
; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
>From 5f5c2be9973a89404ea47d9141881cf487936c53 Mon Sep 17 00:00:00 2001
From: Tejas Gaikwad <tgaikwad966 at gmail.com>
Date: Tue, 28 Apr 2026 18:21:25 +0000
Subject: [PATCH 10/11] adding more testcases
---
.../AArch64/GlobalISel/knownbits-urem.mir | 98 +++++++++++++++++--
1 file changed, 90 insertions(+), 8 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
index cd42608fce6c7..4c988fdcddc3c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
@@ -1,19 +1,101 @@
-# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple aarch64 -passes="print<gisel-value-tracking>" %s -filetype=null 2>&1 | FileCheck %s
-name: urem_pow2
-body: |
- bb.0:
+# CHECK-LABEL: name: @urem_pow2
+# CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
+# CHECK-NEXT: %1:_ KnownBits:00000000000000000000000000001000 SignBits:28
+# CHECK-NEXT: %2:_ KnownBits:00000000000000000000000000000??? SignBits:29
- ; CHECK-LABEL: name: @urem_pow2
- ; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
- ; CHECK-NEXT: %1:_ KnownBits:00000000000000000000000000001000 SignBits:28
- ; CHECK-NEXT: %2:_ KnownBits:00000000000000000000000000000??? SignBits:29
+name: urem_pow2
+body: |
+ bb.1:
+ liveins: $w0
+ %0:_(s32) = COPY $w0
+ %1:_(s32) = G_CONSTANT i32 8
+ %2:_(s32) = G_UREM %0, %1
+ $w0 = COPY %2(s32)
+ RET_ReallyLR implicit $w0
+...
+
+# CHECK-LABEL: name: @urem_non_pow2
+# CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
+# CHECK-NEXT: %1:_ KnownBits:00000000000000000000000000001010 SignBits:28
+# CHECK-NEXT: %2:_ KnownBits:0000000000000000000000000000???? SignBits:28
+
+name: urem_non_pow2
+body: |
+ bb.1:
liveins: $w0
%0:_(s32) = COPY $w0
+ %1:_(s32) = G_CONSTANT i32 10
+ %2:_(s32) = G_UREM %0, %1
+ $w0 = COPY %2(s32)
+ RET_ReallyLR implicit $w0
+...
+
+# CHECK-LABEL: name: @urem
+# CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
+# CHECK-NEXT: %1:_ KnownBits:???????????????????????????????? SignBits:1
+# CHECK-NEXT: %2:_ KnownBits:???????????????????????????????? SignBits:1
+
+name: urem
+body: |
+ bb.1:
+ liveins: $w0, $w1
+
+ %0:_(s32) = COPY $w0
+ %1:_(s32) = COPY $w1
+ %2:_(s32) = G_UREM %0, %1
+ $w0 = COPY %2(s32)
+ RET_ReallyLR implicit $w0
+...
+
+# CHECK-LABEL: name: @urem_implicit_def
+# CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
+# CHECK-NEXT: %1:_ KnownBits:00000000000000000000000000001000 SignBits:28
+# CHECK-NEXT: %2:_ KnownBits:00000000000000000000000000000??? SignBits:29
+
+name: urem_implicit_def
+body: |
+ bb.1:
+ liveins: $w0
+
+ %0:_(s32) = G_IMPLICIT_DEF
%1:_(s32) = G_CONSTANT i32 8
%2:_(s32) = G_UREM %0, %1
$w0 = COPY %2(s32)
RET_ReallyLR implicit $w0
+...
+
+# CHECK-LABEL: name: @urem_both_implicit_def
+# CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
+# CHECK-NEXT: %1:_ KnownBits:???????????????????????????????? SignBits:1
+# CHECK-NEXT: %2:_ KnownBits:???????????????????????????????? SignBits:1
+
+name: urem_both_implicit_def
+body: |
+ bb.1:
+
+ %0:_(s32) = G_IMPLICIT_DEF
+ %1:_(s32) = G_IMPLICIT_DEF
+ %2:_(s32) = G_UREM %0, %1
+ $w0 = COPY %2(s32)
+ RET_ReallyLR implicit $w0
+...
+
+# CHECK-LABEL: name: @urem_const_const
+# CHECK-NEXT: %0:_ KnownBits:00000000000000000000000000001010 SignBits:28
+# CHECK-NEXT: %1:_ KnownBits:00000000000000000000000000000011 SignBits:30
+# CHECK-NEXT: %2:_ KnownBits:000000000000000000000000000000?? SignBits:30
+
+name: urem_const_const
+body: |
+ bb.1:
+
+ %0:_(s32) = G_CONSTANT i32 10
+ %1:_(s32) = G_CONSTANT i32 3
+ %2:_(s32) = G_UREM %0, %1
+ $w0 = COPY %2(s32)
+ RET_ReallyLR implicit $w0
+...
\ No newline at end of file
>From ad927162208868bc68a98270d7a29d3383d60a68 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <arsenm2 at gmail.com>
Date: Thu, 30 Apr 2026 12:56:11 +0100
Subject: [PATCH 11/11] missing newline
---
llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
index 4c988fdcddc3c..c6146d4d1b271 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
@@ -98,4 +98,4 @@ body: |
%2:_(s32) = G_UREM %0, %1
$w0 = COPY %2(s32)
RET_ReallyLR implicit $w0
-...
\ No newline at end of file
+...
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