[llvm] [AMDGPU] Refactor setreg handling in the VGPR MSB lowering (PR #186491)

[Stanislav Mekhanoshin via llvm-commits]

rampitec wrote:

> First, I don't understand the requirement, Are you trying to generate code that would run correctly on chips both with and without the bug? Why is that needed?

Well, look. We just cannot rely on the HW bug for correct behavior. That is what we are doing now: expecting a buggy logic to update the bits.

> Second, if we _are_ trying to do that, then can't you simplify the setreg handling a lot more? We don't need any of the case 1, case 2, case 3 stuff, we can just forget any known MSBs every time we see a setreg.

Force MSB every time? This not needed in the first place, and would never be needed if not of this issue. Practically that means it would regress all over the board, if we just issue MSB updates just because of the hazard.


https://github.com/llvm/llvm-project/pull/186491