[llvm] f966490 - [AMDGPU] Extend max3/min3 tree-reduction combine to cover ternary chains (#194845)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 30 03:20:54 PDT 2026
Author: Dark Steve
Date: 2026-04-30T15:50:49+05:30
New Revision: f966490e30698f4cceb184cf28f6b5162338ef57
URL: https://github.com/llvm/llvm-project/commit/f966490e30698f4cceb184cf28f6b5162338ef57
DIFF: https://github.com/llvm/llvm-project/commit/f966490e30698f4cceb184cf28f6b5162338ef57.diff
LOG: [AMDGPU] Extend max3/min3 tree-reduction combine to cover ternary chains (#194845)
The tree-reduction combine for min/max currently trigger on shapes where
both children of a node are same-opcode. This patch extends it to also
recognize cases where only one child is same-opcode and one-use like
max(max(a, b), c) feeding another max.
For example, with R = max(max(A, B), C) where A, B, and C are each
ternary chains of the form max(max(x, y), z), the current predicate does
not recognize the ternary-chain interiors as still combinable, so the
higher-level rules fire eagerly and produce max3 nodes with 2-op maxes
inside them. With the extended predicate, each ternary chain is allowed
to fold into a max3 first, after which the higher levels reduce cleanly
without leaving stranded 2-op maxes behind.
Adds six regression tests covering a 2-level ternary chain, a mixed
ternary+binary shape and vector examples.
Fix: LCOMPILER-2166
Added:
Modified:
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll
llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 92d9e305f2c3b..64d7a9b299a0b 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -16012,11 +16012,18 @@ SDValue SITargetLowering::performMinMaxCombine(SDNode *N,
if (supportsMin3Max3(*Subtarget, Opc, VT)) {
auto IsTreeWithCombinableChildren = [Opc](SDValue Op) {
- return Op.getOperand(0).getOpcode() == Opc &&
- Op.getOperand(1).getOpcode() == Opc &&
- (Op.getOperand(0).hasOneUse() || Op.getOperand(1).hasOneUse());
+ return (Op.getOperand(0).getOpcode() == Opc &&
+ Op.getOperand(0).hasOneUse()) ||
+ (Op.getOperand(1).getOpcode() == Opc &&
+ Op.getOperand(1).hasOneUse());
};
+ bool CanTreeCombineApply = Op0.getOpcode() == Opc && Op0.hasOneUse() &&
+ Op1.getOpcode() == Opc && Op1.hasOneUse();
+ bool HasCombinableTreeChild =
+ CanTreeCombineApply && (IsTreeWithCombinableChildren(Op0) ||
+ IsTreeWithCombinableChildren(Op1));
+
// Tree reduction: when both operands are the same min/max op, restructure
// to keep a 2-op node on top so higher tree levels can still combine.
//
@@ -16024,9 +16031,7 @@ SDValue SITargetLowering::performMinMaxCombine(SDNode *N,
// min(min(a, b), min(c, d)) -> min(min3(a, b, c), d)
//
// Defer when either inner op is a tree node with combinable children.
- if (Op0.getOpcode() == Opc && Op0.hasOneUse() && Op1.getOpcode() == Opc &&
- Op1.hasOneUse() && !IsTreeWithCombinableChildren(Op0) &&
- !IsTreeWithCombinableChildren(Op1)) {
+ if (CanTreeCombineApply && !HasCombinableTreeChild) {
SDLoc DL(N);
SDValue Inner =
DAG.getNode(minMaxOpcToMin3Max3Opc(Opc), DL, VT, Op0.getOperand(0),
@@ -16037,8 +16042,7 @@ SDValue SITargetLowering::performMinMaxCombine(SDNode *N,
// max(max(a, b), c) -> max3(a, b, c)
// min(min(a, b), c) -> min3(a, b, c)
// Deferred when Op0 is a tree node with combinable children.
- if (Op0.getOpcode() == Opc && Op0.hasOneUse() &&
- !IsTreeWithCombinableChildren(Op0)) {
+ if (Op0.getOpcode() == Opc && Op0.hasOneUse() && !HasCombinableTreeChild) {
SDLoc DL(N);
return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc), DL, N->getValueType(0),
Op0.getOperand(0), Op0.getOperand(1), Op1);
@@ -16048,8 +16052,7 @@ SDValue SITargetLowering::performMinMaxCombine(SDNode *N,
// max(a, max(b, c)) -> max3(a, b, c)
// min(a, min(b, c)) -> min3(a, b, c)
// Deferred when Op1 is a tree node with combinable children.
- if (Op1.getOpcode() == Opc && Op1.hasOneUse() &&
- !IsTreeWithCombinableChildren(Op1)) {
+ if (Op1.getOpcode() == Opc && Op1.hasOneUse() && !HasCombinableTreeChild) {
SDLoc DL(N);
return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc), DL, N->getValueType(0),
Op0, Op1.getOperand(0), Op1.getOperand(1));
diff --git a/llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll b/llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll
index 88c38ccbb1508..a8f5d1d1bc4b4 100644
--- a/llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll
+++ b/llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll
@@ -38,10 +38,10 @@ define float @v_max3_maxnum_tree8_f32(float %a, float %b, float %c, float %d,
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_max3_f32 v0, v0, v1, v2
-; GFX9-NEXT: v_max_f32_e32 v1, v3, v3
-; GFX9-NEXT: v_max_f32_e32 v0, v0, v1
; GFX9-NEXT: v_max3_f32 v1, v4, v5, v6
-; GFX9-NEXT: v_max3_f32 v0, v0, v1, v7
+; GFX9-NEXT: v_max3_f32 v0, v0, v3, v1
+; GFX9-NEXT: v_max_f32_e32 v1, v7, v7
+; GFX9-NEXT: v_max_f32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_max3_maxnum_tree8_f32:
@@ -49,11 +49,11 @@ define float @v_max3_maxnum_tree8_f32(float %a, float %b, float %c, float %d,
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_max3_num_f32 v0, v0, v1, v2
-; GFX1250-NEXT: v_max_num_f32_e32 v1, v3, v3
+; GFX1250-NEXT: v_max3_num_f32 v1, v4, v5, v6
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_max3_num_f32 v0, v0, v3, v1
+; GFX1250-NEXT: v_max_num_f32_e32 v1, v7, v7
; GFX1250-NEXT: v_max_num_f32_e32 v0, v0, v1
-; GFX1250-NEXT: v_max3_num_f32 v1, v4, v5, v6
-; GFX1250-NEXT: v_max3_num_f32 v0, v0, v1, v7
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
float %e, float %f, float %g, float %h) {
%ab = call float @llvm.maxnum.f32(float %a, float %b)
@@ -132,9 +132,9 @@ define float @v_maximum3_tree8_f32(float %a, float %b, float %c, float %d,
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_maximum3_f32 v0, v0, v1, v2
; GFX1250-NEXT: v_maximum3_f32 v1, v4, v5, v6
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_maximum_f32 v0, v0, v3
-; GFX1250-NEXT: v_maximum3_f32 v0, v0, v1, v7
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_maximum3_f32 v0, v0, v3, v1
+; GFX1250-NEXT: v_maximum_f32 v0, v0, v7
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
float %e, float %f, float %g, float %h) {
%ab = call float @llvm.maximum.f32(float %a, float %b)
@@ -261,17 +261,15 @@ define float @v_maximum3_tree16_f32(float %a, float %b, float %c, float %d,
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_maximum3_f32 v0, v0, v1, v2
-; GFX1250-NEXT: v_maximum3_f32 v1, v8, v9, v10
-; GFX1250-NEXT: v_maximum3_f32 v2, v4, v5, v6
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-NEXT: v_maximum_f32 v0, v0, v3
-; GFX1250-NEXT: v_maximum_f32 v1, v1, v11
-; GFX1250-NEXT: v_maximum3_f32 v3, v12, v13, v14
+; GFX1250-NEXT: v_maximum3_f32 v1, v4, v5, v6
+; GFX1250-NEXT: v_maximum3_f32 v2, v8, v9, v10
+; GFX1250-NEXT: v_maximum3_f32 v4, v12, v13, v14
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-NEXT: v_maximum3_f32 v0, v0, v2, v7
-; GFX1250-NEXT: v_maximum3_f32 v1, v1, v3, v15
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_maximum_f32 v0, v0, v1
+; GFX1250-NEXT: v_maximum3_f32 v0, v0, v3, v1
+; GFX1250-NEXT: v_maximum3_f32 v1, v2, v11, v4
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_maximum3_f32 v0, v0, v7, v1
+; GFX1250-NEXT: v_maximum_f32 v0, v0, v15
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
float %e, float %f, float %g, float %h,
float %i, float %j, float %k, float %l,
@@ -318,9 +316,10 @@ define float @v_maximum3_tree_unbalanced_f32(float %a, float %b, float %c, float
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_maximum3_f32 v0, v0, v1, v2
+; GFX1250-NEXT: v_maximum_f32 v0, v0, v1
+; GFX1250-NEXT: v_maximum_f32 v1, v2, v3
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_maximum3_f32 v0, v0, v3, v4
+; GFX1250-NEXT: v_maximum3_f32 v0, v0, v1, v4
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%ab = call float @llvm.maximum.f32(float %a, float %b)
%cd = call float @llvm.maximum.f32(float %c, float %d)
@@ -397,11 +396,12 @@ define float @v_maximum3_tree8_asymmetric_use(float %a, float %b, float %c, floa
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_maximum3_f32 v4, v4, v5, v6
+; GFX1250-NEXT: v_maximum_f32 v0, v0, v1
+; GFX1250-NEXT: v_maximum_f32 v1, v2, v3
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_maximum_f32 v2, v4, v7
; GFX1250-NEXT: v_maximum3_f32 v0, v0, v1, v2
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_maximum_f32 v1, v4, v7
-; GFX1250-NEXT: v_maximum3_f32 v0, v0, v3, v1
-; GFX1250-NEXT: global_store_b32 v[8:9], v1, off
+; GFX1250-NEXT: global_store_b32 v[8:9], v2, off
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
float %e, float %f, float %g, float %h,
ptr addrspace(1) %out) {
@@ -540,6 +540,222 @@ define bfloat @v_no_max3_maxnum_tree4_bf16(bfloat %a, bfloat %b, bfloat %c, bflo
ret bfloat %result
}
+; Two-level ternary tree
+define float @v_max3_maxnum_ternary_2level_f32(
+; GFX9-LABEL: v_max3_maxnum_ternary_2level_f32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_max3_f32 v0, v0, v1, v2
+; GFX9-NEXT: v_max3_f32 v1, v3, v4, v5
+; GFX9-NEXT: v_max3_f32 v2, v6, v7, v8
+; GFX9-NEXT: v_max3_f32 v0, v0, v1, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: v_max3_maxnum_ternary_2level_f32:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_max3_num_f32 v0, v0, v1, v2
+; GFX1250-NEXT: v_max3_num_f32 v1, v3, v4, v5
+; GFX1250-NEXT: v_max3_num_f32 v2, v6, v7, v8
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_max3_num_f32 v0, v0, v1, v2
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+ float %a, float %b, float %c,
+ float %d, float %e, float %f,
+ float %g, float %h, float %i) {
+ %ab = call float @llvm.maxnum.f32(float %a, float %b)
+ %A = call float @llvm.maxnum.f32(float %ab, float %c)
+ %de = call float @llvm.maxnum.f32(float %d, float %e)
+ %B = call float @llvm.maxnum.f32(float %de, float %f)
+ %gh = call float @llvm.maxnum.f32(float %g, float %h)
+ %C = call float @llvm.maxnum.f32(float %gh, float %i)
+ %AB = call float @llvm.maxnum.f32(float %A, float %B)
+ %R = call float @llvm.maxnum.f32(float %AB, float %C)
+ ret float %R
+}
+
+; Mixed ternary + binary: one operand is a 3-leaf ternary tree, the other is
+; a 4-leaf binary tree.
+define float @v_max3_maxnum_mixed_ternary_binary_f32(
+; GFX9-LABEL: v_max3_maxnum_mixed_ternary_binary_f32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_max3_f32 v0, v0, v1, v2
+; GFX9-NEXT: v_max3_f32 v1, v3, v4, v5
+; GFX9-NEXT: v_max3_f32 v0, v0, v1, v6
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: v_max3_maxnum_mixed_ternary_binary_f32:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_max3_num_f32 v0, v0, v1, v2
+; GFX1250-NEXT: v_max3_num_f32 v1, v3, v4, v5
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_max3_num_f32 v0, v0, v1, v6
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+ float %a, float %b, float %c,
+ float %d, float %e, float %f, float %g) {
+ %ab = call float @llvm.maxnum.f32(float %a, float %b)
+ %A = call float @llvm.maxnum.f32(float %ab, float %c)
+ %de = call float @llvm.maxnum.f32(float %d, float %e)
+ %fg = call float @llvm.maxnum.f32(float %f, float %g)
+ %B = call float @llvm.maxnum.f32(float %de, float %fg)
+ %R = call float @llvm.maxnum.f32(float %A, float %B)
+ ret float %R
+}
+
+; 4-value balanced binary tree on <2 x float>
+define <2 x float> @v_max3_maxnum_tree4_v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c, <2 x float> %d) {
+; GFX9-LABEL: v_max3_maxnum_tree4_v2f32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_max3_f32 v0, v0, v2, v4
+; GFX9-NEXT: v_max_f32_e32 v2, v6, v6
+; GFX9-NEXT: v_max_f32_e32 v0, v0, v2
+; GFX9-NEXT: v_max3_f32 v1, v1, v3, v5
+; GFX9-NEXT: v_max_f32_e32 v2, v7, v7
+; GFX9-NEXT: v_max_f32_e32 v1, v1, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: v_max3_maxnum_tree4_v2f32:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_max3_num_f32 v0, v0, v2, v4
+; GFX1250-NEXT: v_max_num_f32_e32 v2, v6, v6
+; GFX1250-NEXT: v_max3_num_f32 v1, v1, v3, v5
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_dual_max_num_f32 v3, v7, v7 :: v_dual_max_num_f32 v0, v0, v2
+; GFX1250-NEXT: v_max_num_f32_e32 v1, v1, v3
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+ %max.ab = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %a, <2 x float> %b)
+ %max.cd = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %c, <2 x float> %d)
+ %result = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %max.ab, <2 x float> %max.cd)
+ ret <2 x float> %result
+}
+
+; 2-level ternary tree on <2 x float>
+define <2 x float> @v_max3_maxnum_ternary_2level_v2f32(
+; GFX9-LABEL: v_max3_maxnum_ternary_2level_v2f32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_max3_f32 v1, v1, v3, v5
+; GFX9-NEXT: v_max3_f32 v0, v0, v2, v4
+; GFX9-NEXT: v_max3_f32 v2, v7, v9, v11
+; GFX9-NEXT: v_max3_f32 v3, v6, v8, v10
+; GFX9-NEXT: v_max3_f32 v4, v13, v15, v17
+; GFX9-NEXT: v_max3_f32 v5, v12, v14, v16
+; GFX9-NEXT: v_max3_f32 v0, v0, v3, v5
+; GFX9-NEXT: v_max3_f32 v1, v1, v2, v4
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: v_max3_maxnum_ternary_2level_v2f32:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_max3_num_f32 v1, v1, v3, v5
+; GFX1250-NEXT: v_max3_num_f32 v0, v0, v2, v4
+; GFX1250-NEXT: v_max3_num_f32 v2, v7, v9, v11
+; GFX1250-NEXT: v_max3_num_f32 v3, v6, v8, v10
+; GFX1250-NEXT: v_max3_num_f32 v4, v12, v14, v16
+; GFX1250-NEXT: v_max3_num_f32 v5, v13, v15, v17
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_max3_num_f32 v0, v0, v3, v4
+; GFX1250-NEXT: v_max3_num_f32 v1, v1, v2, v5
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+ <2 x float> %a, <2 x float> %b, <2 x float> %c,
+ <2 x float> %d, <2 x float> %e, <2 x float> %f,
+ <2 x float> %g, <2 x float> %h, <2 x float> %i) {
+ %ab = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %a, <2 x float> %b)
+ %A = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %ab, <2 x float> %c)
+ %de = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %d, <2 x float> %e)
+ %B = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %de, <2 x float> %f)
+ %gh = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %g, <2 x float> %h)
+ %C = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %gh, <2 x float> %i)
+ %AB = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %A, <2 x float> %B)
+ %R = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %AB, <2 x float> %C)
+ ret <2 x float> %R
+}
+
+; 4-value balanced binary tree on <2 x half>
+define <2 x half> @v_max3_maxnum_tree4_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d) {
+; GFX9-LABEL: v_max3_maxnum_tree4_v2f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_pk_max_f16 v1, v1, v1
+; GFX9-NEXT: v_pk_max_f16 v0, v0, v0
+; GFX9-NEXT: v_pk_max_f16 v0, v0, v1
+; GFX9-NEXT: v_pk_max_f16 v1, v3, v3
+; GFX9-NEXT: v_pk_max_f16 v2, v2, v2
+; GFX9-NEXT: v_pk_max_f16 v1, v2, v1
+; GFX9-NEXT: v_pk_max_f16 v0, v0, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: v_max3_maxnum_tree4_v2f16:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_pk_max3_num_f16 v0, v0, v1, v2
+; GFX1250-NEXT: v_pk_max_num_f16 v1, v3, v3
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+ %max.ab = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %b)
+ %max.cd = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %c, <2 x half> %d)
+ %result = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %max.ab, <2 x half> %max.cd)
+ ret <2 x half> %result
+}
+
+; 2-level ternary tree on <2 x half>
+define <2 x half> @v_max3_maxnum_ternary_2level_v2f16(
+; GFX9-LABEL: v_max3_maxnum_ternary_2level_v2f16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_pk_max_f16 v1, v1, v1
+; GFX9-NEXT: v_pk_max_f16 v0, v0, v0
+; GFX9-NEXT: v_pk_max_f16 v0, v0, v1
+; GFX9-NEXT: v_pk_max_f16 v1, v2, v2
+; GFX9-NEXT: v_pk_max_f16 v0, v0, v1
+; GFX9-NEXT: v_pk_max_f16 v1, v4, v4
+; GFX9-NEXT: v_pk_max_f16 v2, v3, v3
+; GFX9-NEXT: v_pk_max_f16 v1, v2, v1
+; GFX9-NEXT: v_pk_max_f16 v2, v5, v5
+; GFX9-NEXT: v_pk_max_f16 v1, v1, v2
+; GFX9-NEXT: v_pk_max_f16 v2, v7, v7
+; GFX9-NEXT: v_pk_max_f16 v3, v6, v6
+; GFX9-NEXT: v_pk_max_f16 v2, v3, v2
+; GFX9-NEXT: v_pk_max_f16 v3, v8, v8
+; GFX9-NEXT: v_pk_max_f16 v2, v2, v3
+; GFX9-NEXT: v_pk_max_f16 v0, v0, v1
+; GFX9-NEXT: v_pk_max_f16 v0, v0, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: v_max3_maxnum_ternary_2level_v2f16:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_pk_max3_num_f16 v0, v0, v1, v2
+; GFX1250-NEXT: v_pk_max3_num_f16 v1, v3, v4, v5
+; GFX1250-NEXT: v_pk_max3_num_f16 v2, v6, v7, v8
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_pk_max3_num_f16 v0, v0, v1, v2
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+ <2 x half> %a, <2 x half> %b, <2 x half> %c,
+ <2 x half> %d, <2 x half> %e, <2 x half> %f,
+ <2 x half> %g, <2 x half> %h, <2 x half> %i) {
+ %ab = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %b)
+ %A = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %ab, <2 x half> %c)
+ %de = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %d, <2 x half> %e)
+ %B = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %de, <2 x half> %f)
+ %gh = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %g, <2 x half> %h)
+ %C = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %gh, <2 x half> %i)
+ %AB = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %A, <2 x half> %B)
+ %R = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %AB, <2 x half> %C)
+ ret <2 x half> %R
+}
+
declare float @llvm.maxnum.f32(float, float)
declare float @llvm.minnum.f32(float, float)
declare float @llvm.maximum.f32(float, float)
@@ -547,3 +763,5 @@ declare float @llvm.minimum.f32(float, float)
declare half @llvm.maxnum.f16(half, half)
declare double @llvm.maxnum.f64(double, double)
declare bfloat @llvm.maxnum.bf16(bfloat, bfloat)
+declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>)
+declare <2 x half> @llvm.maxnum.v2f16(<2 x half>, <2 x half>)
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
index 6e94fbcc1f7bb..8ca36d4b9a5fa 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
@@ -2935,15 +2935,15 @@ define i32 @test_vector_reduce_smax_v16i32(<16 x i32> %v) {
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT: v_max3_i32 v2, v2, v10, v6
-; GFX7-SDAG-NEXT: v_max3_i32 v1, v1, v9, v5
; GFX7-SDAG-NEXT: v_max_i32_e32 v4, v4, v12
; GFX7-SDAG-NEXT: v_max_i32_e32 v0, v0, v8
-; GFX7-SDAG-NEXT: v_max_i32_e32 v2, v2, v14
; GFX7-SDAG-NEXT: v_max3_i32 v3, v3, v11, v7
+; GFX7-SDAG-NEXT: v_max3_i32 v1, v1, v9, v5
+; GFX7-SDAG-NEXT: v_max_i32_e32 v2, v2, v14
+; GFX7-SDAG-NEXT: v_max_i32_e32 v3, v3, v15
; GFX7-SDAG-NEXT: v_max_i32_e32 v1, v1, v13
-; GFX7-SDAG-NEXT: v_max3_i32 v1, v1, v3, v15
; GFX7-SDAG-NEXT: v_max3_i32 v0, v0, v4, v2
-; GFX7-SDAG-NEXT: v_max_i32_e32 v0, v0, v1
+; GFX7-SDAG-NEXT: v_max3_i32 v0, v0, v1, v3
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_smax_v16i32:
@@ -2970,15 +2970,15 @@ define i32 @test_vector_reduce_smax_v16i32(<16 x i32> %v) {
; GFX8-SDAG: ; %bb.0: ; %entry
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: v_max3_i32 v2, v2, v10, v6
-; GFX8-SDAG-NEXT: v_max3_i32 v1, v1, v9, v5
; GFX8-SDAG-NEXT: v_max_i32_e32 v4, v4, v12
; GFX8-SDAG-NEXT: v_max_i32_e32 v0, v0, v8
-; GFX8-SDAG-NEXT: v_max_i32_e32 v2, v2, v14
; GFX8-SDAG-NEXT: v_max3_i32 v3, v3, v11, v7
+; GFX8-SDAG-NEXT: v_max3_i32 v1, v1, v9, v5
+; GFX8-SDAG-NEXT: v_max_i32_e32 v2, v2, v14
+; GFX8-SDAG-NEXT: v_max_i32_e32 v3, v3, v15
; GFX8-SDAG-NEXT: v_max_i32_e32 v1, v1, v13
-; GFX8-SDAG-NEXT: v_max3_i32 v1, v1, v3, v15
; GFX8-SDAG-NEXT: v_max3_i32 v0, v0, v4, v2
-; GFX8-SDAG-NEXT: v_max_i32_e32 v0, v0, v1
+; GFX8-SDAG-NEXT: v_max3_i32 v0, v0, v1, v3
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: test_vector_reduce_smax_v16i32:
@@ -3005,15 +3005,15 @@ define i32 @test_vector_reduce_smax_v16i32(<16 x i32> %v) {
; GFX9-SDAG: ; %bb.0: ; %entry
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: v_max3_i32 v2, v2, v10, v6
-; GFX9-SDAG-NEXT: v_max3_i32 v1, v1, v9, v5
; GFX9-SDAG-NEXT: v_max_i32_e32 v4, v4, v12
; GFX9-SDAG-NEXT: v_max_i32_e32 v0, v0, v8
-; GFX9-SDAG-NEXT: v_max_i32_e32 v2, v2, v14
; GFX9-SDAG-NEXT: v_max3_i32 v3, v3, v11, v7
+; GFX9-SDAG-NEXT: v_max3_i32 v1, v1, v9, v5
+; GFX9-SDAG-NEXT: v_max_i32_e32 v2, v2, v14
+; GFX9-SDAG-NEXT: v_max_i32_e32 v3, v3, v15
; GFX9-SDAG-NEXT: v_max_i32_e32 v1, v1, v13
-; GFX9-SDAG-NEXT: v_max3_i32 v1, v1, v3, v15
; GFX9-SDAG-NEXT: v_max3_i32 v0, v0, v4, v2
-; GFX9-SDAG-NEXT: v_max_i32_e32 v0, v0, v1
+; GFX9-SDAG-NEXT: v_max3_i32 v0, v0, v1, v3
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: test_vector_reduce_smax_v16i32:
@@ -3039,16 +3039,16 @@ define i32 @test_vector_reduce_smax_v16i32(<16 x i32> %v) {
; GFX10-SDAG-LABEL: test_vector_reduce_smax_v16i32:
; GFX10-SDAG: ; %bb.0: ; %entry
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_max3_i32 v1, v1, v9, v5
; GFX10-SDAG-NEXT: v_max3_i32 v2, v2, v10, v6
; GFX10-SDAG-NEXT: v_max_i32_e32 v4, v4, v12
; GFX10-SDAG-NEXT: v_max_i32_e32 v0, v0, v8
; GFX10-SDAG-NEXT: v_max3_i32 v3, v3, v11, v7
-; GFX10-SDAG-NEXT: v_max_i32_e32 v1, v1, v13
+; GFX10-SDAG-NEXT: v_max3_i32 v1, v1, v9, v5
; GFX10-SDAG-NEXT: v_max_i32_e32 v2, v2, v14
-; GFX10-SDAG-NEXT: v_max3_i32 v1, v1, v3, v15
+; GFX10-SDAG-NEXT: v_max_i32_e32 v3, v3, v15
+; GFX10-SDAG-NEXT: v_max_i32_e32 v1, v1, v13
; GFX10-SDAG-NEXT: v_max3_i32 v0, v0, v4, v2
-; GFX10-SDAG-NEXT: v_max_i32_e32 v0, v0, v1
+; GFX10-SDAG-NEXT: v_max3_i32 v0, v0, v1, v3
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: test_vector_reduce_smax_v16i32:
@@ -3074,18 +3074,18 @@ define i32 @test_vector_reduce_smax_v16i32(<16 x i32> %v) {
; GFX11-SDAG-LABEL: test_vector_reduce_smax_v16i32:
; GFX11-SDAG: ; %bb.0: ; %entry
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_max3_i32 v1, v1, v9, v5
; GFX11-SDAG-NEXT: v_max3_i32 v2, v2, v10, v6
; GFX11-SDAG-NEXT: v_max_i32_e32 v4, v4, v12
; GFX11-SDAG-NEXT: v_max_i32_e32 v0, v0, v8
; GFX11-SDAG-NEXT: v_max3_i32 v3, v3, v11, v7
-; GFX11-SDAG-NEXT: v_max_i32_e32 v1, v1, v13
+; GFX11-SDAG-NEXT: v_max3_i32 v1, v1, v9, v5
; GFX11-SDAG-NEXT: v_max_i32_e32 v2, v2, v14
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_max3_i32 v1, v1, v3, v15
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-SDAG-NEXT: v_max_i32_e32 v3, v3, v15
+; GFX11-SDAG-NEXT: v_max_i32_e32 v1, v1, v13
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_max3_i32 v0, v0, v4, v2
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_max_i32_e32 v0, v0, v1
+; GFX11-SDAG-NEXT: v_max3_i32 v0, v0, v1, v3
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: test_vector_reduce_smax_v16i32:
@@ -3119,18 +3119,18 @@ define i32 @test_vector_reduce_smax_v16i32(<16 x i32> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max3_i32 v1, v1, v9, v5
; GFX12-SDAG-NEXT: v_max3_i32 v2, v2, v10, v6
; GFX12-SDAG-NEXT: v_max_i32_e32 v4, v4, v12
; GFX12-SDAG-NEXT: v_max_i32_e32 v0, v0, v8
; GFX12-SDAG-NEXT: v_max3_i32 v3, v3, v11, v7
-; GFX12-SDAG-NEXT: v_max_i32_e32 v1, v1, v13
+; GFX12-SDAG-NEXT: v_max3_i32 v1, v1, v9, v5
; GFX12-SDAG-NEXT: v_max_i32_e32 v2, v2, v14
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_max3_i32 v1, v1, v3, v15
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-SDAG-NEXT: v_max_i32_e32 v3, v3, v15
+; GFX12-SDAG-NEXT: v_max_i32_e32 v1, v1, v13
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_max3_i32 v0, v0, v4, v2
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_i32_e32 v0, v0, v1
+; GFX12-SDAG-NEXT: v_max3_i32 v0, v0, v1, v3
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_smax_v16i32:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
index 98283c8307890..2107f2d6dd587 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
@@ -2934,15 +2934,15 @@ define i32 @test_vector_reduce_smin_v16i32(<16 x i32> %v) {
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT: v_min3_i32 v2, v2, v10, v6
-; GFX7-SDAG-NEXT: v_min3_i32 v1, v1, v9, v5
; GFX7-SDAG-NEXT: v_min_i32_e32 v4, v4, v12
; GFX7-SDAG-NEXT: v_min_i32_e32 v0, v0, v8
-; GFX7-SDAG-NEXT: v_min_i32_e32 v2, v2, v14
; GFX7-SDAG-NEXT: v_min3_i32 v3, v3, v11, v7
+; GFX7-SDAG-NEXT: v_min3_i32 v1, v1, v9, v5
+; GFX7-SDAG-NEXT: v_min_i32_e32 v2, v2, v14
+; GFX7-SDAG-NEXT: v_min_i32_e32 v3, v3, v15
; GFX7-SDAG-NEXT: v_min_i32_e32 v1, v1, v13
-; GFX7-SDAG-NEXT: v_min3_i32 v1, v1, v3, v15
; GFX7-SDAG-NEXT: v_min3_i32 v0, v0, v4, v2
-; GFX7-SDAG-NEXT: v_min_i32_e32 v0, v0, v1
+; GFX7-SDAG-NEXT: v_min3_i32 v0, v0, v1, v3
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_smin_v16i32:
@@ -2969,15 +2969,15 @@ define i32 @test_vector_reduce_smin_v16i32(<16 x i32> %v) {
; GFX8-SDAG: ; %bb.0: ; %entry
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: v_min3_i32 v2, v2, v10, v6
-; GFX8-SDAG-NEXT: v_min3_i32 v1, v1, v9, v5
; GFX8-SDAG-NEXT: v_min_i32_e32 v4, v4, v12
; GFX8-SDAG-NEXT: v_min_i32_e32 v0, v0, v8
-; GFX8-SDAG-NEXT: v_min_i32_e32 v2, v2, v14
; GFX8-SDAG-NEXT: v_min3_i32 v3, v3, v11, v7
+; GFX8-SDAG-NEXT: v_min3_i32 v1, v1, v9, v5
+; GFX8-SDAG-NEXT: v_min_i32_e32 v2, v2, v14
+; GFX8-SDAG-NEXT: v_min_i32_e32 v3, v3, v15
; GFX8-SDAG-NEXT: v_min_i32_e32 v1, v1, v13
-; GFX8-SDAG-NEXT: v_min3_i32 v1, v1, v3, v15
; GFX8-SDAG-NEXT: v_min3_i32 v0, v0, v4, v2
-; GFX8-SDAG-NEXT: v_min_i32_e32 v0, v0, v1
+; GFX8-SDAG-NEXT: v_min3_i32 v0, v0, v1, v3
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: test_vector_reduce_smin_v16i32:
@@ -3004,15 +3004,15 @@ define i32 @test_vector_reduce_smin_v16i32(<16 x i32> %v) {
; GFX9-SDAG: ; %bb.0: ; %entry
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: v_min3_i32 v2, v2, v10, v6
-; GFX9-SDAG-NEXT: v_min3_i32 v1, v1, v9, v5
; GFX9-SDAG-NEXT: v_min_i32_e32 v4, v4, v12
; GFX9-SDAG-NEXT: v_min_i32_e32 v0, v0, v8
-; GFX9-SDAG-NEXT: v_min_i32_e32 v2, v2, v14
; GFX9-SDAG-NEXT: v_min3_i32 v3, v3, v11, v7
+; GFX9-SDAG-NEXT: v_min3_i32 v1, v1, v9, v5
+; GFX9-SDAG-NEXT: v_min_i32_e32 v2, v2, v14
+; GFX9-SDAG-NEXT: v_min_i32_e32 v3, v3, v15
; GFX9-SDAG-NEXT: v_min_i32_e32 v1, v1, v13
-; GFX9-SDAG-NEXT: v_min3_i32 v1, v1, v3, v15
; GFX9-SDAG-NEXT: v_min3_i32 v0, v0, v4, v2
-; GFX9-SDAG-NEXT: v_min_i32_e32 v0, v0, v1
+; GFX9-SDAG-NEXT: v_min3_i32 v0, v0, v1, v3
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: test_vector_reduce_smin_v16i32:
@@ -3038,16 +3038,16 @@ define i32 @test_vector_reduce_smin_v16i32(<16 x i32> %v) {
; GFX10-SDAG-LABEL: test_vector_reduce_smin_v16i32:
; GFX10-SDAG: ; %bb.0: ; %entry
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_min3_i32 v1, v1, v9, v5
; GFX10-SDAG-NEXT: v_min3_i32 v2, v2, v10, v6
; GFX10-SDAG-NEXT: v_min_i32_e32 v4, v4, v12
; GFX10-SDAG-NEXT: v_min_i32_e32 v0, v0, v8
; GFX10-SDAG-NEXT: v_min3_i32 v3, v3, v11, v7
-; GFX10-SDAG-NEXT: v_min_i32_e32 v1, v1, v13
+; GFX10-SDAG-NEXT: v_min3_i32 v1, v1, v9, v5
; GFX10-SDAG-NEXT: v_min_i32_e32 v2, v2, v14
-; GFX10-SDAG-NEXT: v_min3_i32 v1, v1, v3, v15
+; GFX10-SDAG-NEXT: v_min_i32_e32 v3, v3, v15
+; GFX10-SDAG-NEXT: v_min_i32_e32 v1, v1, v13
; GFX10-SDAG-NEXT: v_min3_i32 v0, v0, v4, v2
-; GFX10-SDAG-NEXT: v_min_i32_e32 v0, v0, v1
+; GFX10-SDAG-NEXT: v_min3_i32 v0, v0, v1, v3
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: test_vector_reduce_smin_v16i32:
@@ -3073,18 +3073,18 @@ define i32 @test_vector_reduce_smin_v16i32(<16 x i32> %v) {
; GFX11-SDAG-LABEL: test_vector_reduce_smin_v16i32:
; GFX11-SDAG: ; %bb.0: ; %entry
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_min3_i32 v1, v1, v9, v5
; GFX11-SDAG-NEXT: v_min3_i32 v2, v2, v10, v6
; GFX11-SDAG-NEXT: v_min_i32_e32 v4, v4, v12
; GFX11-SDAG-NEXT: v_min_i32_e32 v0, v0, v8
; GFX11-SDAG-NEXT: v_min3_i32 v3, v3, v11, v7
-; GFX11-SDAG-NEXT: v_min_i32_e32 v1, v1, v13
+; GFX11-SDAG-NEXT: v_min3_i32 v1, v1, v9, v5
; GFX11-SDAG-NEXT: v_min_i32_e32 v2, v2, v14
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_min3_i32 v1, v1, v3, v15
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-SDAG-NEXT: v_min_i32_e32 v3, v3, v15
+; GFX11-SDAG-NEXT: v_min_i32_e32 v1, v1, v13
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_min3_i32 v0, v0, v4, v2
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_min_i32_e32 v0, v0, v1
+; GFX11-SDAG-NEXT: v_min3_i32 v0, v0, v1, v3
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: test_vector_reduce_smin_v16i32:
@@ -3118,18 +3118,18 @@ define i32 @test_vector_reduce_smin_v16i32(<16 x i32> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_min3_i32 v1, v1, v9, v5
; GFX12-SDAG-NEXT: v_min3_i32 v2, v2, v10, v6
; GFX12-SDAG-NEXT: v_min_i32_e32 v4, v4, v12
; GFX12-SDAG-NEXT: v_min_i32_e32 v0, v0, v8
; GFX12-SDAG-NEXT: v_min3_i32 v3, v3, v11, v7
-; GFX12-SDAG-NEXT: v_min_i32_e32 v1, v1, v13
+; GFX12-SDAG-NEXT: v_min3_i32 v1, v1, v9, v5
; GFX12-SDAG-NEXT: v_min_i32_e32 v2, v2, v14
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_min3_i32 v1, v1, v3, v15
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-SDAG-NEXT: v_min_i32_e32 v3, v3, v15
+; GFX12-SDAG-NEXT: v_min_i32_e32 v1, v1, v13
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_min3_i32 v0, v0, v4, v2
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_i32_e32 v0, v0, v1
+; GFX12-SDAG-NEXT: v_min3_i32 v0, v0, v1, v3
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_smin_v16i32:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
index 4a6d9e2e0689c..78a8ec8d408d0 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
@@ -2810,15 +2810,15 @@ define i32 @test_vector_reduce_umax_v16i32(<16 x i32> %v) {
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT: v_max3_u32 v2, v2, v10, v6
-; GFX7-SDAG-NEXT: v_max3_u32 v1, v1, v9, v5
; GFX7-SDAG-NEXT: v_max_u32_e32 v4, v4, v12
; GFX7-SDAG-NEXT: v_max_u32_e32 v0, v0, v8
-; GFX7-SDAG-NEXT: v_max_u32_e32 v2, v2, v14
; GFX7-SDAG-NEXT: v_max3_u32 v3, v3, v11, v7
+; GFX7-SDAG-NEXT: v_max3_u32 v1, v1, v9, v5
+; GFX7-SDAG-NEXT: v_max_u32_e32 v2, v2, v14
+; GFX7-SDAG-NEXT: v_max_u32_e32 v3, v3, v15
; GFX7-SDAG-NEXT: v_max_u32_e32 v1, v1, v13
-; GFX7-SDAG-NEXT: v_max3_u32 v1, v1, v3, v15
; GFX7-SDAG-NEXT: v_max3_u32 v0, v0, v4, v2
-; GFX7-SDAG-NEXT: v_max_u32_e32 v0, v0, v1
+; GFX7-SDAG-NEXT: v_max3_u32 v0, v0, v1, v3
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_umax_v16i32:
@@ -2845,15 +2845,15 @@ define i32 @test_vector_reduce_umax_v16i32(<16 x i32> %v) {
; GFX8-SDAG: ; %bb.0: ; %entry
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: v_max3_u32 v2, v2, v10, v6
-; GFX8-SDAG-NEXT: v_max3_u32 v1, v1, v9, v5
; GFX8-SDAG-NEXT: v_max_u32_e32 v4, v4, v12
; GFX8-SDAG-NEXT: v_max_u32_e32 v0, v0, v8
-; GFX8-SDAG-NEXT: v_max_u32_e32 v2, v2, v14
; GFX8-SDAG-NEXT: v_max3_u32 v3, v3, v11, v7
+; GFX8-SDAG-NEXT: v_max3_u32 v1, v1, v9, v5
+; GFX8-SDAG-NEXT: v_max_u32_e32 v2, v2, v14
+; GFX8-SDAG-NEXT: v_max_u32_e32 v3, v3, v15
; GFX8-SDAG-NEXT: v_max_u32_e32 v1, v1, v13
-; GFX8-SDAG-NEXT: v_max3_u32 v1, v1, v3, v15
; GFX8-SDAG-NEXT: v_max3_u32 v0, v0, v4, v2
-; GFX8-SDAG-NEXT: v_max_u32_e32 v0, v0, v1
+; GFX8-SDAG-NEXT: v_max3_u32 v0, v0, v1, v3
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: test_vector_reduce_umax_v16i32:
@@ -2880,15 +2880,15 @@ define i32 @test_vector_reduce_umax_v16i32(<16 x i32> %v) {
; GFX9-SDAG: ; %bb.0: ; %entry
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: v_max3_u32 v2, v2, v10, v6
-; GFX9-SDAG-NEXT: v_max3_u32 v1, v1, v9, v5
; GFX9-SDAG-NEXT: v_max_u32_e32 v4, v4, v12
; GFX9-SDAG-NEXT: v_max_u32_e32 v0, v0, v8
-; GFX9-SDAG-NEXT: v_max_u32_e32 v2, v2, v14
; GFX9-SDAG-NEXT: v_max3_u32 v3, v3, v11, v7
+; GFX9-SDAG-NEXT: v_max3_u32 v1, v1, v9, v5
+; GFX9-SDAG-NEXT: v_max_u32_e32 v2, v2, v14
+; GFX9-SDAG-NEXT: v_max_u32_e32 v3, v3, v15
; GFX9-SDAG-NEXT: v_max_u32_e32 v1, v1, v13
-; GFX9-SDAG-NEXT: v_max3_u32 v1, v1, v3, v15
; GFX9-SDAG-NEXT: v_max3_u32 v0, v0, v4, v2
-; GFX9-SDAG-NEXT: v_max_u32_e32 v0, v0, v1
+; GFX9-SDAG-NEXT: v_max3_u32 v0, v0, v1, v3
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: test_vector_reduce_umax_v16i32:
@@ -2914,16 +2914,16 @@ define i32 @test_vector_reduce_umax_v16i32(<16 x i32> %v) {
; GFX10-SDAG-LABEL: test_vector_reduce_umax_v16i32:
; GFX10-SDAG: ; %bb.0: ; %entry
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_max3_u32 v1, v1, v9, v5
; GFX10-SDAG-NEXT: v_max3_u32 v2, v2, v10, v6
; GFX10-SDAG-NEXT: v_max_u32_e32 v4, v4, v12
; GFX10-SDAG-NEXT: v_max_u32_e32 v0, v0, v8
; GFX10-SDAG-NEXT: v_max3_u32 v3, v3, v11, v7
-; GFX10-SDAG-NEXT: v_max_u32_e32 v1, v1, v13
+; GFX10-SDAG-NEXT: v_max3_u32 v1, v1, v9, v5
; GFX10-SDAG-NEXT: v_max_u32_e32 v2, v2, v14
-; GFX10-SDAG-NEXT: v_max3_u32 v1, v1, v3, v15
+; GFX10-SDAG-NEXT: v_max_u32_e32 v3, v3, v15
+; GFX10-SDAG-NEXT: v_max_u32_e32 v1, v1, v13
; GFX10-SDAG-NEXT: v_max3_u32 v0, v0, v4, v2
-; GFX10-SDAG-NEXT: v_max_u32_e32 v0, v0, v1
+; GFX10-SDAG-NEXT: v_max3_u32 v0, v0, v1, v3
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: test_vector_reduce_umax_v16i32:
@@ -2949,18 +2949,18 @@ define i32 @test_vector_reduce_umax_v16i32(<16 x i32> %v) {
; GFX11-SDAG-LABEL: test_vector_reduce_umax_v16i32:
; GFX11-SDAG: ; %bb.0: ; %entry
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_max3_u32 v1, v1, v9, v5
; GFX11-SDAG-NEXT: v_max3_u32 v2, v2, v10, v6
; GFX11-SDAG-NEXT: v_max_u32_e32 v4, v4, v12
; GFX11-SDAG-NEXT: v_max_u32_e32 v0, v0, v8
; GFX11-SDAG-NEXT: v_max3_u32 v3, v3, v11, v7
-; GFX11-SDAG-NEXT: v_max_u32_e32 v1, v1, v13
+; GFX11-SDAG-NEXT: v_max3_u32 v1, v1, v9, v5
; GFX11-SDAG-NEXT: v_max_u32_e32 v2, v2, v14
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_max3_u32 v1, v1, v3, v15
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-SDAG-NEXT: v_max_u32_e32 v3, v3, v15
+; GFX11-SDAG-NEXT: v_max_u32_e32 v1, v1, v13
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_max3_u32 v0, v0, v4, v2
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_max_u32_e32 v0, v0, v1
+; GFX11-SDAG-NEXT: v_max3_u32 v0, v0, v1, v3
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: test_vector_reduce_umax_v16i32:
@@ -2994,18 +2994,18 @@ define i32 @test_vector_reduce_umax_v16i32(<16 x i32> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_max3_u32 v1, v1, v9, v5
; GFX12-SDAG-NEXT: v_max3_u32 v2, v2, v10, v6
; GFX12-SDAG-NEXT: v_max_u32_e32 v4, v4, v12
; GFX12-SDAG-NEXT: v_max_u32_e32 v0, v0, v8
; GFX12-SDAG-NEXT: v_max3_u32 v3, v3, v11, v7
-; GFX12-SDAG-NEXT: v_max_u32_e32 v1, v1, v13
+; GFX12-SDAG-NEXT: v_max3_u32 v1, v1, v9, v5
; GFX12-SDAG-NEXT: v_max_u32_e32 v2, v2, v14
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_max3_u32 v1, v1, v3, v15
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-SDAG-NEXT: v_max_u32_e32 v3, v3, v15
+; GFX12-SDAG-NEXT: v_max_u32_e32 v1, v1, v13
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_max3_u32 v0, v0, v4, v2
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_u32_e32 v0, v0, v1
+; GFX12-SDAG-NEXT: v_max3_u32 v0, v0, v1, v3
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_umax_v16i32:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
index 49c9145dad075..5b2c1c3134acd 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
@@ -2541,15 +2541,15 @@ define i32 @test_vector_reduce_umin_v16i32(<16 x i32> %v) {
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT: v_min3_u32 v2, v2, v10, v6
-; GFX7-SDAG-NEXT: v_min3_u32 v1, v1, v9, v5
; GFX7-SDAG-NEXT: v_min_u32_e32 v4, v4, v12
; GFX7-SDAG-NEXT: v_min_u32_e32 v0, v0, v8
-; GFX7-SDAG-NEXT: v_min_u32_e32 v2, v2, v14
; GFX7-SDAG-NEXT: v_min3_u32 v3, v3, v11, v7
+; GFX7-SDAG-NEXT: v_min3_u32 v1, v1, v9, v5
+; GFX7-SDAG-NEXT: v_min_u32_e32 v2, v2, v14
+; GFX7-SDAG-NEXT: v_min_u32_e32 v3, v3, v15
; GFX7-SDAG-NEXT: v_min_u32_e32 v1, v1, v13
-; GFX7-SDAG-NEXT: v_min3_u32 v1, v1, v3, v15
; GFX7-SDAG-NEXT: v_min3_u32 v0, v0, v4, v2
-; GFX7-SDAG-NEXT: v_min_u32_e32 v0, v0, v1
+; GFX7-SDAG-NEXT: v_min3_u32 v0, v0, v1, v3
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_umin_v16i32:
@@ -2576,15 +2576,15 @@ define i32 @test_vector_reduce_umin_v16i32(<16 x i32> %v) {
; GFX8-SDAG: ; %bb.0: ; %entry
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: v_min3_u32 v2, v2, v10, v6
-; GFX8-SDAG-NEXT: v_min3_u32 v1, v1, v9, v5
; GFX8-SDAG-NEXT: v_min_u32_e32 v4, v4, v12
; GFX8-SDAG-NEXT: v_min_u32_e32 v0, v0, v8
-; GFX8-SDAG-NEXT: v_min_u32_e32 v2, v2, v14
; GFX8-SDAG-NEXT: v_min3_u32 v3, v3, v11, v7
+; GFX8-SDAG-NEXT: v_min3_u32 v1, v1, v9, v5
+; GFX8-SDAG-NEXT: v_min_u32_e32 v2, v2, v14
+; GFX8-SDAG-NEXT: v_min_u32_e32 v3, v3, v15
; GFX8-SDAG-NEXT: v_min_u32_e32 v1, v1, v13
-; GFX8-SDAG-NEXT: v_min3_u32 v1, v1, v3, v15
; GFX8-SDAG-NEXT: v_min3_u32 v0, v0, v4, v2
-; GFX8-SDAG-NEXT: v_min_u32_e32 v0, v0, v1
+; GFX8-SDAG-NEXT: v_min3_u32 v0, v0, v1, v3
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: test_vector_reduce_umin_v16i32:
@@ -2611,15 +2611,15 @@ define i32 @test_vector_reduce_umin_v16i32(<16 x i32> %v) {
; GFX9-SDAG: ; %bb.0: ; %entry
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: v_min3_u32 v2, v2, v10, v6
-; GFX9-SDAG-NEXT: v_min3_u32 v1, v1, v9, v5
; GFX9-SDAG-NEXT: v_min_u32_e32 v4, v4, v12
; GFX9-SDAG-NEXT: v_min_u32_e32 v0, v0, v8
-; GFX9-SDAG-NEXT: v_min_u32_e32 v2, v2, v14
; GFX9-SDAG-NEXT: v_min3_u32 v3, v3, v11, v7
+; GFX9-SDAG-NEXT: v_min3_u32 v1, v1, v9, v5
+; GFX9-SDAG-NEXT: v_min_u32_e32 v2, v2, v14
+; GFX9-SDAG-NEXT: v_min_u32_e32 v3, v3, v15
; GFX9-SDAG-NEXT: v_min_u32_e32 v1, v1, v13
-; GFX9-SDAG-NEXT: v_min3_u32 v1, v1, v3, v15
; GFX9-SDAG-NEXT: v_min3_u32 v0, v0, v4, v2
-; GFX9-SDAG-NEXT: v_min_u32_e32 v0, v0, v1
+; GFX9-SDAG-NEXT: v_min3_u32 v0, v0, v1, v3
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: test_vector_reduce_umin_v16i32:
@@ -2645,16 +2645,16 @@ define i32 @test_vector_reduce_umin_v16i32(<16 x i32> %v) {
; GFX10-SDAG-LABEL: test_vector_reduce_umin_v16i32:
; GFX10-SDAG: ; %bb.0: ; %entry
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_min3_u32 v1, v1, v9, v5
; GFX10-SDAG-NEXT: v_min3_u32 v2, v2, v10, v6
; GFX10-SDAG-NEXT: v_min_u32_e32 v4, v4, v12
; GFX10-SDAG-NEXT: v_min_u32_e32 v0, v0, v8
; GFX10-SDAG-NEXT: v_min3_u32 v3, v3, v11, v7
-; GFX10-SDAG-NEXT: v_min_u32_e32 v1, v1, v13
+; GFX10-SDAG-NEXT: v_min3_u32 v1, v1, v9, v5
; GFX10-SDAG-NEXT: v_min_u32_e32 v2, v2, v14
-; GFX10-SDAG-NEXT: v_min3_u32 v1, v1, v3, v15
+; GFX10-SDAG-NEXT: v_min_u32_e32 v3, v3, v15
+; GFX10-SDAG-NEXT: v_min_u32_e32 v1, v1, v13
; GFX10-SDAG-NEXT: v_min3_u32 v0, v0, v4, v2
-; GFX10-SDAG-NEXT: v_min_u32_e32 v0, v0, v1
+; GFX10-SDAG-NEXT: v_min3_u32 v0, v0, v1, v3
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: test_vector_reduce_umin_v16i32:
@@ -2680,18 +2680,18 @@ define i32 @test_vector_reduce_umin_v16i32(<16 x i32> %v) {
; GFX11-SDAG-LABEL: test_vector_reduce_umin_v16i32:
; GFX11-SDAG: ; %bb.0: ; %entry
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_min3_u32 v1, v1, v9, v5
; GFX11-SDAG-NEXT: v_min3_u32 v2, v2, v10, v6
; GFX11-SDAG-NEXT: v_min_u32_e32 v4, v4, v12
; GFX11-SDAG-NEXT: v_min_u32_e32 v0, v0, v8
; GFX11-SDAG-NEXT: v_min3_u32 v3, v3, v11, v7
-; GFX11-SDAG-NEXT: v_min_u32_e32 v1, v1, v13
+; GFX11-SDAG-NEXT: v_min3_u32 v1, v1, v9, v5
; GFX11-SDAG-NEXT: v_min_u32_e32 v2, v2, v14
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_min3_u32 v1, v1, v3, v15
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-SDAG-NEXT: v_min_u32_e32 v3, v3, v15
+; GFX11-SDAG-NEXT: v_min_u32_e32 v1, v1, v13
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_min3_u32 v0, v0, v4, v2
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_min_u32_e32 v0, v0, v1
+; GFX11-SDAG-NEXT: v_min3_u32 v0, v0, v1, v3
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: test_vector_reduce_umin_v16i32:
@@ -2725,18 +2725,18 @@ define i32 @test_vector_reduce_umin_v16i32(<16 x i32> %v) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_min3_u32 v1, v1, v9, v5
; GFX12-SDAG-NEXT: v_min3_u32 v2, v2, v10, v6
; GFX12-SDAG-NEXT: v_min_u32_e32 v4, v4, v12
; GFX12-SDAG-NEXT: v_min_u32_e32 v0, v0, v8
; GFX12-SDAG-NEXT: v_min3_u32 v3, v3, v11, v7
-; GFX12-SDAG-NEXT: v_min_u32_e32 v1, v1, v13
+; GFX12-SDAG-NEXT: v_min3_u32 v1, v1, v9, v5
; GFX12-SDAG-NEXT: v_min_u32_e32 v2, v2, v14
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_min3_u32 v1, v1, v3, v15
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-SDAG-NEXT: v_min_u32_e32 v3, v3, v15
+; GFX12-SDAG-NEXT: v_min_u32_e32 v1, v1, v13
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_min3_u32 v0, v0, v4, v2
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_u32_e32 v0, v0, v1
+; GFX12-SDAG-NEXT: v_min3_u32 v0, v0, v1, v3
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_umin_v16i32:
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