[llvm] [AMDGPU] Waterfall loop codegen improvement in SIInstrInfo (PR #192415)

[Matt Arsenault via llvm-commits]

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@@ -7119,21 +7140,27 @@ emitLoadScalarOpsFromVGPRLoop(const SIInstrInfo &TII,
       BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), CurReg)
           .addReg(VScalarOp);
 
-      Register NewCondReg = MRI.createVirtualRegister(BoolXExecRC);
+      if (UseNewExecInstructions) {
+        BuildMI(LoopBB, I, DL, TII.get(LMC.CmpXEqU32Opc))
+            .addReg(CurReg)
+            .addReg(VScalarOp);
+      } else {
+        Register NewCondReg = MRI.createVirtualRegister(BoolXExecRC);
 
-      BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_CMP_EQ_U32_e64), NewCondReg)
-          .addReg(CurReg)
-          .addReg(VScalarOp);
+        BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_CMP_EQ_U32_e64), NewCondReg)
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arsenm wrote:

Are these introduced tabs? 

https://github.com/llvm/llvm-project/pull/192415