[llvm] [AArch64][GlobalISel] Lower unmerge to extract_subvector (PR #195046)

[Matt Arsenault via llvm-commits]

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@@ -7862,6 +7862,15 @@ AArch64InstructionSelector::selectExtractHigh(MachineOperand &Root) const {
       return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }}};
     }
   }
+  if (Extract->MI->getOpcode() == TargetOpcode::G_EXTRACT_SUBVECTOR &&
+      Extract->MI->getNumOperands() == 3) {
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arsenm wrote:

The operand count can't be different 

https://github.com/llvm/llvm-project/pull/195046