[llvm] [DAG] Support soft half promotion of insert_vector_elt (PR #194994)

[Matt Arsenault via llvm-commits]

================
@@ -0,0 +1,107 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
----------------
arsenm wrote:

Don't need all the -verify-machineinstrs

https://github.com/llvm/llvm-project/pull/194994