[llvm] [AArch64][GlobalISel] Normalize and cleanup some test checks. NFC (PR #195016)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 29 23:35:33 PDT 2026
https://github.com/davemgreen created https://github.com/llvm/llvm-project/pull/195016
None
>From a4e1fb33f63099467a01b5ee11751d9a575952eb Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Thu, 30 Apr 2026 07:35:21 +0100
Subject: [PATCH] [AArch64][GlobalISel] Normalize and cleanup some test checks.
NFC
---
llvm/test/CodeGen/AArch64/adc.ll | 73 +--
.../AArch64/arm64-extract-insert-varidx.ll | 524 +++++++++---------
.../AArch64/arm64-extract_subvector.ll | 7 +-
llvm/test/CodeGen/AArch64/fcmp-fp128.ll | 6 +-
llvm/test/CodeGen/AArch64/shift-logic.ll | 281 +++++-----
llvm/test/CodeGen/AArch64/trunc-avg-fold.ll | 7 +-
6 files changed, 432 insertions(+), 466 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/adc.ll b/llvm/test/CodeGen/AArch64/adc.ll
index 03f3cf192102d..df092bfa2f9ba 100644
--- a/llvm/test/CodeGen/AArch64/adc.ll
+++ b/llvm/test/CodeGen/AArch64/adc.ll
@@ -1,16 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-apple-ios7.0 | FileCheck --check-prefixes=CHECK-LE %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-apple-ios7.0 | FileCheck --check-prefixes=CHECK,CHECK-LE %s
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64_be-none-linux-gnu | FileCheck --check-prefixes=CHECK-BE %s
-; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-apple-ios7.0 -global-isel | FileCheck --check-prefixes=CHECK-GI %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-apple-ios7.0 -global-isel | FileCheck --check-prefixes=CHECK,CHECK-GI %s
define i128 @test_simple(i128 %a, i128 %b, i128 %c) {
-; CHECK-LE-LABEL: test_simple:
-; CHECK-LE: ; %bb.0:
-; CHECK-LE-NEXT: adds x8, x0, x2
-; CHECK-LE-NEXT: adc x9, x1, x3
-; CHECK-LE-NEXT: subs x0, x8, x4
-; CHECK-LE-NEXT: sbc x1, x9, x5
-; CHECK-LE-NEXT: ret
+; CHECK-LABEL: test_simple:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: adds x8, x0, x2
+; CHECK-NEXT: adc x9, x1, x3
+; CHECK-NEXT: subs x0, x8, x4
+; CHECK-NEXT: sbc x1, x9, x5
+; CHECK-NEXT: ret
;
; CHECK-BE-LABEL: test_simple:
; CHECK-BE: // %bb.0:
@@ -19,14 +19,6 @@ define i128 @test_simple(i128 %a, i128 %b, i128 %c) {
; CHECK-BE-NEXT: subs x1, x8, x5
; CHECK-BE-NEXT: sbc x0, x9, x4
; CHECK-BE-NEXT: ret
-;
-; CHECK-GI-LABEL: test_simple:
-; CHECK-GI: ; %bb.0:
-; CHECK-GI-NEXT: adds x8, x0, x2
-; CHECK-GI-NEXT: adc x9, x1, x3
-; CHECK-GI-NEXT: subs x0, x8, x4
-; CHECK-GI-NEXT: sbc x1, x9, x5
-; CHECK-GI-NEXT: ret
%valadd = add i128 %a, %b
%valsub = sub i128 %valadd, %c
ret i128 %valsub
@@ -55,12 +47,12 @@ define i128 @test_imm(i128 %a) {
}
define i128 @test_shifted(i128 %a, i128 %b) {
-; CHECK-LE-LABEL: test_shifted:
-; CHECK-LE: ; %bb.0:
-; CHECK-LE-NEXT: extr x8, x3, x2, #19
-; CHECK-LE-NEXT: adds x0, x0, x2, lsl #45
-; CHECK-LE-NEXT: adc x1, x1, x8
-; CHECK-LE-NEXT: ret
+; CHECK-LABEL: test_shifted:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: extr x8, x3, x2, #19
+; CHECK-NEXT: adds x0, x0, x2, lsl #45
+; CHECK-NEXT: adc x1, x1, x8
+; CHECK-NEXT: ret
;
; CHECK-BE-LABEL: test_shifted:
; CHECK-BE: // %bb.0:
@@ -68,28 +60,21 @@ define i128 @test_shifted(i128 %a, i128 %b) {
; CHECK-BE-NEXT: adds x1, x1, x3, lsl #45
; CHECK-BE-NEXT: adc x0, x0, x8
; CHECK-BE-NEXT: ret
-;
-; CHECK-GI-LABEL: test_shifted:
-; CHECK-GI: ; %bb.0:
-; CHECK-GI-NEXT: extr x8, x3, x2, #19
-; CHECK-GI-NEXT: adds x0, x0, x2, lsl #45
-; CHECK-GI-NEXT: adc x1, x1, x8
-; CHECK-GI-NEXT: ret
%rhs = shl i128 %b, 45
%val = add i128 %a, %rhs
ret i128 %val
}
define i128 @test_extended(i128 %a, i16 %b) {
-; CHECK-LE-LABEL: test_extended:
-; CHECK-LE: ; %bb.0:
-; CHECK-LE-NEXT: ; kill: def $w2 killed $w2 def $x2
-; CHECK-LE-NEXT: sxth x8, w2
-; CHECK-LE-NEXT: adds x0, x0, w2, sxth #3
-; CHECK-LE-NEXT: asr x9, x8, #63
-; CHECK-LE-NEXT: extr x8, x9, x8, #61
-; CHECK-LE-NEXT: adc x1, x1, x8
-; CHECK-LE-NEXT: ret
+; CHECK-LABEL: test_extended:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ; kill: def $w2 killed $w2 def $x2
+; CHECK-NEXT: sxth x8, w2
+; CHECK-NEXT: adds x0, x0, w2, sxth #3
+; CHECK-NEXT: asr x9, x8, #63
+; CHECK-NEXT: extr x8, x9, x8, #61
+; CHECK-NEXT: adc x1, x1, x8
+; CHECK-NEXT: ret
;
; CHECK-BE-LABEL: test_extended:
; CHECK-BE: // %bb.0:
@@ -100,16 +85,6 @@ define i128 @test_extended(i128 %a, i16 %b) {
; CHECK-BE-NEXT: extr x8, x9, x8, #61
; CHECK-BE-NEXT: adc x0, x0, x8
; CHECK-BE-NEXT: ret
-;
-; CHECK-GI-LABEL: test_extended:
-; CHECK-GI: ; %bb.0:
-; CHECK-GI-NEXT: ; kill: def $w2 killed $w2 def $x2
-; CHECK-GI-NEXT: sxth x8, w2
-; CHECK-GI-NEXT: adds x0, x0, w2, sxth #3
-; CHECK-GI-NEXT: asr x9, x8, #63
-; CHECK-GI-NEXT: extr x8, x9, x8, #61
-; CHECK-GI-NEXT: adc x1, x1, x8
-; CHECK-GI-NEXT: ret
%ext = sext i16 %b to i128
%rhs = shl i128 %ext, 3
%val = add i128 %a, %rhs
diff --git a/llvm/test/CodeGen/AArch64/arm64-extract-insert-varidx.ll b/llvm/test/CodeGen/AArch64/arm64-extract-insert-varidx.ll
index 69b30108ed534..8db13306d92d5 100644
--- a/llvm/test/CodeGen/AArch64/arm64-extract-insert-varidx.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-extract-insert-varidx.ll
@@ -1,50 +1,50 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
-; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast -aarch64-enable-sink-fold=true | FileCheck %s --check-prefix=CHECK-SDAG
-; RUN: llc < %s -global-isel -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast -aarch64-enable-sink-fold=true | FileCheck %s --check-prefix=CHECK-GISEL
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast -aarch64-enable-sink-fold=true | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -global-isel -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast -aarch64-enable-sink-fold=true | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define <4 x i8> @test_varidx_extract_v8s8(<8 x i8> %x, i32 %idx) {
-; CHECK-SDAG-LABEL: test_varidx_extract_v8s8:
-; CHECK-SDAG: // %bb.0:
-; CHECK-SDAG-NEXT: sub sp, sp, #16
-; CHECK-SDAG-NEXT: .cfi_def_cfa_offset 16
-; CHECK-SDAG-NEXT: add x8, sp, #8
-; CHECK-SDAG-NEXT: // kill: def $w0 killed $w0 def $x0
-; CHECK-SDAG-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SDAG-NEXT: str d0, [sp, #8]
-; CHECK-SDAG-NEXT: bfxil x8, x0, #0, #3
-; CHECK-SDAG-NEXT: ld1 { v1.b }[0], [x8]
-; CHECK-SDAG-NEXT: mov v1.b[2], v0.b[1]
-; CHECK-SDAG-NEXT: mov v1.b[4], v0.b[2]
-; CHECK-SDAG-NEXT: mov v1.b[6], v0.b[3]
-; CHECK-SDAG-NEXT: fmov d0, d1
-; CHECK-SDAG-NEXT: add sp, sp, #16
-; CHECK-SDAG-NEXT: ret
+; CHECK-SD-LABEL: test_varidx_extract_v8s8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sub sp, sp, #16
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
+; CHECK-SD-NEXT: add x8, sp, #8
+; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: str d0, [sp, #8]
+; CHECK-SD-NEXT: bfxil x8, x0, #0, #3
+; CHECK-SD-NEXT: ld1 { v1.b }[0], [x8]
+; CHECK-SD-NEXT: mov v1.b[2], v0.b[1]
+; CHECK-SD-NEXT: mov v1.b[4], v0.b[2]
+; CHECK-SD-NEXT: mov v1.b[6], v0.b[3]
+; CHECK-SD-NEXT: fmov d0, d1
+; CHECK-SD-NEXT: add sp, sp, #16
+; CHECK-SD-NEXT: ret
;
-; CHECK-GISEL-LABEL: test_varidx_extract_v8s8:
-; CHECK-GISEL: // %bb.0:
-; CHECK-GISEL-NEXT: sub sp, sp, #16
-; CHECK-GISEL-NEXT: .cfi_def_cfa_offset 16
-; CHECK-GISEL-NEXT: mov w9, w0
-; CHECK-GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GISEL-NEXT: mov b1, v0.b[1]
-; CHECK-GISEL-NEXT: add x8, sp, #8
-; CHECK-GISEL-NEXT: and x9, x9, #0x7
-; CHECK-GISEL-NEXT: str d0, [sp, #8]
-; CHECK-GISEL-NEXT: mov b2, v0.b[2]
-; CHECK-GISEL-NEXT: lsl x10, x9, #1
-; CHECK-GISEL-NEXT: mov b0, v0.b[3]
-; CHECK-GISEL-NEXT: sub x9, x10, x9
-; CHECK-GISEL-NEXT: ldrb w8, [x8, x9]
-; CHECK-GISEL-NEXT: fmov w9, s1
-; CHECK-GISEL-NEXT: fmov s1, w8
-; CHECK-GISEL-NEXT: fmov w8, s2
-; CHECK-GISEL-NEXT: mov v1.h[1], w9
-; CHECK-GISEL-NEXT: mov v1.h[2], w8
-; CHECK-GISEL-NEXT: fmov w8, s0
-; CHECK-GISEL-NEXT: mov v1.h[3], w8
-; CHECK-GISEL-NEXT: fmov d0, d1
-; CHECK-GISEL-NEXT: add sp, sp, #16
-; CHECK-GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_varidx_extract_v8s8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #16
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
+; CHECK-GI-NEXT: mov w9, w0
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: mov b1, v0.b[1]
+; CHECK-GI-NEXT: add x8, sp, #8
+; CHECK-GI-NEXT: and x9, x9, #0x7
+; CHECK-GI-NEXT: str d0, [sp, #8]
+; CHECK-GI-NEXT: mov b2, v0.b[2]
+; CHECK-GI-NEXT: lsl x10, x9, #1
+; CHECK-GI-NEXT: mov b0, v0.b[3]
+; CHECK-GI-NEXT: sub x9, x10, x9
+; CHECK-GI-NEXT: ldrb w8, [x8, x9]
+; CHECK-GI-NEXT: fmov w9, s1
+; CHECK-GI-NEXT: fmov s1, w8
+; CHECK-GI-NEXT: fmov w8, s2
+; CHECK-GI-NEXT: mov v1.h[1], w9
+; CHECK-GI-NEXT: mov v1.h[2], w8
+; CHECK-GI-NEXT: fmov w8, s0
+; CHECK-GI-NEXT: mov v1.h[3], w8
+; CHECK-GI-NEXT: fmov d0, d1
+; CHECK-GI-NEXT: add sp, sp, #16
+; CHECK-GI-NEXT: ret
%tmp = extractelement <8 x i8> %x, i32 %idx
%tmp2 = insertelement <4 x i8> undef, i8 %tmp, i32 0
%tmp3 = extractelement <8 x i8> %x, i32 1
@@ -57,47 +57,47 @@ define <4 x i8> @test_varidx_extract_v8s8(<8 x i8> %x, i32 %idx) {
}
define <8 x i8> @test_varidx_extract_v16s8(<16 x i8> %x, i32 %idx) {
-; CHECK-SDAG-LABEL: test_varidx_extract_v16s8:
-; CHECK-SDAG: // %bb.0:
-; CHECK-SDAG-NEXT: sub sp, sp, #16
-; CHECK-SDAG-NEXT: .cfi_def_cfa_offset 16
-; CHECK-SDAG-NEXT: mov x8, sp
-; CHECK-SDAG-NEXT: // kill: def $w0 killed $w0 def $x0
-; CHECK-SDAG-NEXT: str q0, [sp]
-; CHECK-SDAG-NEXT: bfxil x8, x0, #0, #4
-; CHECK-SDAG-NEXT: ldr b1, [x8]
-; CHECK-SDAG-NEXT: mov v1.b[1], v0.b[1]
-; CHECK-SDAG-NEXT: mov v1.b[2], v0.b[2]
-; CHECK-SDAG-NEXT: mov v1.b[3], v0.b[3]
-; CHECK-SDAG-NEXT: mov v1.b[4], v0.b[4]
-; CHECK-SDAG-NEXT: mov v1.b[5], v0.b[5]
-; CHECK-SDAG-NEXT: mov v1.b[6], v0.b[6]
-; CHECK-SDAG-NEXT: mov v1.b[7], v0.b[7]
-; CHECK-SDAG-NEXT: fmov d0, d1
-; CHECK-SDAG-NEXT: add sp, sp, #16
-; CHECK-SDAG-NEXT: ret
+; CHECK-SD-LABEL: test_varidx_extract_v16s8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sub sp, sp, #16
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
+; CHECK-SD-NEXT: mov x8, sp
+; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-SD-NEXT: str q0, [sp]
+; CHECK-SD-NEXT: bfxil x8, x0, #0, #4
+; CHECK-SD-NEXT: ldr b1, [x8]
+; CHECK-SD-NEXT: mov v1.b[1], v0.b[1]
+; CHECK-SD-NEXT: mov v1.b[2], v0.b[2]
+; CHECK-SD-NEXT: mov v1.b[3], v0.b[3]
+; CHECK-SD-NEXT: mov v1.b[4], v0.b[4]
+; CHECK-SD-NEXT: mov v1.b[5], v0.b[5]
+; CHECK-SD-NEXT: mov v1.b[6], v0.b[6]
+; CHECK-SD-NEXT: mov v1.b[7], v0.b[7]
+; CHECK-SD-NEXT: fmov d0, d1
+; CHECK-SD-NEXT: add sp, sp, #16
+; CHECK-SD-NEXT: ret
;
-; CHECK-GISEL-LABEL: test_varidx_extract_v16s8:
-; CHECK-GISEL: // %bb.0:
-; CHECK-GISEL-NEXT: sub sp, sp, #16
-; CHECK-GISEL-NEXT: .cfi_def_cfa_offset 16
-; CHECK-GISEL-NEXT: mov w9, w0
-; CHECK-GISEL-NEXT: mov x8, sp
-; CHECK-GISEL-NEXT: str q0, [sp]
-; CHECK-GISEL-NEXT: and x9, x9, #0xf
-; CHECK-GISEL-NEXT: lsl x10, x9, #1
-; CHECK-GISEL-NEXT: sub x9, x10, x9
-; CHECK-GISEL-NEXT: ldr b1, [x8, x9]
-; CHECK-GISEL-NEXT: mov v1.b[1], v0.b[1]
-; CHECK-GISEL-NEXT: mov v1.b[2], v0.b[2]
-; CHECK-GISEL-NEXT: mov v1.b[3], v0.b[3]
-; CHECK-GISEL-NEXT: mov v1.b[4], v0.b[4]
-; CHECK-GISEL-NEXT: mov v1.b[5], v0.b[5]
-; CHECK-GISEL-NEXT: mov v1.b[6], v0.b[6]
-; CHECK-GISEL-NEXT: mov v1.b[7], v0.b[7]
-; CHECK-GISEL-NEXT: fmov d0, d1
-; CHECK-GISEL-NEXT: add sp, sp, #16
-; CHECK-GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_varidx_extract_v16s8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #16
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
+; CHECK-GI-NEXT: mov w9, w0
+; CHECK-GI-NEXT: mov x8, sp
+; CHECK-GI-NEXT: str q0, [sp]
+; CHECK-GI-NEXT: and x9, x9, #0xf
+; CHECK-GI-NEXT: lsl x10, x9, #1
+; CHECK-GI-NEXT: sub x9, x10, x9
+; CHECK-GI-NEXT: ldr b1, [x8, x9]
+; CHECK-GI-NEXT: mov v1.b[1], v0.b[1]
+; CHECK-GI-NEXT: mov v1.b[2], v0.b[2]
+; CHECK-GI-NEXT: mov v1.b[3], v0.b[3]
+; CHECK-GI-NEXT: mov v1.b[4], v0.b[4]
+; CHECK-GI-NEXT: mov v1.b[5], v0.b[5]
+; CHECK-GI-NEXT: mov v1.b[6], v0.b[6]
+; CHECK-GI-NEXT: mov v1.b[7], v0.b[7]
+; CHECK-GI-NEXT: fmov d0, d1
+; CHECK-GI-NEXT: add sp, sp, #16
+; CHECK-GI-NEXT: ret
%tmp = extractelement <16 x i8> %x, i32 %idx
%tmp2 = insertelement <8 x i8> undef, i8 %tmp, i32 0
%tmp3 = extractelement <16 x i8> %x, i32 1
@@ -118,69 +118,69 @@ define <8 x i8> @test_varidx_extract_v16s8(<16 x i8> %x, i32 %idx) {
}
define i16 @test_varidx_extract_v2s16(<2 x i16> %x, i32 %idx) {
-; CHECK-SDAG-LABEL: test_varidx_extract_v2s16:
-; CHECK-SDAG: // %bb.0:
-; CHECK-SDAG-NEXT: sub sp, sp, #16
-; CHECK-SDAG-NEXT: .cfi_def_cfa_offset 16
-; CHECK-SDAG-NEXT: add x8, sp, #8
-; CHECK-SDAG-NEXT: // kill: def $w0 killed $w0 def $x0
-; CHECK-SDAG-NEXT: str d0, [sp, #8]
-; CHECK-SDAG-NEXT: bfi x8, x0, #2, #1
-; CHECK-SDAG-NEXT: ldr w0, [x8]
-; CHECK-SDAG-NEXT: add sp, sp, #16
-; CHECK-SDAG-NEXT: ret
+; CHECK-SD-LABEL: test_varidx_extract_v2s16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sub sp, sp, #16
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
+; CHECK-SD-NEXT: add x8, sp, #8
+; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-SD-NEXT: str d0, [sp, #8]
+; CHECK-SD-NEXT: bfi x8, x0, #2, #1
+; CHECK-SD-NEXT: ldr w0, [x8]
+; CHECK-SD-NEXT: add sp, sp, #16
+; CHECK-SD-NEXT: ret
;
-; CHECK-GISEL-LABEL: test_varidx_extract_v2s16:
-; CHECK-GISEL: // %bb.0:
-; CHECK-GISEL-NEXT: sub sp, sp, #16
-; CHECK-GISEL-NEXT: .cfi_def_cfa_offset 16
-; CHECK-GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GISEL-NEXT: mov s1, v0.s[1]
-; CHECK-GISEL-NEXT: mov w9, w0
-; CHECK-GISEL-NEXT: add x8, sp, #12
-; CHECK-GISEL-NEXT: str h0, [sp, #12]
-; CHECK-GISEL-NEXT: and x9, x9, #0x1
-; CHECK-GISEL-NEXT: str h1, [sp, #14]
-; CHECK-GISEL-NEXT: ldrh w0, [x8, x9, lsl #1]
-; CHECK-GISEL-NEXT: add sp, sp, #16
-; CHECK-GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_varidx_extract_v2s16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #16
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: mov s1, v0.s[1]
+; CHECK-GI-NEXT: mov w9, w0
+; CHECK-GI-NEXT: add x8, sp, #12
+; CHECK-GI-NEXT: str h0, [sp, #12]
+; CHECK-GI-NEXT: and x9, x9, #0x1
+; CHECK-GI-NEXT: str h1, [sp, #14]
+; CHECK-GI-NEXT: ldrh w0, [x8, x9, lsl #1]
+; CHECK-GI-NEXT: add sp, sp, #16
+; CHECK-GI-NEXT: ret
%tmp = extractelement <2 x i16> %x, i32 %idx
ret i16 %tmp
}
define <2 x i16> @test_varidx_extract_v4s16(<4 x i16> %x, i32 %idx) {
-; CHECK-SDAG-LABEL: test_varidx_extract_v4s16:
-; CHECK-SDAG: // %bb.0:
-; CHECK-SDAG-NEXT: sub sp, sp, #16
-; CHECK-SDAG-NEXT: .cfi_def_cfa_offset 16
-; CHECK-SDAG-NEXT: add x8, sp, #8
-; CHECK-SDAG-NEXT: // kill: def $w0 killed $w0 def $x0
-; CHECK-SDAG-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SDAG-NEXT: str d0, [sp, #8]
-; CHECK-SDAG-NEXT: bfi x8, x0, #1, #2
-; CHECK-SDAG-NEXT: ld1 { v1.h }[0], [x8]
-; CHECK-SDAG-NEXT: mov v1.h[2], v0.h[1]
-; CHECK-SDAG-NEXT: fmov d0, d1
-; CHECK-SDAG-NEXT: add sp, sp, #16
-; CHECK-SDAG-NEXT: ret
+; CHECK-SD-LABEL: test_varidx_extract_v4s16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sub sp, sp, #16
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
+; CHECK-SD-NEXT: add x8, sp, #8
+; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: str d0, [sp, #8]
+; CHECK-SD-NEXT: bfi x8, x0, #1, #2
+; CHECK-SD-NEXT: ld1 { v1.h }[0], [x8]
+; CHECK-SD-NEXT: mov v1.h[2], v0.h[1]
+; CHECK-SD-NEXT: fmov d0, d1
+; CHECK-SD-NEXT: add sp, sp, #16
+; CHECK-SD-NEXT: ret
;
-; CHECK-GISEL-LABEL: test_varidx_extract_v4s16:
-; CHECK-GISEL: // %bb.0:
-; CHECK-GISEL-NEXT: sub sp, sp, #16
-; CHECK-GISEL-NEXT: .cfi_def_cfa_offset 16
-; CHECK-GISEL-NEXT: mov w9, w0
-; CHECK-GISEL-NEXT: mov w8, #2 // =0x2
-; CHECK-GISEL-NEXT: add x10, sp, #8
-; CHECK-GISEL-NEXT: and x9, x9, #0x3
-; CHECK-GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GISEL-NEXT: str d0, [sp, #8]
-; CHECK-GISEL-NEXT: umaddl x8, w9, w8, x10
-; CHECK-GISEL-NEXT: umov w9, v0.h[1]
-; CHECK-GISEL-NEXT: ld1 { v0.h }[0], [x8]
-; CHECK-GISEL-NEXT: mov v0.s[1], w9
-; CHECK-GISEL-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-GISEL-NEXT: add sp, sp, #16
-; CHECK-GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_varidx_extract_v4s16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #16
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
+; CHECK-GI-NEXT: mov w9, w0
+; CHECK-GI-NEXT: mov w8, #2 // =0x2
+; CHECK-GI-NEXT: add x10, sp, #8
+; CHECK-GI-NEXT: and x9, x9, #0x3
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: str d0, [sp, #8]
+; CHECK-GI-NEXT: umaddl x8, w9, w8, x10
+; CHECK-GI-NEXT: umov w9, v0.h[1]
+; CHECK-GI-NEXT: ld1 { v0.h }[0], [x8]
+; CHECK-GI-NEXT: mov v0.s[1], w9
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: add sp, sp, #16
+; CHECK-GI-NEXT: ret
%tmp = extractelement <4 x i16> %x, i32 %idx
%tmp2 = insertelement <2 x i16> undef, i16 %tmp, i32 0
%tmp3 = extractelement <4 x i16> %x, i32 1
@@ -189,37 +189,37 @@ define <2 x i16> @test_varidx_extract_v4s16(<4 x i16> %x, i32 %idx) {
}
define <4 x i16> @test_varidx_extract_v8s16(<8 x i16> %x, i32 %idx) {
-; CHECK-SDAG-LABEL: test_varidx_extract_v8s16:
-; CHECK-SDAG: // %bb.0:
-; CHECK-SDAG-NEXT: sub sp, sp, #16
-; CHECK-SDAG-NEXT: .cfi_def_cfa_offset 16
-; CHECK-SDAG-NEXT: mov x8, sp
-; CHECK-SDAG-NEXT: // kill: def $w0 killed $w0 def $x0
-; CHECK-SDAG-NEXT: str q0, [sp]
-; CHECK-SDAG-NEXT: bfi x8, x0, #1, #3
-; CHECK-SDAG-NEXT: ldr h1, [x8]
-; CHECK-SDAG-NEXT: mov v1.h[1], v0.h[1]
-; CHECK-SDAG-NEXT: mov v1.h[2], v0.h[2]
-; CHECK-SDAG-NEXT: mov v1.h[3], v0.h[3]
-; CHECK-SDAG-NEXT: fmov d0, d1
-; CHECK-SDAG-NEXT: add sp, sp, #16
-; CHECK-SDAG-NEXT: ret
+; CHECK-SD-LABEL: test_varidx_extract_v8s16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sub sp, sp, #16
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
+; CHECK-SD-NEXT: mov x8, sp
+; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-SD-NEXT: str q0, [sp]
+; CHECK-SD-NEXT: bfi x8, x0, #1, #3
+; CHECK-SD-NEXT: ldr h1, [x8]
+; CHECK-SD-NEXT: mov v1.h[1], v0.h[1]
+; CHECK-SD-NEXT: mov v1.h[2], v0.h[2]
+; CHECK-SD-NEXT: mov v1.h[3], v0.h[3]
+; CHECK-SD-NEXT: fmov d0, d1
+; CHECK-SD-NEXT: add sp, sp, #16
+; CHECK-SD-NEXT: ret
;
-; CHECK-GISEL-LABEL: test_varidx_extract_v8s16:
-; CHECK-GISEL: // %bb.0:
-; CHECK-GISEL-NEXT: sub sp, sp, #16
-; CHECK-GISEL-NEXT: .cfi_def_cfa_offset 16
-; CHECK-GISEL-NEXT: mov w9, w0
-; CHECK-GISEL-NEXT: mov x8, sp
-; CHECK-GISEL-NEXT: str q0, [sp]
-; CHECK-GISEL-NEXT: and x9, x9, #0x7
-; CHECK-GISEL-NEXT: ldr h1, [x8, x9, lsl #1]
-; CHECK-GISEL-NEXT: mov v1.h[1], v0.h[1]
-; CHECK-GISEL-NEXT: mov v1.h[2], v0.h[2]
-; CHECK-GISEL-NEXT: mov v1.h[3], v0.h[3]
-; CHECK-GISEL-NEXT: fmov d0, d1
-; CHECK-GISEL-NEXT: add sp, sp, #16
-; CHECK-GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_varidx_extract_v8s16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #16
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
+; CHECK-GI-NEXT: mov w9, w0
+; CHECK-GI-NEXT: mov x8, sp
+; CHECK-GI-NEXT: str q0, [sp]
+; CHECK-GI-NEXT: and x9, x9, #0x7
+; CHECK-GI-NEXT: ldr h1, [x8, x9, lsl #1]
+; CHECK-GI-NEXT: mov v1.h[1], v0.h[1]
+; CHECK-GI-NEXT: mov v1.h[2], v0.h[2]
+; CHECK-GI-NEXT: mov v1.h[3], v0.h[3]
+; CHECK-GI-NEXT: fmov d0, d1
+; CHECK-GI-NEXT: add sp, sp, #16
+; CHECK-GI-NEXT: ret
%tmp = extractelement <8 x i16> %x, i32 %idx
%tmp2 = insertelement <4 x i16> undef, i16 %tmp, i32 0
%tmp3 = extractelement <8 x i16> %x, i32 1
@@ -232,61 +232,61 @@ define <4 x i16> @test_varidx_extract_v8s16(<8 x i16> %x, i32 %idx) {
}
define i32 @test_varidx_extract_v2s32(<2 x i32> %x, i32 %idx) {
-; CHECK-SDAG-LABEL: test_varidx_extract_v2s32:
-; CHECK-SDAG: // %bb.0:
-; CHECK-SDAG-NEXT: sub sp, sp, #16
-; CHECK-SDAG-NEXT: .cfi_def_cfa_offset 16
-; CHECK-SDAG-NEXT: add x8, sp, #8
-; CHECK-SDAG-NEXT: // kill: def $w0 killed $w0 def $x0
-; CHECK-SDAG-NEXT: str d0, [sp, #8]
-; CHECK-SDAG-NEXT: bfi x8, x0, #2, #1
-; CHECK-SDAG-NEXT: ldr w0, [x8]
-; CHECK-SDAG-NEXT: add sp, sp, #16
-; CHECK-SDAG-NEXT: ret
+; CHECK-SD-LABEL: test_varidx_extract_v2s32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sub sp, sp, #16
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
+; CHECK-SD-NEXT: add x8, sp, #8
+; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-SD-NEXT: str d0, [sp, #8]
+; CHECK-SD-NEXT: bfi x8, x0, #2, #1
+; CHECK-SD-NEXT: ldr w0, [x8]
+; CHECK-SD-NEXT: add sp, sp, #16
+; CHECK-SD-NEXT: ret
;
-; CHECK-GISEL-LABEL: test_varidx_extract_v2s32:
-; CHECK-GISEL: // %bb.0:
-; CHECK-GISEL-NEXT: sub sp, sp, #16
-; CHECK-GISEL-NEXT: .cfi_def_cfa_offset 16
-; CHECK-GISEL-NEXT: mov w9, w0
-; CHECK-GISEL-NEXT: add x8, sp, #8
-; CHECK-GISEL-NEXT: str d0, [sp, #8]
-; CHECK-GISEL-NEXT: and x9, x9, #0x1
-; CHECK-GISEL-NEXT: ldr w0, [x8, x9, lsl #2]
-; CHECK-GISEL-NEXT: add sp, sp, #16
-; CHECK-GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_varidx_extract_v2s32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #16
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
+; CHECK-GI-NEXT: mov w9, w0
+; CHECK-GI-NEXT: add x8, sp, #8
+; CHECK-GI-NEXT: str d0, [sp, #8]
+; CHECK-GI-NEXT: and x9, x9, #0x1
+; CHECK-GI-NEXT: ldr w0, [x8, x9, lsl #2]
+; CHECK-GI-NEXT: add sp, sp, #16
+; CHECK-GI-NEXT: ret
%tmp = extractelement <2 x i32> %x, i32 %idx
ret i32 %tmp
}
define <2 x i32> @test_varidx_extract_v4s32(<4 x i32> %x, i32 %idx) {
-; CHECK-SDAG-LABEL: test_varidx_extract_v4s32:
-; CHECK-SDAG: // %bb.0:
-; CHECK-SDAG-NEXT: sub sp, sp, #16
-; CHECK-SDAG-NEXT: .cfi_def_cfa_offset 16
-; CHECK-SDAG-NEXT: mov x8, sp
-; CHECK-SDAG-NEXT: // kill: def $w0 killed $w0 def $x0
-; CHECK-SDAG-NEXT: str q0, [sp]
-; CHECK-SDAG-NEXT: bfi x8, x0, #2, #2
-; CHECK-SDAG-NEXT: ldr s1, [x8]
-; CHECK-SDAG-NEXT: mov v1.s[1], v0.s[1]
-; CHECK-SDAG-NEXT: fmov d0, d1
-; CHECK-SDAG-NEXT: add sp, sp, #16
-; CHECK-SDAG-NEXT: ret
+; CHECK-SD-LABEL: test_varidx_extract_v4s32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sub sp, sp, #16
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
+; CHECK-SD-NEXT: mov x8, sp
+; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-SD-NEXT: str q0, [sp]
+; CHECK-SD-NEXT: bfi x8, x0, #2, #2
+; CHECK-SD-NEXT: ldr s1, [x8]
+; CHECK-SD-NEXT: mov v1.s[1], v0.s[1]
+; CHECK-SD-NEXT: fmov d0, d1
+; CHECK-SD-NEXT: add sp, sp, #16
+; CHECK-SD-NEXT: ret
;
-; CHECK-GISEL-LABEL: test_varidx_extract_v4s32:
-; CHECK-GISEL: // %bb.0:
-; CHECK-GISEL-NEXT: sub sp, sp, #16
-; CHECK-GISEL-NEXT: .cfi_def_cfa_offset 16
-; CHECK-GISEL-NEXT: mov w9, w0
-; CHECK-GISEL-NEXT: mov x8, sp
-; CHECK-GISEL-NEXT: str q0, [sp]
-; CHECK-GISEL-NEXT: and x9, x9, #0x3
-; CHECK-GISEL-NEXT: ldr s1, [x8, x9, lsl #2]
-; CHECK-GISEL-NEXT: mov v1.s[1], v0.s[1]
-; CHECK-GISEL-NEXT: fmov d0, d1
-; CHECK-GISEL-NEXT: add sp, sp, #16
-; CHECK-GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_varidx_extract_v4s32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #16
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
+; CHECK-GI-NEXT: mov w9, w0
+; CHECK-GI-NEXT: mov x8, sp
+; CHECK-GI-NEXT: str q0, [sp]
+; CHECK-GI-NEXT: and x9, x9, #0x3
+; CHECK-GI-NEXT: ldr s1, [x8, x9, lsl #2]
+; CHECK-GI-NEXT: mov v1.s[1], v0.s[1]
+; CHECK-GI-NEXT: fmov d0, d1
+; CHECK-GI-NEXT: add sp, sp, #16
+; CHECK-GI-NEXT: ret
%tmp = extractelement <4 x i32> %x, i32 %idx
%tmp2 = insertelement <2 x i32> undef, i32 %tmp, i32 0
%tmp3 = extractelement <4 x i32> %x, i32 1
@@ -295,57 +295,59 @@ define <2 x i32> @test_varidx_extract_v4s32(<4 x i32> %x, i32 %idx) {
}
define i64 @test_varidx_extract_v2s64(<2 x i64> %x, i32 %idx) {
-; CHECK-SDAG-LABEL: test_varidx_extract_v2s64:
-; CHECK-SDAG: // %bb.0:
-; CHECK-SDAG-NEXT: sub sp, sp, #16
-; CHECK-SDAG-NEXT: .cfi_def_cfa_offset 16
-; CHECK-SDAG-NEXT: mov x8, sp
-; CHECK-SDAG-NEXT: // kill: def $w0 killed $w0 def $x0
-; CHECK-SDAG-NEXT: str q0, [sp]
-; CHECK-SDAG-NEXT: bfi x8, x0, #3, #1
-; CHECK-SDAG-NEXT: ldr x0, [x8]
-; CHECK-SDAG-NEXT: add sp, sp, #16
-; CHECK-SDAG-NEXT: ret
+; CHECK-SD-LABEL: test_varidx_extract_v2s64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sub sp, sp, #16
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
+; CHECK-SD-NEXT: mov x8, sp
+; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-SD-NEXT: str q0, [sp]
+; CHECK-SD-NEXT: bfi x8, x0, #3, #1
+; CHECK-SD-NEXT: ldr x0, [x8]
+; CHECK-SD-NEXT: add sp, sp, #16
+; CHECK-SD-NEXT: ret
;
-; CHECK-GISEL-LABEL: test_varidx_extract_v2s64:
-; CHECK-GISEL: // %bb.0:
-; CHECK-GISEL-NEXT: sub sp, sp, #16
-; CHECK-GISEL-NEXT: .cfi_def_cfa_offset 16
-; CHECK-GISEL-NEXT: mov w9, w0
-; CHECK-GISEL-NEXT: mov x8, sp
-; CHECK-GISEL-NEXT: str q0, [sp]
-; CHECK-GISEL-NEXT: and x9, x9, #0x1
-; CHECK-GISEL-NEXT: ldr x0, [x8, x9, lsl #3]
-; CHECK-GISEL-NEXT: add sp, sp, #16
-; CHECK-GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_varidx_extract_v2s64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #16
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
+; CHECK-GI-NEXT: mov w9, w0
+; CHECK-GI-NEXT: mov x8, sp
+; CHECK-GI-NEXT: str q0, [sp]
+; CHECK-GI-NEXT: and x9, x9, #0x1
+; CHECK-GI-NEXT: ldr x0, [x8, x9, lsl #3]
+; CHECK-GI-NEXT: add sp, sp, #16
+; CHECK-GI-NEXT: ret
%tmp = extractelement <2 x i64> %x, i32 %idx
ret i64 %tmp
}
define ptr @test_varidx_extract_v2p0(<2 x ptr> %x, i32 %idx) {
-; CHECK-SDAG-LABEL: test_varidx_extract_v2p0:
-; CHECK-SDAG: // %bb.0:
-; CHECK-SDAG-NEXT: sub sp, sp, #16
-; CHECK-SDAG-NEXT: .cfi_def_cfa_offset 16
-; CHECK-SDAG-NEXT: mov x8, sp
-; CHECK-SDAG-NEXT: // kill: def $w0 killed $w0 def $x0
-; CHECK-SDAG-NEXT: str q0, [sp]
-; CHECK-SDAG-NEXT: bfi x8, x0, #3, #1
-; CHECK-SDAG-NEXT: ldr x0, [x8]
-; CHECK-SDAG-NEXT: add sp, sp, #16
-; CHECK-SDAG-NEXT: ret
+; CHECK-SD-LABEL: test_varidx_extract_v2p0:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sub sp, sp, #16
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
+; CHECK-SD-NEXT: mov x8, sp
+; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-SD-NEXT: str q0, [sp]
+; CHECK-SD-NEXT: bfi x8, x0, #3, #1
+; CHECK-SD-NEXT: ldr x0, [x8]
+; CHECK-SD-NEXT: add sp, sp, #16
+; CHECK-SD-NEXT: ret
;
-; CHECK-GISEL-LABEL: test_varidx_extract_v2p0:
-; CHECK-GISEL: // %bb.0:
-; CHECK-GISEL-NEXT: sub sp, sp, #16
-; CHECK-GISEL-NEXT: .cfi_def_cfa_offset 16
-; CHECK-GISEL-NEXT: mov w9, w0
-; CHECK-GISEL-NEXT: mov x8, sp
-; CHECK-GISEL-NEXT: str q0, [sp]
-; CHECK-GISEL-NEXT: and x9, x9, #0x1
-; CHECK-GISEL-NEXT: ldr x0, [x8, x9, lsl #3]
-; CHECK-GISEL-NEXT: add sp, sp, #16
-; CHECK-GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_varidx_extract_v2p0:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #16
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
+; CHECK-GI-NEXT: mov w9, w0
+; CHECK-GI-NEXT: mov x8, sp
+; CHECK-GI-NEXT: str q0, [sp]
+; CHECK-GI-NEXT: and x9, x9, #0x1
+; CHECK-GI-NEXT: ldr x0, [x8, x9, lsl #3]
+; CHECK-GI-NEXT: add sp, sp, #16
+; CHECK-GI-NEXT: ret
%tmp = extractelement <2 x ptr> %x, i32 %idx
ret ptr %tmp
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll b/llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll
index f08ff2ccf693d..aaabb442e764a 100644
--- a/llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s --check-prefix=CHECK-SD
-; RUN: llc < %s -mtriple=arm64-eabi -global-isel=1 -aarch64-neon-syntax=apple | FileCheck %s --check-prefix=CHECK-GI
+; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=arm64-eabi -global-isel=1 -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; Extract of an upper half of a vector is an "ext.16b v0, v0, v0, #8" insn.
@@ -108,3 +108,6 @@ define <1 x double> @v1f64(<2 x double> %a) nounwind {
%ret = shufflevector <2 x double> %a, <2 x double> %a, <1 x i32> <i32 1>
ret <1 x double> %ret
}
+
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/fcmp-fp128.ll b/llvm/test/CodeGen/AArch64/fcmp-fp128.ll
index d067d833a7e16..9f6c6eab925fa 100644
--- a/llvm/test/CodeGen/AArch64/fcmp-fp128.ll
+++ b/llvm/test/CodeGen/AArch64/fcmp-fp128.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK-SD
-; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK-GI
+; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; Checks generated libcalls for fp128 types
@@ -556,3 +556,5 @@ entry:
ret double %s
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/shift-logic.ll b/llvm/test/CodeGen/AArch64/shift-logic.ll
index b1ad31d1475ce..8f82b54ba7132 100644
--- a/llvm/test/CodeGen/AArch64/shift-logic.ll
+++ b/llvm/test/CodeGen/AArch64/shift-logic.ll
@@ -1,19 +1,19 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
-; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=1 | FileCheck %s --check-prefix=CHECK-GISEL
+; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define i8 @shl_and(i8 %x, i8 %y) nounwind {
-; CHECK-LABEL: shl_and:
-; CHECK: // %bb.0:
-; CHECK-NEXT: lsl w8, w0, #5
-; CHECK-NEXT: and w0, w8, w1, lsl #2
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: shl_and:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: lsl w8, w0, #5
+; CHECK-SD-NEXT: and w0, w8, w1, lsl #2
+; CHECK-SD-NEXT: ret
;
-; CHECK-GISEL-LABEL: shl_and:
-; CHECK-GISEL: // %bb.0:
-; CHECK-GISEL-NEXT: lsl w8, w1, #2
-; CHECK-GISEL-NEXT: and w0, w8, w0, lsl #5
-; CHECK-GISEL-NEXT: ret
+; CHECK-GI-LABEL: shl_and:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: lsl w8, w1, #2
+; CHECK-GI-NEXT: and w0, w8, w0, lsl #5
+; CHECK-GI-NEXT: ret
%sh0 = shl i8 %x, 3
%r = and i8 %sh0, %y
%sh1 = shl i8 %r, 2
@@ -21,17 +21,17 @@ define i8 @shl_and(i8 %x, i8 %y) nounwind {
}
define i16 @shl_or(i16 %x, i16 %y) nounwind {
-; CHECK-LABEL: shl_or:
-; CHECK: // %bb.0:
-; CHECK-NEXT: lsl w8, w0, #12
-; CHECK-NEXT: orr w0, w8, w1, lsl #7
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: shl_or:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: lsl w8, w0, #12
+; CHECK-SD-NEXT: orr w0, w8, w1, lsl #7
+; CHECK-SD-NEXT: ret
;
-; CHECK-GISEL-LABEL: shl_or:
-; CHECK-GISEL: // %bb.0:
-; CHECK-GISEL-NEXT: lsl w8, w1, #7
-; CHECK-GISEL-NEXT: orr w0, w8, w0, lsl #12
-; CHECK-GISEL-NEXT: ret
+; CHECK-GI-LABEL: shl_or:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: lsl w8, w1, #7
+; CHECK-GI-NEXT: orr w0, w8, w0, lsl #12
+; CHECK-GI-NEXT: ret
%sh0 = shl i16 %x, 5
%r = or i16 %y, %sh0
%sh1 = shl i16 %r, 7
@@ -39,17 +39,17 @@ define i16 @shl_or(i16 %x, i16 %y) nounwind {
}
define i32 @shl_xor(i32 %x, i32 %y) nounwind {
-; CHECK-LABEL: shl_xor:
-; CHECK: // %bb.0:
-; CHECK-NEXT: lsl w8, w0, #12
-; CHECK-NEXT: eor w0, w8, w1, lsl #7
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: shl_xor:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: lsl w8, w0, #12
+; CHECK-SD-NEXT: eor w0, w8, w1, lsl #7
+; CHECK-SD-NEXT: ret
;
-; CHECK-GISEL-LABEL: shl_xor:
-; CHECK-GISEL: // %bb.0:
-; CHECK-GISEL-NEXT: lsl w8, w1, #7
-; CHECK-GISEL-NEXT: eor w0, w8, w0, lsl #12
-; CHECK-GISEL-NEXT: ret
+; CHECK-GI-LABEL: shl_xor:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: lsl w8, w1, #7
+; CHECK-GI-NEXT: eor w0, w8, w0, lsl #12
+; CHECK-GI-NEXT: ret
%sh0 = shl i32 %x, 5
%r = xor i32 %sh0, %y
%sh1 = shl i32 %r, 7
@@ -57,17 +57,17 @@ define i32 @shl_xor(i32 %x, i32 %y) nounwind {
}
define i64 @lshr_and(i64 %x, i64 %y) nounwind {
-; CHECK-LABEL: lshr_and:
-; CHECK: // %bb.0:
-; CHECK-NEXT: lsr x8, x0, #12
-; CHECK-NEXT: and x0, x8, x1, lsr #7
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: lshr_and:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: lsr x8, x0, #12
+; CHECK-SD-NEXT: and x0, x8, x1, lsr #7
+; CHECK-SD-NEXT: ret
;
-; CHECK-GISEL-LABEL: lshr_and:
-; CHECK-GISEL: // %bb.0:
-; CHECK-GISEL-NEXT: lsr x8, x1, #7
-; CHECK-GISEL-NEXT: and x0, x8, x0, lsr #12
-; CHECK-GISEL-NEXT: ret
+; CHECK-GI-LABEL: lshr_and:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: lsr x8, x1, #7
+; CHECK-GI-NEXT: and x0, x8, x0, lsr #12
+; CHECK-GI-NEXT: ret
%sh0 = lshr i64 %x, 5
%r = and i64 %y, %sh0
%sh1 = lshr i64 %r, 7
@@ -75,19 +75,19 @@ define i64 @lshr_and(i64 %x, i64 %y) nounwind {
}
define <4 x i32> @lshr_or(<4 x i32> %x, <4 x i32> %y) nounwind {
-; CHECK-LABEL: lshr_or:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ushr v1.4s, v1.4s, #7
-; CHECK-NEXT: ushr v0.4s, v0.4s, #12
-; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: lshr_or:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ushr v1.4s, v1.4s, #7
+; CHECK-SD-NEXT: ushr v0.4s, v0.4s, #12
+; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT: ret
;
-; CHECK-GISEL-LABEL: lshr_or:
-; CHECK-GISEL: // %bb.0:
-; CHECK-GISEL-NEXT: ushr v0.4s, v0.4s, #5
-; CHECK-GISEL-NEXT: orr v0.16b, v0.16b, v1.16b
-; CHECK-GISEL-NEXT: ushr v0.4s, v0.4s, #7
-; CHECK-GISEL-NEXT: ret
+; CHECK-GI-LABEL: lshr_or:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushr v0.4s, v0.4s, #5
+; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: ushr v0.4s, v0.4s, #7
+; CHECK-GI-NEXT: ret
%sh0 = lshr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>
%r = or <4 x i32> %sh0, %y
%sh1 = lshr <4 x i32> %r, <i32 7, i32 7, i32 7, i32 7>
@@ -95,19 +95,19 @@ define <4 x i32> @lshr_or(<4 x i32> %x, <4 x i32> %y) nounwind {
}
define <8 x i16> @lshr_xor(<8 x i16> %x, <8 x i16> %y) nounwind {
-; CHECK-LABEL: lshr_xor:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ushr v1.8h, v1.8h, #7
-; CHECK-NEXT: ushr v0.8h, v0.8h, #12
-; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: lshr_xor:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ushr v1.8h, v1.8h, #7
+; CHECK-SD-NEXT: ushr v0.8h, v0.8h, #12
+; CHECK-SD-NEXT: eor v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT: ret
;
-; CHECK-GISEL-LABEL: lshr_xor:
-; CHECK-GISEL: // %bb.0:
-; CHECK-GISEL-NEXT: ushr v0.8h, v0.8h, #5
-; CHECK-GISEL-NEXT: eor v0.16b, v1.16b, v0.16b
-; CHECK-GISEL-NEXT: ushr v0.8h, v0.8h, #7
-; CHECK-GISEL-NEXT: ret
+; CHECK-GI-LABEL: lshr_xor:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushr v0.8h, v0.8h, #5
+; CHECK-GI-NEXT: eor v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT: ushr v0.8h, v0.8h, #7
+; CHECK-GI-NEXT: ret
%sh0 = lshr <8 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
%r = xor <8 x i16> %y, %sh0
%sh1 = lshr <8 x i16> %r, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
@@ -116,19 +116,19 @@ define <8 x i16> @lshr_xor(<8 x i16> %x, <8 x i16> %y) nounwind {
define <16 x i8> @ashr_and(<16 x i8> %x, <16 x i8> %y) nounwind {
-; CHECK-LABEL: ashr_and:
-; CHECK: // %bb.0:
-; CHECK-NEXT: sshr v1.16b, v1.16b, #2
-; CHECK-NEXT: sshr v0.16b, v0.16b, #5
-; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: ashr_and:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sshr v1.16b, v1.16b, #2
+; CHECK-SD-NEXT: sshr v0.16b, v0.16b, #5
+; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT: ret
;
-; CHECK-GISEL-LABEL: ashr_and:
-; CHECK-GISEL: // %bb.0:
-; CHECK-GISEL-NEXT: sshr v0.16b, v0.16b, #3
-; CHECK-GISEL-NEXT: and v0.16b, v1.16b, v0.16b
-; CHECK-GISEL-NEXT: sshr v0.16b, v0.16b, #2
-; CHECK-GISEL-NEXT: ret
+; CHECK-GI-LABEL: ashr_and:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshr v0.16b, v0.16b, #3
+; CHECK-GI-NEXT: and v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT: sshr v0.16b, v0.16b, #2
+; CHECK-GI-NEXT: ret
%sh0 = ashr <16 x i8> %x, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
%r = and <16 x i8> %y, %sh0
%sh1 = ashr <16 x i8> %r, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
@@ -136,19 +136,19 @@ define <16 x i8> @ashr_and(<16 x i8> %x, <16 x i8> %y) nounwind {
}
define <2 x i64> @ashr_or(<2 x i64> %x, <2 x i64> %y) nounwind {
-; CHECK-LABEL: ashr_or:
-; CHECK: // %bb.0:
-; CHECK-NEXT: sshr v1.2d, v1.2d, #7
-; CHECK-NEXT: sshr v0.2d, v0.2d, #12
-; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: ashr_or:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sshr v1.2d, v1.2d, #7
+; CHECK-SD-NEXT: sshr v0.2d, v0.2d, #12
+; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT: ret
;
-; CHECK-GISEL-LABEL: ashr_or:
-; CHECK-GISEL: // %bb.0:
-; CHECK-GISEL-NEXT: sshr v0.2d, v0.2d, #5
-; CHECK-GISEL-NEXT: orr v0.16b, v0.16b, v1.16b
-; CHECK-GISEL-NEXT: sshr v0.2d, v0.2d, #7
-; CHECK-GISEL-NEXT: ret
+; CHECK-GI-LABEL: ashr_or:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshr v0.2d, v0.2d, #5
+; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: sshr v0.2d, v0.2d, #7
+; CHECK-GI-NEXT: ret
%sh0 = ashr <2 x i64> %x, <i64 5, i64 5>
%r = or <2 x i64> %sh0, %y
%sh1 = ashr <2 x i64> %r, <i64 7, i64 7>
@@ -156,17 +156,17 @@ define <2 x i64> @ashr_or(<2 x i64> %x, <2 x i64> %y) nounwind {
}
define i32 @ashr_xor(i32 %x, i32 %y) nounwind {
-; CHECK-LABEL: ashr_xor:
-; CHECK: // %bb.0:
-; CHECK-NEXT: asr w8, w0, #12
-; CHECK-NEXT: eor w0, w8, w1, asr #7
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: ashr_xor:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: asr w8, w0, #12
+; CHECK-SD-NEXT: eor w0, w8, w1, asr #7
+; CHECK-SD-NEXT: ret
;
-; CHECK-GISEL-LABEL: ashr_xor:
-; CHECK-GISEL: // %bb.0:
-; CHECK-GISEL-NEXT: asr w8, w1, #7
-; CHECK-GISEL-NEXT: eor w0, w8, w0, asr #12
-; CHECK-GISEL-NEXT: ret
+; CHECK-GI-LABEL: ashr_xor:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: asr w8, w1, #7
+; CHECK-GI-NEXT: eor w0, w8, w0, asr #12
+; CHECK-GI-NEXT: ret
%sh0 = ashr i32 %x, 5
%r = xor i32 %y, %sh0
%sh1 = ashr i32 %r, 7
@@ -179,12 +179,6 @@ define i32 @shr_mismatch_xor(i32 %x, i32 %y) nounwind {
; CHECK-NEXT: eor w8, w1, w0, asr #5
; CHECK-NEXT: lsr w0, w8, #7
; CHECK-NEXT: ret
-;
-; CHECK-GISEL-LABEL: shr_mismatch_xor:
-; CHECK-GISEL: // %bb.0:
-; CHECK-GISEL-NEXT: eor w8, w1, w0, asr #5
-; CHECK-GISEL-NEXT: lsr w0, w8, #7
-; CHECK-GISEL-NEXT: ret
%sh0 = ashr i32 %x, 5
%r = xor i32 %y, %sh0
%sh1 = lshr i32 %r, 7
@@ -197,12 +191,6 @@ define i32 @ashr_overshift_xor(i32 %x, i32 %y) nounwind {
; CHECK-NEXT: eor w8, w1, w0, asr #15
; CHECK-NEXT: asr w0, w8, #17
; CHECK-NEXT: ret
-;
-; CHECK-GISEL-LABEL: ashr_overshift_xor:
-; CHECK-GISEL: // %bb.0:
-; CHECK-GISEL-NEXT: eor w8, w1, w0, asr #15
-; CHECK-GISEL-NEXT: asr w0, w8, #17
-; CHECK-GISEL-NEXT: ret
%sh0 = ashr i32 %x, 15
%r = xor i32 %y, %sh0
%sh1 = ashr i32 %r, 17
@@ -216,13 +204,6 @@ define i32 @lshr_or_extra_use(i32 %x, i32 %y, ptr %p) nounwind {
; CHECK-NEXT: lsr w0, w8, #7
; CHECK-NEXT: str w8, [x2]
; CHECK-NEXT: ret
-;
-; CHECK-GISEL-LABEL: lshr_or_extra_use:
-; CHECK-GISEL: // %bb.0:
-; CHECK-GISEL-NEXT: orr w8, w1, w0, lsr #5
-; CHECK-GISEL-NEXT: lsr w0, w8, #7
-; CHECK-GISEL-NEXT: str w8, [x2]
-; CHECK-GISEL-NEXT: ret
%sh0 = lshr i32 %x, 5
%r = or i32 %sh0, %y
store i32 %r, ptr %p
@@ -231,16 +212,16 @@ define i32 @lshr_or_extra_use(i32 %x, i32 %y, ptr %p) nounwind {
}
define i64 @desirable_to_commute1(i64 %x) {
-; CHECK-LABEL: desirable_to_commute1:
-; CHECK: // %bb.0:
-; CHECK-NEXT: and x0, x0, #0x7fff8
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: desirable_to_commute1:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: and x0, x0, #0x7fff8
+; CHECK-SD-NEXT: ret
;
-; CHECK-GISEL-LABEL: desirable_to_commute1:
-; CHECK-GISEL: // %bb.0:
-; CHECK-GISEL-NEXT: ubfx x8, x0, #3, #16
-; CHECK-GISEL-NEXT: lsl x0, x8, #3
-; CHECK-GISEL-NEXT: ret
+; CHECK-GI-LABEL: desirable_to_commute1:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ubfx x8, x0, #3, #16
+; CHECK-GI-NEXT: lsl x0, x8, #3
+; CHECK-GI-NEXT: ret
%s1 = lshr i64 %x, 3
%a = and i64 %s1, 65535
%s2 = shl i64 %a, 3
@@ -248,17 +229,17 @@ define i64 @desirable_to_commute1(i64 %x) {
}
define i64 @desirable_to_commute2(ptr %p, i64 %i) {
-; CHECK-LABEL: desirable_to_commute2:
-; CHECK: // %bb.0:
-; CHECK-NEXT: and x8, x1, #0x1ff8
-; CHECK-NEXT: ldr x0, [x0, x8]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: desirable_to_commute2:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: and x8, x1, #0x1ff8
+; CHECK-SD-NEXT: ldr x0, [x0, x8]
+; CHECK-SD-NEXT: ret
;
-; CHECK-GISEL-LABEL: desirable_to_commute2:
-; CHECK-GISEL: // %bb.0:
-; CHECK-GISEL-NEXT: ubfx x8, x1, #3, #10
-; CHECK-GISEL-NEXT: ldr x0, [x0, x8, lsl #3]
-; CHECK-GISEL-NEXT: ret
+; CHECK-GI-LABEL: desirable_to_commute2:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ubfx x8, x1, #3, #10
+; CHECK-GI-NEXT: ldr x0, [x0, x8, lsl #3]
+; CHECK-GI-NEXT: ret
%lshr = lshr i64 %i, 3
%and = and i64 %lshr, 1023
%pidx = getelementptr i64, ptr %p, i64 %and
@@ -270,19 +251,19 @@ define i64 @desirable_to_commute2(ptr %p, i64 %i) {
; Lshr and shl will have different shift amount type.
; Compare apint will cause crash when type is different.
define void @apint_type_mismatch(i16 %a, ptr %p) {
-; CHECK-LABEL: apint_type_mismatch:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: and w8, w0, #0x7f8
-; CHECK-NEXT: str w8, [x1]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: apint_type_mismatch:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: and w8, w0, #0x7f8
+; CHECK-SD-NEXT: str w8, [x1]
+; CHECK-SD-NEXT: ret
;
-; CHECK-GISEL-LABEL: apint_type_mismatch:
-; CHECK-GISEL: // %bb.0: // %entry
-; CHECK-GISEL-NEXT: ubfx w8, w0, #3, #13
-; CHECK-GISEL-NEXT: and w8, w8, #0xff
-; CHECK-GISEL-NEXT: lsl w8, w8, #3
-; CHECK-GISEL-NEXT: str w8, [x1]
-; CHECK-GISEL-NEXT: ret
+; CHECK-GI-LABEL: apint_type_mismatch:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ubfx w8, w0, #3, #13
+; CHECK-GI-NEXT: and w8, w8, #0xff
+; CHECK-GI-NEXT: lsl w8, w8, #3
+; CHECK-GI-NEXT: str w8, [x1]
+; CHECK-GI-NEXT: ret
entry:
%lshr = lshr i16 %a, 3
%and = and i16 %lshr, 255
diff --git a/llvm/test/CodeGen/AArch64/trunc-avg-fold.ll b/llvm/test/CodeGen/AArch64/trunc-avg-fold.ll
index 0a72bbccf0ed2..36705412d3bd0 100644
--- a/llvm/test/CodeGen/AArch64/trunc-avg-fold.ll
+++ b/llvm/test/CodeGen/AArch64/trunc-avg-fold.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=aarch64-- -O2 -mattr=+neon < %s | FileCheck %s --check-prefixes=CHECK-SD
-; RUN: llc -mtriple=aarch64-- -O2 -mattr=+neon -global-isel < %s | FileCheck %s --check-prefixes=CHECK-GI
+; RUN: llc -mtriple=aarch64 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -mtriple=aarch64 -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define <8 x i8> @avgceil_u_i8_to_i16(<8 x i8> %a, <8 x i8> %b) {
; CHECK-SD-LABEL: avgceil_u_i8_to_i16:
@@ -82,3 +82,6 @@ define <8 x i8> @test_avgfloor_s(<8 x i8> %a, <8 x i8> %b) {
%res = trunc <8 x i16> %avg16 to <8 x i8>
ret <8 x i8> %res
}
+
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
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