[llvm] [AArch64] Use dup (lane mov) over ext for high-half extract (PR #195010)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 29 23:04:54 PDT 2026
https://github.com/davemgreen created https://github.com/llvm/llvm-project/pull/195010
This changes the instruction we use to extract the high half of a vector register from a `ext v0, v1, v1, 8` to a `dup d0, v1.d[1]`. This is apparently slightly quicker on certain cpus and is generally a simpler instruction. This matches the instruction that gisel already produces.
>From c9434180c4fbacf0b9986a35f83ebe11d65e0d83 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Thu, 30 Apr 2026 07:02:01 +0100
Subject: [PATCH] [AArch64] Use dup (lane mov) over ext for high-half extract
This changes the instruction we use to extract the high half of a vector
register from a ext v0, v1, v1, 8 to a dup d0, v1.d[1]. This is apparently
slighty quicker on certain cpus and is generally a simpler instruction.
---
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 26 +-
llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll | 24 +-
llvm/test/CodeGen/AArch64/aarch64-mulv.ll | 37 +-
.../AArch64/aarch64_be-shuffle-vector.ll | 4 +-
llvm/test/CodeGen/AArch64/abd-combine.ll | 2 +-
llvm/test/CodeGen/AArch64/add-extract.ll | 4 +-
llvm/test/CodeGen/AArch64/arm64-ext.ll | 2 +-
.../AArch64/arm64-extract_subvector.ll | 21 +-
llvm/test/CodeGen/AArch64/arm64-neon-copy.ll | 14 +-
.../CodeGen/AArch64/arm64-neon-simd-vget.ll | 42 +-
llvm/test/CodeGen/AArch64/bf16-shuffle.ll | 3 +-
.../CodeGen/AArch64/bf16-vector-shuffle.ll | 3 +-
llvm/test/CodeGen/AArch64/clmul-fixed.ll | 12 +-
.../CodeGen/AArch64/combine-storetomstore.ll | 4 +-
.../complex-deinterleaving-mixed-cases.ll | 28 +-
.../complex-deinterleaving-multiuses.ll | 20 +-
.../complex-deinterleaving-uniform-cases.ll | 8 +-
llvm/test/CodeGen/AArch64/concat-vector.ll | 16 +-
llvm/test/CodeGen/AArch64/ctlz.ll | 3 +-
llvm/test/CodeGen/AArch64/ctpop.ll | 3 +-
llvm/test/CodeGen/AArch64/cttz.ll | 3 +-
llvm/test/CodeGen/AArch64/double_reduct.ll | 30 +-
llvm/test/CodeGen/AArch64/ext-narrow-index.ll | 56 +--
.../CodeGen/AArch64/extract-subvec-combine.ll | 20 +-
.../CodeGen/AArch64/extract-vector-elt.ll | 2 +-
.../AArch64/f16f32dot-fixed-length-fdot.ll | 2 +-
llvm/test/CodeGen/AArch64/fabs.ll | 3 +-
llvm/test/CodeGen/AArch64/faddsub.ll | 6 +-
llvm/test/CodeGen/AArch64/fcmp.ll | 8 +-
llvm/test/CodeGen/AArch64/fcopysign.ll | 3 +-
llvm/test/CodeGen/AArch64/fcvt.ll | 21 +-
llvm/test/CodeGen/AArch64/fdiv.ll | 3 +-
.../AArch64/fixed-vector-deinterleave.ll | 18 +-
.../AArch64/fixed-vector-interleave.ll | 9 +-
llvm/test/CodeGen/AArch64/fminimummaximum.ll | 6 +-
llvm/test/CodeGen/AArch64/fminmax.ll | 6 +-
llvm/test/CodeGen/AArch64/fmla.ll | 9 +-
llvm/test/CodeGen/AArch64/fmul.ll | 3 +-
llvm/test/CodeGen/AArch64/fneg.ll | 3 +-
.../AArch64/fp-maximumnum-minimumnum.ll | 13 +-
.../CodeGen/AArch64/fp16-vector-shuffle.ll | 3 +-
llvm/test/CodeGen/AArch64/fpext.ll | 34 +-
llvm/test/CodeGen/AArch64/fptoi.ll | 166 ++-----
.../test/CodeGen/AArch64/fptosi-sat-vector.ll | 34 +-
.../test/CodeGen/AArch64/fptoui-sat-vector.ll | 18 +-
llvm/test/CodeGen/AArch64/freeze.ll | 6 +-
llvm/test/CodeGen/AArch64/fsqrt.ll | 3 +-
.../CodeGen/AArch64/highextractbitcast.ll | 87 ++--
llvm/test/CodeGen/AArch64/icmp.ll | 3 +-
llvm/test/CodeGen/AArch64/insert-subvector.ll | 6 +-
llvm/test/CodeGen/AArch64/insertextract.ll | 12 +-
llvm/test/CodeGen/AArch64/itofp.ll | 432 ++++--------------
llvm/test/CodeGen/AArch64/neon-abd.ll | 4 +-
.../neon-partial-reduce-dot-product.ll | 70 +--
llvm/test/CodeGen/AArch64/neon-scalar-copy.ll | 121 +++--
llvm/test/CodeGen/AArch64/nontemporal-load.ll | 12 +-
llvm/test/CodeGen/AArch64/ptradd.ll | 8 +-
llvm/test/CodeGen/AArch64/reduce-and.ll | 16 +-
llvm/test/CodeGen/AArch64/reduce-or.ll | 16 +-
llvm/test/CodeGen/AArch64/reduce-xor.ll | 16 +-
llvm/test/CodeGen/AArch64/sext.ll | 12 +-
llvm/test/CodeGen/AArch64/st1-lane.ll | 176 +++----
.../sve-fixed-length-extract-subvector.ll | 21 +-
.../AArch64/sve-fixed-length-fp-to-int.ll | 4 +-
.../AArch64/sve-fixed-length-int-extends.ll | 12 +-
.../AArch64/sve-fixed-length-int-to-fp.ll | 4 +-
.../sve-fixed-length-masked-expandloads.ll | 48 +-
.../AArch64/sve-fixed-length-masked-gather.ll | 4 +-
.../AArch64/sve-fixed-length-masked-loads.ll | 24 +-
.../sve-fixed-length-masked-scatter.ll | 8 +-
.../AArch64/sve-fixed-vector-llrint.ll | 214 ++++-----
.../CodeGen/AArch64/sve-fixed-vector-lrint.ll | 214 ++++-----
llvm/test/CodeGen/AArch64/vec_uaddo.ll | 2 +-
llvm/test/CodeGen/AArch64/vec_umulo.ll | 2 +-
.../AArch64/vecreduce-and-legalization.ll | 8 +-
llvm/test/CodeGen/AArch64/vecreduce-bitext.ll | 72 +--
llvm/test/CodeGen/AArch64/vecreduce-fmul.ll | 34 +-
.../AArch64/vecreduce-umax-legalization.ll | 2 +-
llvm/test/CodeGen/AArch64/vector-fcvt.ll | 12 +-
llvm/test/CodeGen/AArch64/vector-llrint.ll | 100 ++--
llvm/test/CodeGen/AArch64/vector-lrint.ll | 114 ++---
llvm/test/CodeGen/AArch64/vselect-ext.ll | 8 +-
llvm/test/CodeGen/AArch64/zext-shuffle.ll | 12 +-
llvm/test/CodeGen/AArch64/zext-to-tbl.ll | 32 +-
llvm/test/CodeGen/AArch64/zext.ll | 14 +-
85 files changed, 1081 insertions(+), 1639 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index f20f978fe7e8a..17d2e0e5ee317 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -7559,10 +7559,6 @@ multiclass ExtPat<ValueType VT64, ValueType VT128, int N> {
(EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
def : Pat<(VT128 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
(EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
- // We use EXT to handle extract_subvector to copy the upper 64-bits of a
- // 128-bit vector.
- def : Pat<(VT64 (extract_subvector V128:$Rn, (i64 N))),
- (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
// A 64-bit EXT of two halves of the same 128-bit register can be done as a
// single 128-bit EXT.
def : Pat<(VT64 (AArch64ext (extract_subvector V128:$Rn, (i64 0)),
@@ -10951,14 +10947,22 @@ def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 0))),
def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 0))),
(EXTRACT_SUBREG V128:$Rn, dsub)>;
-def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
- (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
-def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
- (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
-def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
- (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
+def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 8))),
+ (DUPi64 FPR128:$Rn, 1)>;
+def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 4))),
+ (DUPi64 FPR128:$Rn, 1)>;
+def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 2))),
+ (DUPi64 FPR128:$Rn, 1)>;
def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
- (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
+ (DUPi64 FPR128:$Rn, 1)>;
+def : Pat<(v4bf16 (extract_subvector (v8bf16 FPR128:$Rn), (i64 4))),
+ (DUPi64 FPR128:$Rn, 1)>;
+def : Pat<(v4f16 (extract_subvector (v8f16 FPR128:$Rn), (i64 4))),
+ (DUPi64 FPR128:$Rn, 1)>;
+def : Pat<(v2f32 (extract_subvector (v4f32 FPR128:$Rn), (i64 2))),
+ (DUPi64 FPR128:$Rn, 1)>;
+def : Pat<(v1f64 (extract_subvector (v2f64 FPR128:$Rn), (i64 1))),
+ (DUPi64 FPR128:$Rn, 1)>;
// A 64-bit subvector insert to the first 128-bit vector position
// is a subregister copy that needs no instruction.
diff --git a/llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll b/llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll
index 2f0ec2b75bfc6..c5a8bba502e22 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll
@@ -604,7 +604,7 @@ entry:
define i64 @sminv_v2i64(<2 x i64> %a) {
; CHECK-SD-NOSVE-LABEL: sminv_v2i64:
; CHECK-SD-NOSVE: // %bb.0: // %entry
-; CHECK-SD-NOSVE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NOSVE-NEXT: mov d1, v0.d[1]
; CHECK-SD-NOSVE-NEXT: cmgt d2, d1, d0
; CHECK-SD-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; CHECK-SD-NOSVE-NEXT: fmov x0, d0
@@ -643,7 +643,7 @@ define i64 @sminv_v3i64(<3 x i64> %a) {
; CHECK-SD-NOSVE-NEXT: mov v2.d[1], x8
; CHECK-SD-NOSVE-NEXT: cmgt v1.2d, v2.2d, v0.2d
; CHECK-SD-NOSVE-NEXT: bif v0.16b, v2.16b, v1.16b
-; CHECK-SD-NOSVE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NOSVE-NEXT: mov d1, v0.d[1]
; CHECK-SD-NOSVE-NEXT: cmgt d2, d1, d0
; CHECK-SD-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; CHECK-SD-NOSVE-NEXT: fmov x0, d0
@@ -690,7 +690,7 @@ define i64 @sminv_v4i64(<4 x i64> %a) {
; CHECK-SD-NOSVE: // %bb.0: // %entry
; CHECK-SD-NOSVE-NEXT: cmgt v2.2d, v1.2d, v0.2d
; CHECK-SD-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-SD-NOSVE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NOSVE-NEXT: mov d1, v0.d[1]
; CHECK-SD-NOSVE-NEXT: cmgt d2, d1, d0
; CHECK-SD-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; CHECK-SD-NOSVE-NEXT: fmov x0, d0
@@ -996,7 +996,7 @@ entry:
define i64 @smaxv_v2i64(<2 x i64> %a) {
; CHECK-SD-NOSVE-LABEL: smaxv_v2i64:
; CHECK-SD-NOSVE: // %bb.0: // %entry
-; CHECK-SD-NOSVE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NOSVE-NEXT: mov d1, v0.d[1]
; CHECK-SD-NOSVE-NEXT: cmgt d2, d0, d1
; CHECK-SD-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; CHECK-SD-NOSVE-NEXT: fmov x0, d0
@@ -1035,7 +1035,7 @@ define i64 @smaxv_v3i64(<3 x i64> %a) {
; CHECK-SD-NOSVE-NEXT: mov v2.d[1], x8
; CHECK-SD-NOSVE-NEXT: cmgt v1.2d, v0.2d, v2.2d
; CHECK-SD-NOSVE-NEXT: bif v0.16b, v2.16b, v1.16b
-; CHECK-SD-NOSVE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NOSVE-NEXT: mov d1, v0.d[1]
; CHECK-SD-NOSVE-NEXT: cmgt d2, d0, d1
; CHECK-SD-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; CHECK-SD-NOSVE-NEXT: fmov x0, d0
@@ -1082,7 +1082,7 @@ define i64 @smaxv_v4i64(<4 x i64> %a) {
; CHECK-SD-NOSVE: // %bb.0: // %entry
; CHECK-SD-NOSVE-NEXT: cmgt v2.2d, v0.2d, v1.2d
; CHECK-SD-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-SD-NOSVE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NOSVE-NEXT: mov d1, v0.d[1]
; CHECK-SD-NOSVE-NEXT: cmgt d2, d0, d1
; CHECK-SD-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; CHECK-SD-NOSVE-NEXT: fmov x0, d0
@@ -1386,7 +1386,7 @@ entry:
define i64 @uminv_v2i64(<2 x i64> %a) {
; CHECK-SD-NOSVE-LABEL: uminv_v2i64:
; CHECK-SD-NOSVE: // %bb.0: // %entry
-; CHECK-SD-NOSVE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NOSVE-NEXT: mov d1, v0.d[1]
; CHECK-SD-NOSVE-NEXT: cmhi d2, d1, d0
; CHECK-SD-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; CHECK-SD-NOSVE-NEXT: fmov x0, d0
@@ -1425,7 +1425,7 @@ define i64 @uminv_v3i64(<3 x i64> %a) {
; CHECK-SD-NOSVE-NEXT: mov v2.d[1], x8
; CHECK-SD-NOSVE-NEXT: cmhi v1.2d, v2.2d, v0.2d
; CHECK-SD-NOSVE-NEXT: bif v0.16b, v2.16b, v1.16b
-; CHECK-SD-NOSVE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NOSVE-NEXT: mov d1, v0.d[1]
; CHECK-SD-NOSVE-NEXT: cmhi d2, d1, d0
; CHECK-SD-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; CHECK-SD-NOSVE-NEXT: fmov x0, d0
@@ -1472,7 +1472,7 @@ define i64 @uminv_v4i64(<4 x i64> %a) {
; CHECK-SD-NOSVE: // %bb.0: // %entry
; CHECK-SD-NOSVE-NEXT: cmhi v2.2d, v1.2d, v0.2d
; CHECK-SD-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-SD-NOSVE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NOSVE-NEXT: mov d1, v0.d[1]
; CHECK-SD-NOSVE-NEXT: cmhi d2, d1, d0
; CHECK-SD-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; CHECK-SD-NOSVE-NEXT: fmov x0, d0
@@ -1765,7 +1765,7 @@ entry:
define i64 @umaxv_v2i64(<2 x i64> %a) {
; CHECK-SD-NOSVE-LABEL: umaxv_v2i64:
; CHECK-SD-NOSVE: // %bb.0: // %entry
-; CHECK-SD-NOSVE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NOSVE-NEXT: mov d1, v0.d[1]
; CHECK-SD-NOSVE-NEXT: cmhi d2, d0, d1
; CHECK-SD-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; CHECK-SD-NOSVE-NEXT: fmov x0, d0
@@ -1803,7 +1803,7 @@ define i64 @umaxv_v3i64(<3 x i64> %a) {
; CHECK-SD-NOSVE-NEXT: mov v0.d[1], v1.d[0]
; CHECK-SD-NOSVE-NEXT: mov v3.d[1], xzr
; CHECK-SD-NOSVE-NEXT: cmhi v3.2d, v0.2d, v3.2d
-; CHECK-SD-NOSVE-NEXT: ext v4.16b, v3.16b, v3.16b, #8
+; CHECK-SD-NOSVE-NEXT: mov d4, v3.d[1]
; CHECK-SD-NOSVE-NEXT: bif v0.16b, v2.16b, v3.16b
; CHECK-SD-NOSVE-NEXT: and v1.8b, v1.8b, v4.8b
; CHECK-SD-NOSVE-NEXT: cmhi d2, d0, d1
@@ -1850,7 +1850,7 @@ define i64 @umaxv_v4i64(<4 x i64> %a) {
; CHECK-SD-NOSVE: // %bb.0: // %entry
; CHECK-SD-NOSVE-NEXT: cmhi v2.2d, v0.2d, v1.2d
; CHECK-SD-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-SD-NOSVE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NOSVE-NEXT: mov d1, v0.d[1]
; CHECK-SD-NOSVE-NEXT: cmhi d2, d0, d1
; CHECK-SD-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; CHECK-SD-NOSVE-NEXT: fmov x0, d0
diff --git a/llvm/test/CodeGen/AArch64/aarch64-mulv.ll b/llvm/test/CodeGen/AArch64/aarch64-mulv.ll
index fecc6554667fa..f200444cfa23f 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-mulv.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-mulv.ll
@@ -125,7 +125,7 @@ entry:
define i8 @mulv_v16i8(<16 x i8> %a) {
; CHECK-SD-LABEL: mulv_v16i8:
; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: mul v0.8b, v0.8b, v1.8b
; CHECK-SD-NEXT: umov w8, v0.b[1]
; CHECK-SD-NEXT: umov w9, v0.b[0]
@@ -173,7 +173,7 @@ define i8 @mulv_v32i8(<32 x i8> %a) {
; CHECK-SD-LABEL: mulv_v32i8:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: mul v0.16b, v0.16b, v1.16b
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: mul v0.8b, v0.8b, v1.8b
; CHECK-SD-NEXT: umov w8, v0.b[1]
; CHECK-SD-NEXT: umov w9, v0.b[0]
@@ -290,7 +290,7 @@ entry:
define i16 @mulv_v8i16(<8 x i16> %a) {
; CHECK-SD-LABEL: mulv_v8i16:
; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: mul v0.4h, v0.4h, v1.4h
; CHECK-SD-NEXT: umov w8, v0.h[1]
; CHECK-SD-NEXT: umov w9, v0.h[0]
@@ -322,7 +322,7 @@ define i16 @mulv_v16i16(<16 x i16> %a) {
; CHECK-SD-LABEL: mulv_v16i16:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: mul v0.8h, v0.8h, v1.8h
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: mul v0.4h, v0.4h, v1.4h
; CHECK-SD-NEXT: umov w8, v0.h[1]
; CHECK-SD-NEXT: umov w9, v0.h[0]
@@ -372,7 +372,7 @@ define i32 @mulv_v3i32(<3 x i32> %a) {
; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: mov v1.s[3], w8
-; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT: mov d1, v1.d[1]
; CHECK-NEXT: mul v0.2s, v0.2s, v1.2s
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0
@@ -384,23 +384,14 @@ entry:
}
define i32 @mulv_v4i32(<4 x i32> %a) {
-; CHECK-SD-LABEL: mulv_v4i32:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: mul v0.2s, v0.2s, v1.2s
-; CHECK-SD-NEXT: mov w8, v0.s[1]
-; CHECK-SD-NEXT: fmov w9, s0
-; CHECK-SD-NEXT: mul w0, w9, w8
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: mulv_v4i32:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: mul v0.2s, v0.2s, v1.2s
-; CHECK-GI-NEXT: mov w8, v0.s[1]
-; CHECK-GI-NEXT: fmov w9, s0
-; CHECK-GI-NEXT: mul w0, w9, w8
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: mulv_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov d1, v0.d[1]
+; CHECK-NEXT: mul v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: mov w8, v0.s[1]
+; CHECK-NEXT: fmov w9, s0
+; CHECK-NEXT: mul w0, w9, w8
+; CHECK-NEXT: ret
entry:
%arg1 = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> %a)
ret i32 %arg1
@@ -410,7 +401,7 @@ define i32 @mulv_v8i32(<8 x i32> %a) {
; CHECK-SD-LABEL: mulv_v8i32:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: mul v0.4s, v0.4s, v1.4s
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: mul v0.2s, v0.2s, v1.2s
; CHECK-SD-NEXT: mov w8, v0.s[1]
; CHECK-SD-NEXT: fmov w9, s0
diff --git a/llvm/test/CodeGen/AArch64/aarch64_be-shuffle-vector.ll b/llvm/test/CodeGen/AArch64/aarch64_be-shuffle-vector.ll
index 4e60d99dbed36..f88d88cf1661c 100644
--- a/llvm/test/CodeGen/AArch64/aarch64_be-shuffle-vector.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64_be-shuffle-vector.ll
@@ -6,7 +6,7 @@ define <4 x i16> @test_reconstructshuffle(<16 x i8> %a, <16 x i8> %b) nounwind {
; CHECKLE-LABEL: test_reconstructshuffle:
; CHECKLE: // %bb.0:
; CHECKLE-NEXT: mov b2, v0.b[3]
-; CHECKLE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECKLE-NEXT: mov d1, v1.d[1]
; CHECKLE-NEXT: mov v2.b[2], v0.b[2]
; CHECKLE-NEXT: mov v2.b[4], v0.b[1]
; CHECKLE-NEXT: mov v2.b[6], v0.b[0]
@@ -22,7 +22,7 @@ define <4 x i16> @test_reconstructshuffle(<16 x i8> %a, <16 x i8> %b) nounwind {
; CHECKBE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECKBE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECKBE-NEXT: mov b2, v0.b[3]
-; CHECKBE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECKBE-NEXT: mov d1, v1.d[1]
; CHECKBE-NEXT: mov v2.b[2], v0.b[2]
; CHECKBE-NEXT: mov v2.b[4], v0.b[1]
; CHECKBE-NEXT: mov v2.b[6], v0.b[0]
diff --git a/llvm/test/CodeGen/AArch64/abd-combine.ll b/llvm/test/CodeGen/AArch64/abd-combine.ll
index cdb40ceb46b1e..d632648bbcd11 100644
--- a/llvm/test/CodeGen/AArch64/abd-combine.ll
+++ b/llvm/test/CodeGen/AArch64/abd-combine.ll
@@ -340,7 +340,7 @@ define <8 x i16> @abds_const_lhs(<8 x i16> %src1) {
define <8 x i16> @abds_const_zero(<8 x i16> %src1) {
; CHECK-LABEL: abds_const_zero:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: abs v0.4h, v0.4h
; CHECK-NEXT: abs v1.4h, v1.4h
; CHECK-NEXT: mov v0.d[1], v1.d[0]
diff --git a/llvm/test/CodeGen/AArch64/add-extract.ll b/llvm/test/CodeGen/AArch64/add-extract.ll
index 923bf089f47ba..002b8e52f4199 100644
--- a/llvm/test/CodeGen/AArch64/add-extract.ll
+++ b/llvm/test/CodeGen/AArch64/add-extract.ll
@@ -120,7 +120,7 @@ define i32 @add_i32_ext_load(<1 x i32> %A, ptr %B) nounwind {
define i64 @add_i64_ext_ext_test1(<1 x i64> %A, <2 x i64> %B) nounwind {
; CHECK-SD-LABEL: add_i64_ext_ext_test1:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-SD-NEXT: mov d2, v1.d[1]
; CHECK-SD-NEXT: add d0, d0, d1
; CHECK-SD-NEXT: add d0, d0, d2
; CHECK-SD-NEXT: fmov x0, d0
@@ -145,7 +145,7 @@ define i64 @add_i64_ext_ext_test1(<1 x i64> %A, <2 x i64> %B) nounwind {
define i64 @sub_i64_ext_ext_test1(<1 x i64> %A, <2 x i64> %B) nounwind {
; CHECK-SD-LABEL: sub_i64_ext_ext_test1:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-SD-NEXT: mov d2, v1.d[1]
; CHECK-SD-NEXT: sub d0, d0, d1
; CHECK-SD-NEXT: sub d0, d0, d2
; CHECK-SD-NEXT: fmov x0, d0
diff --git a/llvm/test/CodeGen/AArch64/arm64-ext.ll b/llvm/test/CodeGen/AArch64/arm64-ext.ll
index c3670579c9148..3194fe1d9a9bc 100644
--- a/llvm/test/CodeGen/AArch64/arm64-ext.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-ext.ll
@@ -101,7 +101,7 @@ define <8 x i16> @test_vextRq_undef2(<8 x i16> %tmp1) nounwind {
define <4 x i16> @test_undef(<8 x i16> %tmp1, <8 x i16> %tmp2) {
; CHECK-SD-LABEL: test_undef:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d0, v0.d[1]
; CHECK-SD-NEXT: zip1 v0.4h, v0.4h, v1.4h
; CHECK-SD-NEXT: ret
;
diff --git a/llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll b/llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll
index f08ff2ccf693d..2647993e52de1 100644
--- a/llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll
@@ -7,8 +7,7 @@
define <8 x i8> @v8i8(<16 x i8> %a) nounwind {
; CHECK-SD-LABEL: v8i8:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext.16b v0, v0, v0, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: mov d0, v0[1]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v8i8:
@@ -22,8 +21,7 @@ define <8 x i8> @v8i8(<16 x i8> %a) nounwind {
define <4 x i16> @v4i16(<8 x i16> %a) nounwind {
; CHECK-SD-LABEL: v4i16:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext.16b v0, v0, v0, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: mov d0, v0[1]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v4i16:
@@ -37,8 +35,7 @@ define <4 x i16> @v4i16(<8 x i16> %a) nounwind {
define <2 x i32> @v2i32(<4 x i32> %a) nounwind {
; CHECK-SD-LABEL: v2i32:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext.16b v0, v0, v0, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: mov d0, v0[1]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2i32:
@@ -52,8 +49,7 @@ define <2 x i32> @v2i32(<4 x i32> %a) nounwind {
define <1 x i64> @v1i64(<2 x i64> %a) nounwind {
; CHECK-SD-LABEL: v1i64:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext.16b v0, v0, v0, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: mov d0, v0[1]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v1i64:
@@ -67,8 +63,7 @@ define <1 x i64> @v1i64(<2 x i64> %a) nounwind {
define <1 x ptr> @v1p0(<2 x ptr> %a) nounwind {
; CHECK-SD-LABEL: v1p0:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext.16b v0, v0, v0, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: mov d0, v0[1]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v1p0:
@@ -82,8 +77,7 @@ define <1 x ptr> @v1p0(<2 x ptr> %a) nounwind {
define <2 x float> @v2f32(<4 x float> %a) nounwind {
; CHECK-SD-LABEL: v2f32:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext.16b v0, v0, v0, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: mov d0, v0[1]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2f32:
@@ -97,8 +91,7 @@ define <2 x float> @v2f32(<4 x float> %a) nounwind {
define <1 x double> @v1f64(<2 x double> %a) nounwind {
; CHECK-SD-LABEL: v1f64:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext.16b v0, v0, v0, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: mov d0, v0[1]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v1f64:
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
index 4f3666c58d317..18d745939e478 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
@@ -284,16 +284,10 @@ define <2 x float> @ins4f2(<4 x float> %tmp1, <2 x float> %tmp2) {
}
define <1 x double> @ins2f1(<2 x double> %tmp1, <1 x double> %tmp2) {
-; CHECK-SD-LABEL: ins2f1:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: ins2f1:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d0, v0.d[1]
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: ins2f1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov d0, v0.d[1]
+; CHECK-NEXT: ret
%tmp3 = extractelement <2 x double> %tmp1, i32 1
%tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0
ret <1 x double> %tmp4
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-simd-vget.ll b/llvm/test/CodeGen/AArch64/arm64-neon-simd-vget.ll
index 96d5b5ef85415..dbf19b1d6fa57 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-simd-vget.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-simd-vget.ll
@@ -4,8 +4,7 @@
define <8 x i8> @test_vget_high_s8(<16 x i8> %a) {
; CHECK-LABEL: test_vget_high_s8:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -15,8 +14,7 @@ entry:
define <4 x i16> @test_vget_high_s16(<8 x i16> %a) {
; CHECK-LABEL: test_vget_high_s16:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -26,8 +24,7 @@ entry:
define <2 x i32> @test_vget_high_s32(<4 x i32> %a) {
; CHECK-LABEL: test_vget_high_s32:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -37,8 +34,7 @@ entry:
define <1 x i64> @test_vget_high_s64(<2 x i64> %a) {
; CHECK-LABEL: test_vget_high_s64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <2 x i64> %a, <2 x i64> undef, <1 x i32> <i32 1>
@@ -48,8 +44,7 @@ entry:
define <8 x i8> @test_vget_high_u8(<16 x i8> %a) {
; CHECK-LABEL: test_vget_high_u8:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -59,8 +54,7 @@ entry:
define <4 x i16> @test_vget_high_u16(<8 x i16> %a) {
; CHECK-LABEL: test_vget_high_u16:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -70,8 +64,7 @@ entry:
define <2 x i32> @test_vget_high_u32(<4 x i32> %a) {
; CHECK-LABEL: test_vget_high_u32:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -81,8 +74,7 @@ entry:
define <1 x i64> @test_vget_high_u64(<2 x i64> %a) {
; CHECK-LABEL: test_vget_high_u64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <2 x i64> %a, <2 x i64> undef, <1 x i32> <i32 1>
@@ -92,8 +84,7 @@ entry:
define <1 x i64> @test_vget_high_p64(<2 x i64> %a) {
; CHECK-LABEL: test_vget_high_p64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <2 x i64> %a, <2 x i64> undef, <1 x i32> <i32 1>
@@ -103,8 +94,7 @@ entry:
define <4 x i16> @test_vget_high_f16(<8 x i16> %a) {
; CHECK-LABEL: test_vget_high_f16:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -114,8 +104,7 @@ entry:
define <2 x float> @test_vget_high_f32(<4 x float> %a) {
; CHECK-LABEL: test_vget_high_f32:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 2, i32 3>
@@ -125,8 +114,7 @@ entry:
define <8 x i8> @test_vget_high_p8(<16 x i8> %a) {
; CHECK-LABEL: test_vget_high_p8:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -136,8 +124,7 @@ entry:
define <4 x i16> @test_vget_high_p16(<8 x i16> %a) {
; CHECK-LABEL: test_vget_high_p16:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -147,8 +134,7 @@ entry:
define <1 x double> @test_vget_high_f64(<2 x double> %a) {
; CHECK-LABEL: test_vget_high_f64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <2 x double> %a, <2 x double> undef, <1 x i32> <i32 1>
diff --git a/llvm/test/CodeGen/AArch64/bf16-shuffle.ll b/llvm/test/CodeGen/AArch64/bf16-shuffle.ll
index d59de3c56f4ee..26a2f9d5299db 100644
--- a/llvm/test/CodeGen/AArch64/bf16-shuffle.ll
+++ b/llvm/test/CodeGen/AArch64/bf16-shuffle.ll
@@ -201,8 +201,7 @@ entry:
define dso_local <4 x bfloat> @test_vext_aligned_bf16(<8 x bfloat> %a) {
; CHECK-LABEL: test_vext_aligned_bf16:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
entry:
%vext = shufflevector <8 x bfloat> %a, <8 x bfloat> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
diff --git a/llvm/test/CodeGen/AArch64/bf16-vector-shuffle.ll b/llvm/test/CodeGen/AArch64/bf16-vector-shuffle.ll
index 222d7435ff742..9e13201692db6 100644
--- a/llvm/test/CodeGen/AArch64/bf16-vector-shuffle.ll
+++ b/llvm/test/CodeGen/AArch64/bf16-vector-shuffle.ll
@@ -101,8 +101,7 @@ entry:
define <4 x bfloat> @test_vget_high_bf16(<8 x bfloat> %a) nounwind {
; CHECK-LABEL: test_vget_high_bf16:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <8 x bfloat> %a, <8 x bfloat> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
diff --git a/llvm/test/CodeGen/AArch64/clmul-fixed.ll b/llvm/test/CodeGen/AArch64/clmul-fixed.ll
index 70ddde74aafbc..c0d1116230067 100644
--- a/llvm/test/CodeGen/AArch64/clmul-fixed.ll
+++ b/llvm/test/CodeGen/AArch64/clmul-fixed.ll
@@ -2811,8 +2811,8 @@ define <8 x i16> @clmul_v8i16_neon_zext(<8 x i8> %x, <8 x i8> %y) {
define <16 x i16> @clmul_v16i16_neon_zext(<16 x i8> %x, <16 x i8> %y) {
; CHECK-LABEL: clmul_v16i16_neon_zext:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT: mov d2, v0.d[1]
+; CHECK-NEXT: mov d3, v1.d[1]
; CHECK-NEXT: rbit v4.8b, v1.8b
; CHECK-NEXT: rbit v5.8b, v0.8b
; CHECK-NEXT: pmul v0.8b, v0.8b, v1.8b
@@ -2928,8 +2928,8 @@ define <8 x i32> @clmul_v8i32_neon_zext(<8 x i16> %x, <8 x i16> %y) {
; CHECK-NEXT: .cfi_offset b10, -24
; CHECK-NEXT: .cfi_offset b11, -32
; CHECK-NEXT: .cfi_offset b12, -48
-; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT: mov d2, v0.d[1]
+; CHECK-NEXT: mov d3, v1.d[1]
; CHECK-NEXT: rev16 v5.8b, v1.8b
; CHECK-NEXT: rev16 v6.8b, v0.8b
; CHECK-NEXT: movi v4.2d, #0000000000000000
@@ -5456,8 +5456,8 @@ define <2 x i128> @clmul_v2i128_neon_zext(<2 x i64> %x, <2 x i64> %y) {
; CHECK-AES-NEXT: fmov x11, d1
; CHECK-AES-NEXT: mov x8, v0.d[1]
; CHECK-AES-NEXT: mov x9, v1.d[1]
-; CHECK-AES-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-AES-NEXT: ext v3.16b, v0.16b, v0.16b, #8
+; CHECK-AES-NEXT: mov d2, v1.d[1]
+; CHECK-AES-NEXT: mov d3, v0.d[1]
; CHECK-AES-NEXT: pmull v0.1q, v0.1d, v1.1d
; CHECK-AES-NEXT: rbit x11, x11
; CHECK-AES-NEXT: rbit x10, x10
diff --git a/llvm/test/CodeGen/AArch64/combine-storetomstore.ll b/llvm/test/CodeGen/AArch64/combine-storetomstore.ll
index d4244fedf7504..b0026f79403d6 100644
--- a/llvm/test/CodeGen/AArch64/combine-storetomstore.ll
+++ b/llvm/test/CodeGen/AArch64/combine-storetomstore.ll
@@ -347,7 +347,7 @@ define void @test_masked_store_success_v16i16(<16 x i16> %x, ptr %ptr, <16 x i1>
define void @test_masked_store_success_v16i32(<16 x i32> %x, ptr %ptr, <16 x i1> %mask) {
; SVE-LABEL: test_masked_store_success_v16i32:
; SVE: // %bb.0:
-; SVE-NEXT: ext v5.16b, v4.16b, v4.16b, #8
+; SVE-NEXT: mov d5, v4.d[1]
; SVE-NEXT: // kill: def $q0 killed $q0 def $z0
; SVE-NEXT: zip2 v6.8b, v4.8b, v0.8b
; SVE-NEXT: mov x8, #4 // =0x4
@@ -751,7 +751,7 @@ define void @test_masked_store_success_invert_mask_v8i32(<8 x i32> %x, ptr %ptr,
define void @test_masked_store_success_invert_mask_v16i32(<16 x i32> %x, ptr %ptr, <16 x i1> %mask) {
; SVE-LABEL: test_masked_store_success_invert_mask_v16i32:
; SVE: // %bb.0:
-; SVE-NEXT: ext v5.16b, v4.16b, v4.16b, #8
+; SVE-NEXT: mov d5, v4.d[1]
; SVE-NEXT: // kill: def $q0 killed $q0 def $z0
; SVE-NEXT: zip2 v6.8b, v4.8b, v0.8b
; SVE-NEXT: mov x8, #4 // =0x4
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-mixed-cases.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-mixed-cases.ll
index 1ed9cf2db24f7..7e0b46107ceea 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-mixed-cases.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-mixed-cases.ll
@@ -44,9 +44,9 @@ define <4 x float> @add_mul(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fsub v0.4s, v1.4s, v0.4s
; CHECK-NEXT: fsub v1.4s, v1.4s, v2.4s
-; CHECK-NEXT: ext v3.16b, v2.16b, v2.16b, #8
-; CHECK-NEXT: ext v4.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: ext v5.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT: mov d3, v2.d[1]
+; CHECK-NEXT: mov d4, v0.d[1]
+; CHECK-NEXT: mov d5, v1.d[1]
; CHECK-NEXT: zip2 v0.2s, v0.2s, v4.2s
; CHECK-NEXT: zip2 v4.2s, v2.2s, v3.2s
; CHECK-NEXT: zip1 v1.2s, v1.2s, v5.2s
@@ -79,13 +79,13 @@ entry:
define <4 x float> @mul_mul270_mul(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
; CHECK-LABEL: mul_mul270_mul:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v3.16b, v2.16b, v2.16b, #8
-; CHECK-NEXT: ext v4.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT: mov d3, v2.d[1]
+; CHECK-NEXT: mov d4, v1.d[1]
; CHECK-NEXT: zip1 v5.2s, v2.2s, v3.2s
; CHECK-NEXT: zip1 v6.2s, v1.2s, v4.2s
; CHECK-NEXT: zip2 v2.2s, v2.2s, v3.2s
; CHECK-NEXT: zip2 v1.2s, v1.2s, v4.2s
-; CHECK-NEXT: ext v3.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d3, v0.d[1]
; CHECK-NEXT: fmul v7.2s, v6.2s, v5.2s
; CHECK-NEXT: fneg v4.2s, v7.2s
; CHECK-NEXT: zip2 v7.2s, v0.2s, v3.2s
@@ -258,12 +258,12 @@ entry:
define <4 x float> @mul_triangle_addmul(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
; CHECK-LABEL: mul_triangle_addmul:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v3.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: ext v4.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT: mov d3, v0.d[1]
+; CHECK-NEXT: mov d4, v1.d[1]
; CHECK-NEXT: zip1 v5.2s, v0.2s, v3.2s
; CHECK-NEXT: zip1 v6.2s, v1.2s, v4.2s
; CHECK-NEXT: zip2 v1.2s, v1.2s, v4.2s
-; CHECK-NEXT: ext v4.16b, v2.16b, v2.16b, #8
+; CHECK-NEXT: mov d4, v2.d[1]
; CHECK-NEXT: zip2 v0.2s, v0.2s, v3.2s
; CHECK-NEXT: fmul v7.2s, v6.2s, v5.2s
; CHECK-NEXT: fmul v5.2s, v1.2s, v5.2s
@@ -311,8 +311,8 @@ entry:
define <4 x float> @mul_triangle_multiuses(<4 x float> %a, <4 x float> %b, ptr %p) {
; CHECK-LABEL: mul_triangle_multiuses:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT: mov d2, v0.d[1]
+; CHECK-NEXT: mov d3, v1.d[1]
; CHECK-NEXT: zip2 v4.2s, v0.2s, v2.2s
; CHECK-NEXT: zip1 v5.2s, v1.2s, v3.2s
; CHECK-NEXT: zip1 v0.2s, v0.2s, v2.2s
@@ -442,13 +442,13 @@ entry:
define <4 x float> @mul_divequal(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
; CHECK-LABEL: mul_divequal:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v3.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: ext v4.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT: mov d3, v0.d[1]
+; CHECK-NEXT: mov d4, v1.d[1]
; CHECK-NEXT: zip2 v5.2s, v0.2s, v3.2s
; CHECK-NEXT: zip2 v6.2s, v1.2s, v4.2s
; CHECK-NEXT: zip1 v0.2s, v0.2s, v3.2s
; CHECK-NEXT: zip1 v1.2s, v1.2s, v4.2s
-; CHECK-NEXT: ext v3.16b, v2.16b, v2.16b, #8
+; CHECK-NEXT: mov d3, v2.d[1]
; CHECK-NEXT: fmul v7.2s, v5.2s, v6.2s
; CHECK-NEXT: fneg v4.2s, v7.2s
; CHECK-NEXT: zip1 v7.2s, v2.2s, v3.2s
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll
index 039025dafa0d6..8cb1ac4ae548a 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll
@@ -46,8 +46,8 @@ entry:
define <4 x float> @mul_triangle_external_use(<4 x float> %a, <4 x float> %b, ptr %p) {
; CHECK-LABEL: mul_triangle_external_use:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT: mov d2, v0.d[1]
+; CHECK-NEXT: mov d3, v1.d[1]
; CHECK-NEXT: zip2 v4.2s, v0.2s, v2.2s
; CHECK-NEXT: zip1 v5.2s, v1.2s, v3.2s
; CHECK-NEXT: zip1 v0.2s, v0.2s, v2.2s
@@ -94,9 +94,9 @@ entry:
define <4 x float> @multiple_muls_shuffle_external(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, ptr %p1, ptr %p2) {
; CHECK-LABEL: multiple_muls_shuffle_external:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v5.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: ext v6.16b, v1.16b, v1.16b, #8
-; CHECK-NEXT: ext v4.16b, v2.16b, v2.16b, #8
+; CHECK-NEXT: mov d5, v0.d[1]
+; CHECK-NEXT: mov d6, v1.d[1]
+; CHECK-NEXT: mov d4, v2.d[1]
; CHECK-NEXT: zip2 v7.2s, v0.2s, v5.2s
; CHECK-NEXT: zip1 v16.2s, v1.2s, v6.2s
; CHECK-NEXT: zip2 v1.2s, v1.2s, v6.2s
@@ -168,7 +168,7 @@ define <4 x float> @multiple_muls_shuffle_external_with_loads(ptr %ptr_a, ptr %p
; CHECK-NEXT: fmla v4.2s, v0.2s, v2.2s
; CHECK-NEXT: str d4, [x4]
; CHECK-NEXT: ldr q5, [x2]
-; CHECK-NEXT: ext v7.16b, v5.16b, v5.16b, #8
+; CHECK-NEXT: mov d7, v5.d[1]
; CHECK-NEXT: zip1 v0.2s, v5.2s, v7.2s
; CHECK-NEXT: zip2 v1.2s, v5.2s, v7.2s
; CHECK-NEXT: fmul v3.2s, v0.2s, v6.2s
@@ -227,10 +227,10 @@ entry:
define <4 x float> @multiple_muls_mul_external(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, ptr %p1, ptr %p2) {
; CHECK-LABEL: multiple_muls_mul_external:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v4.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: ext v5.16b, v1.16b, v1.16b, #8
-; CHECK-NEXT: ext v16.16b, v2.16b, v2.16b, #8
-; CHECK-NEXT: ext v17.16b, v3.16b, v3.16b, #8
+; CHECK-NEXT: mov d4, v0.d[1]
+; CHECK-NEXT: mov d5, v1.d[1]
+; CHECK-NEXT: mov d16, v2.d[1]
+; CHECK-NEXT: mov d17, v3.d[1]
; CHECK-NEXT: zip2 v6.2s, v0.2s, v4.2s
; CHECK-NEXT: zip2 v7.2s, v1.2s, v5.2s
; CHECK-NEXT: zip1 v19.2s, v2.2s, v16.2s
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll
index 13434fabefa78..09c2e481b0433 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll
@@ -31,8 +31,8 @@ entry:
define <4 x float> @simple_mul_no_contract(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: simple_mul_no_contract:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT: mov d2, v0.d[1]
+; CHECK-NEXT: mov d3, v1.d[1]
; CHECK-NEXT: zip1 v4.2s, v0.2s, v2.2s
; CHECK-NEXT: zip2 v0.2s, v0.2s, v2.2s
; CHECK-NEXT: zip1 v2.2s, v1.2s, v3.2s
@@ -149,8 +149,8 @@ entry:
define <4 x float> @add_external_use(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: add_external_use:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT: mov d2, v0.d[1]
+; CHECK-NEXT: mov d3, v1.d[1]
; CHECK-NEXT: zip1 v4.2s, v0.2s, v2.2s
; CHECK-NEXT: zip2 v0.2s, v0.2s, v2.2s
; CHECK-NEXT: zip1 v2.2s, v1.2s, v3.2s
diff --git a/llvm/test/CodeGen/AArch64/concat-vector.ll b/llvm/test/CodeGen/AArch64/concat-vector.ll
index e6e863b074592..385ec6710185b 100644
--- a/llvm/test/CodeGen/AArch64/concat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/concat-vector.ll
@@ -349,17 +349,11 @@ entry:
}
define <8 x i16> @concat_low_high_v8i16(<8 x i16> %a_vec, <8 x i16> %b_vec) {
-; CHECK-SD-LABEL: concat_low_high_v8i16:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: concat_low_high_v8i16:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: concat_low_high_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov d1, v1.d[1]
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ret
entry:
%shuffle.i3 = shufflevector <8 x i16> %a_vec, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%shuffle.i = shufflevector <8 x i16> %b_vec, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
diff --git a/llvm/test/CodeGen/AArch64/ctlz.ll b/llvm/test/CodeGen/AArch64/ctlz.ll
index 5740eaa977875..a1b6f1b931808 100644
--- a/llvm/test/CodeGen/AArch64/ctlz.ll
+++ b/llvm/test/CodeGen/AArch64/ctlz.ll
@@ -343,10 +343,9 @@ define <3 x i64> @v3i64(<3 x i64> %d) {
; CHECK-SD-NEXT: uaddlp v1.8h, v1.16b
; CHECK-SD-NEXT: uaddlp v0.2d, v0.4s
; CHECK-SD-NEXT: uaddlp v2.4s, v1.8h
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: uaddlp v2.2d, v2.4s
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-SD-NEXT: ret
;
diff --git a/llvm/test/CodeGen/AArch64/ctpop.ll b/llvm/test/CodeGen/AArch64/ctpop.ll
index be62efca6cb6a..61a9d84ad2622 100644
--- a/llvm/test/CodeGen/AArch64/ctpop.ll
+++ b/llvm/test/CodeGen/AArch64/ctpop.ll
@@ -311,9 +311,8 @@ define <3 x i64> @v3i64(<3 x i64> %d) {
; CHECK-SD-NEXT: uaddlp v0.4s, v0.8h
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-SD-NEXT: uaddlp v0.2d, v0.4s
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v3i64:
diff --git a/llvm/test/CodeGen/AArch64/cttz.ll b/llvm/test/CodeGen/AArch64/cttz.ll
index b04e8df455357..ef8bee9c10572 100644
--- a/llvm/test/CodeGen/AArch64/cttz.ll
+++ b/llvm/test/CodeGen/AArch64/cttz.ll
@@ -494,9 +494,8 @@ define <3 x i64> @v3i64(<3 x i64> %d) {
; CHECK-SD-NEXT: uaddlp v0.2d, v0.4s
; CHECK-SD-NEXT: uaddlp v2.2d, v2.4s
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v3i64:
diff --git a/llvm/test/CodeGen/AArch64/double_reduct.ll b/llvm/test/CodeGen/AArch64/double_reduct.ll
index e231b91f1199b..2277b64e61975 100644
--- a/llvm/test/CodeGen/AArch64/double_reduct.ll
+++ b/llvm/test/CodeGen/AArch64/double_reduct.ll
@@ -53,7 +53,7 @@ define float @fmul_f32(<8 x float> %a, <4 x float> %b) {
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: fmul v0.4s, v0.4s, v1.4s
; CHECK-SD-NEXT: fmul v0.4s, v0.4s, v2.4s
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: fmul v0.2s, v0.2s, v1.2s
; CHECK-SD-NEXT: fmul s0, s0, v0.s[1]
; CHECK-SD-NEXT: ret
@@ -81,7 +81,7 @@ define float @fmul_f32_same(<4 x float> %a, <4 x float> %b) {
; CHECK-SD-LABEL: fmul_f32_same:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: fmul v0.4s, v0.4s, v1.4s
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: fmul v0.2s, v0.2s, v1.2s
; CHECK-SD-NEXT: fmul s0, s0, v0.s[1]
; CHECK-SD-NEXT: ret
@@ -376,7 +376,7 @@ define i32 @mul_i32(<8 x i32> %a, <4 x i32> %b) {
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-SD-NEXT: mul v0.4s, v0.4s, v2.4s
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: mul v0.2s, v0.2s, v1.2s
; CHECK-SD-NEXT: mov w8, v0.s[1]
; CHECK-SD-NEXT: fmov w9, s0
@@ -410,7 +410,7 @@ define i32 @mul_i32_same(<4 x i32> %a, <4 x i32> %b) {
; CHECK-SD-LABEL: mul_i32_same:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mul v0.4s, v0.4s, v1.4s
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: mul v0.2s, v0.2s, v1.2s
; CHECK-SD-NEXT: mov w8, v0.s[1]
; CHECK-SD-NEXT: fmov w9, s0
@@ -442,7 +442,7 @@ define i32 @and_i32(<8 x i32> %a, <4 x i32> %b) {
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-SD-NEXT: fmov x8, d0
; CHECK-SD-NEXT: lsr x9, x8, #32
@@ -474,7 +474,7 @@ define i32 @and_i32_same(<4 x i32> %a, <4 x i32> %b) {
; CHECK-SD-LABEL: and_i32_same:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-SD-NEXT: fmov x8, d0
; CHECK-SD-NEXT: lsr x9, x8, #32
@@ -506,7 +506,7 @@ define i32 @or_i32(<8 x i32> %a, <4 x i32> %b) {
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-SD-NEXT: fmov x8, d0
; CHECK-SD-NEXT: lsr x9, x8, #32
@@ -538,7 +538,7 @@ define i32 @or_i32_same(<4 x i32> %a, <4 x i32> %b) {
; CHECK-SD-LABEL: or_i32_same:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-SD-NEXT: fmov x8, d0
; CHECK-SD-NEXT: lsr x9, x8, #32
@@ -570,7 +570,7 @@ define i32 @xor_i32(<8 x i32> %a, <4 x i32> %b) {
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: eor v0.16b, v0.16b, v1.16b
; CHECK-SD-NEXT: eor v0.16b, v0.16b, v2.16b
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-SD-NEXT: fmov x8, d0
; CHECK-SD-NEXT: lsr x9, x8, #32
@@ -602,7 +602,7 @@ define i32 @xor_i32_same(<4 x i32> %a, <4 x i32> %b) {
; CHECK-SD-LABEL: xor_i32_same:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: eor v0.16b, v0.16b, v1.16b
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-SD-NEXT: fmov x8, d0
; CHECK-SD-NEXT: lsr x9, x8, #32
@@ -905,7 +905,7 @@ define float @nested_mul_f32(<4 x float> %a, <4 x float> %b, float %c, float %d)
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: fmul v0.4s, v0.4s, v1.4s
; CHECK-SD-NEXT: fmul s2, s2, s3
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: fmul v0.2s, v0.2s, v1.2s
; CHECK-SD-NEXT: fmul s0, s0, v0.s[1]
; CHECK-SD-NEXT: fmul s0, s0, s2
@@ -1056,7 +1056,7 @@ define i32 @nested_mul_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-SD-NEXT: mul w8, w0, w1
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: mul v0.2s, v0.2s, v1.2s
; CHECK-SD-NEXT: mov w9, v0.s[1]
; CHECK-SD-NEXT: fmov w10, s0
@@ -1093,7 +1093,7 @@ define i32 @nested_and_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-SD-NEXT: and w8, w0, w1
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-SD-NEXT: fmov x9, d0
; CHECK-SD-NEXT: lsr x10, x9, #32
@@ -1130,7 +1130,7 @@ define i32 @nested_or_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-SD-NEXT: orr w8, w0, w1
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-SD-NEXT: fmov x9, d0
; CHECK-SD-NEXT: lsr x10, x9, #32
@@ -1167,7 +1167,7 @@ define i32 @nested_xor_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: eor v0.16b, v0.16b, v1.16b
; CHECK-SD-NEXT: eor w8, w0, w1
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-SD-NEXT: fmov x9, d0
; CHECK-SD-NEXT: lsr x10, x9, #32
diff --git a/llvm/test/CodeGen/AArch64/ext-narrow-index.ll b/llvm/test/CodeGen/AArch64/ext-narrow-index.ll
index f62cfef9baf28..e275bd1fb9241 100644
--- a/llvm/test/CodeGen/AArch64/ext-narrow-index.ll
+++ b/llvm/test/CodeGen/AArch64/ext-narrow-index.ll
@@ -28,16 +28,10 @@ entry:
}
define <8 x i8> @i8_off8(<16 x i8> %arg1, <16 x i8> %arg2) {
-; CHECK-SD-LABEL: i8_off8:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GISEL-LABEL: i8_off8:
-; CHECK-GISEL: // %bb.0: // %entry
-; CHECK-GISEL-NEXT: mov d0, v0.d[1]
-; CHECK-GISEL-NEXT: ret
+; CHECK-LABEL: i8_off8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov d0, v0.d[1]
+; CHECK-NEXT: ret
entry:
%shuffle = shufflevector <16 x i8> %arg1, <16 x i8> %arg2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <8 x i8> %shuffle
@@ -171,16 +165,10 @@ entry:
}
define <1 x i64> @i64_off1(<2 x i64> %arg1, <2 x i64> %arg2) {
-; CHECK-SD-LABEL: i64_off1:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GISEL-LABEL: i64_off1:
-; CHECK-GISEL: // %bb.0: // %entry
-; CHECK-GISEL-NEXT: mov d0, v0.d[1]
-; CHECK-GISEL-NEXT: ret
+; CHECK-LABEL: i64_off1:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov d0, v0.d[1]
+; CHECK-NEXT: ret
entry:
%shuffle = shufflevector <2 x i64> %arg1, <2 x i64> %arg2, <1 x i32> <i32 1>
ret <1 x i64> %shuffle
@@ -220,16 +208,10 @@ entry:
}
define <8 x i8> @i8_zero_off8(<16 x i8> %arg1) {
-; CHECK-SD-LABEL: i8_zero_off8:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GISEL-LABEL: i8_zero_off8:
-; CHECK-GISEL: // %bb.0: // %entry
-; CHECK-GISEL-NEXT: mov d0, v0.d[1]
-; CHECK-GISEL-NEXT: ret
+; CHECK-LABEL: i8_zero_off8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov d0, v0.d[1]
+; CHECK-NEXT: ret
entry:
%shuffle = shufflevector <16 x i8> %arg1, <16 x i8> zeroinitializer, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <8 x i8> %shuffle
@@ -364,16 +346,10 @@ entry:
}
define <1 x i64> @i64_zero_off1(<2 x i64> %arg1) {
-; CHECK-SD-LABEL: i64_zero_off1:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GISEL-LABEL: i64_zero_off1:
-; CHECK-GISEL: // %bb.0: // %entry
-; CHECK-GISEL-NEXT: mov d0, v0.d[1]
-; CHECK-GISEL-NEXT: ret
+; CHECK-LABEL: i64_zero_off1:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov d0, v0.d[1]
+; CHECK-NEXT: ret
entry:
%shuffle = shufflevector <2 x i64> %arg1, <2 x i64> zeroinitializer, <1 x i32> <i32 1>
ret <1 x i64> %shuffle
diff --git a/llvm/test/CodeGen/AArch64/extract-subvec-combine.ll b/llvm/test/CodeGen/AArch64/extract-subvec-combine.ll
index 368103bf2f2fe..2779f535adc4b 100644
--- a/llvm/test/CodeGen/AArch64/extract-subvec-combine.ll
+++ b/llvm/test/CodeGen/AArch64/extract-subvec-combine.ll
@@ -44,15 +44,14 @@ define <2 x i32> @and_extract_zext_idx2(<4 x i16> %vec) nounwind {
; CHECK-SD-LABEL: and_extract_zext_idx2:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: mov d0, v0.d[1]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: and_extract_zext_idx2:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-GI-NEXT: movi d1, #0x00ffff0000ffff
-; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-GI-NEXT: mov d0, v0.d[1]
; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: ret
%zext = zext <4 x i16> %vec to <4 x i32>
@@ -65,15 +64,14 @@ define <4 x i16> @and_extract_sext_idx4(<8 x i8> %vec) nounwind {
; CHECK-SD-LABEL: and_extract_sext_idx4:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: mov d0, v0.d[1]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: and_extract_sext_idx4:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff
-; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-GI-NEXT: mov d0, v0.d[1]
; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: ret
%sext = sext <8 x i8> %vec to <8 x i16>
@@ -148,14 +146,13 @@ define <2 x i32> @sext_extract_zext_idx2(<4 x i16> %vec) nounwind {
; CHECK-SD-LABEL: sext_extract_zext_idx2:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: sshll v0.4s, v0.4h, #0
-; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: mov d0, v0.d[1]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: sext_extract_zext_idx2:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-GI-NEXT: mov d0, v0.d[1]
; CHECK-GI-NEXT: shl v0.2s, v0.2s, #16
; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #16
; CHECK-GI-NEXT: ret
@@ -170,14 +167,13 @@ define <4 x i16> @sext_extract_sext_idx4(<8 x i8> %vec) nounwind {
; CHECK-SD-LABEL: sext_extract_sext_idx4:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0
-; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: mov d0, v0.d[1]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: sext_extract_sext_idx4:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
-; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-GI-NEXT: mov d0, v0.d[1]
; CHECK-GI-NEXT: shl v0.4h, v0.4h, #8
; CHECK-GI-NEXT: sshr v0.4h, v0.4h, #8
; CHECK-GI-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/extract-vector-elt.ll b/llvm/test/CodeGen/AArch64/extract-vector-elt.ll
index 23bc6e0fb04ea..f05b37435f83c 100644
--- a/llvm/test/CodeGen/AArch64/extract-vector-elt.ll
+++ b/llvm/test/CodeGen/AArch64/extract-vector-elt.ll
@@ -765,7 +765,7 @@ define i32 @extract_v4i32_vector_insert(<4 x i32> %a, <2 x i32> %b, i32 %c) {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
diff --git a/llvm/test/CodeGen/AArch64/f16f32dot-fixed-length-fdot.ll b/llvm/test/CodeGen/AArch64/f16f32dot-fixed-length-fdot.ll
index ab72173755a61..c7cfccb0e7446 100644
--- a/llvm/test/CodeGen/AArch64/f16f32dot-fixed-length-fdot.ll
+++ b/llvm/test/CodeGen/AArch64/f16f32dot-fixed-length-fdot.ll
@@ -52,7 +52,7 @@ define <2 x float> @fixed_fdot(<2 x float> %acc, <4 x half> %a, <4 x half> %b) {
; CHECK-EXPAND-NEXT: fcvtl v2.4s, v2.4h
; CHECK-EXPAND-NEXT: fmul v1.4s, v1.4s, v2.4s
; CHECK-EXPAND-NEXT: fadd v0.2s, v0.2s, v1.2s
-; CHECK-EXPAND-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECK-EXPAND-NEXT: mov d1, v1.d[1]
; CHECK-EXPAND-NEXT: fadd v0.2s, v1.2s, v0.2s
; CHECK-EXPAND-NEXT: ret
;
diff --git a/llvm/test/CodeGen/AArch64/fabs.ll b/llvm/test/CodeGen/AArch64/fabs.ll
index 43e9007073634..ece7bdea5bc06 100644
--- a/llvm/test/CodeGen/AArch64/fabs.ll
+++ b/llvm/test/CodeGen/AArch64/fabs.ll
@@ -77,9 +77,8 @@ define <3 x double> @fabs_v3f64(<3 x double> %a) {
; CHECK-SD-NEXT: fabs v2.2d, v2.2d
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-SD-NEXT: fabs v0.2d, v0.2d
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: fabs_v3f64:
diff --git a/llvm/test/CodeGen/AArch64/faddsub.ll b/llvm/test/CodeGen/AArch64/faddsub.ll
index b15579199a059..51d5ff7e1b5de 100644
--- a/llvm/test/CodeGen/AArch64/faddsub.ll
+++ b/llvm/test/CodeGen/AArch64/faddsub.ll
@@ -79,9 +79,8 @@ define <3 x double> @fadd_v3f64(<3 x double> %a, <3 x double> %b) {
; CHECK-SD-NEXT: fadd v2.2d, v2.2d, v5.2d
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-SD-NEXT: fadd v0.2d, v0.2d, v3.2d
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: fadd_v3f64:
@@ -420,9 +419,8 @@ define <3 x double> @fsub_v3f64(<3 x double> %a, <3 x double> %b) {
; CHECK-SD-NEXT: fsub v2.2d, v2.2d, v5.2d
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-SD-NEXT: fsub v0.2d, v0.2d, v3.2d
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: fsub_v3f64:
diff --git a/llvm/test/CodeGen/AArch64/fcmp.ll b/llvm/test/CodeGen/AArch64/fcmp.ll
index d360a9da7d966..339273a734559 100644
--- a/llvm/test/CodeGen/AArch64/fcmp.ll
+++ b/llvm/test/CodeGen/AArch64/fcmp.ll
@@ -711,8 +711,8 @@ define <3 x double> @v3f128_double(<3 x fp128> %a, <3 x fp128> %b, <3 x double>
; CHECK-SD-NEXT: str q1, [sp, #64] // 16-byte Spill
; CHECK-SD-NEXT: ldp q0, q1, [sp, #112] // 32-byte Folded Reload
; CHECK-SD-NEXT: bl __lttf2
-; CHECK-SD-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload
; CHECK-SD-NEXT: cmp w0, #0
+; CHECK-SD-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload
; CHECK-SD-NEXT: ldp q2, q4, [sp, #64] // 32-byte Folded Reload
; CHECK-SD-NEXT: cset w8, mi
; CHECK-SD-NEXT: sbfx x8, x8, #0, #1
@@ -721,10 +721,9 @@ define <3 x double> @v3f128_double(<3 x fp128> %a, <3 x fp128> %b, <3 x double>
; CHECK-SD-NEXT: bit v0.16b, v1.16b, v2.16b
; CHECK-SD-NEXT: fmov d2, x8
; CHECK-SD-NEXT: bsl v2.16b, v4.16b, v3.16b
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: add sp, sp, #160
; CHECK-SD-NEXT: ret
;
@@ -829,9 +828,8 @@ define <3 x double> @v3f64_double(<3 x double> %a, <3 x double> %b, <3 x double>
; CHECK-SD-NEXT: bsl v2.16b, v17.16b, v16.16b
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-SD-NEXT: bsl v0.16b, v6.16b, v1.16b
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v3f64_double:
diff --git a/llvm/test/CodeGen/AArch64/fcopysign.ll b/llvm/test/CodeGen/AArch64/fcopysign.ll
index 3a5f7e2cd6b29..f9be735ea782f 100644
--- a/llvm/test/CodeGen/AArch64/fcopysign.ll
+++ b/llvm/test/CodeGen/AArch64/fcopysign.ll
@@ -91,9 +91,8 @@ define <3 x double> @copysign_v3f64(<3 x double> %a, <3 x double> %b) {
; CHECK-SD-NEXT: bif v0.16b, v3.16b, v1.16b
; CHECK-SD-NEXT: bif v2.16b, v5.16b, v1.16b
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: copysign_v3f64:
diff --git a/llvm/test/CodeGen/AArch64/fcvt.ll b/llvm/test/CodeGen/AArch64/fcvt.ll
index b408e9c1bd4e6..2532a7b6a9406 100644
--- a/llvm/test/CodeGen/AArch64/fcvt.ll
+++ b/llvm/test/CodeGen/AArch64/fcvt.ll
@@ -73,9 +73,8 @@ define <3 x double> @ceil_v3f64(<3 x double> %a) {
; CHECK-SD-NEXT: frintp v2.2d, v2.2d
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-SD-NEXT: frintp v0.2d, v0.2d
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: ceil_v3f64:
@@ -372,9 +371,8 @@ define <3 x double> @floor_v3f64(<3 x double> %a) {
; CHECK-SD-NEXT: frintm v2.2d, v2.2d
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-SD-NEXT: frintm v0.2d, v0.2d
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: floor_v3f64:
@@ -671,9 +669,8 @@ define <3 x double> @nearbyint_v3f64(<3 x double> %a) {
; CHECK-SD-NEXT: frinti v2.2d, v2.2d
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-SD-NEXT: frinti v0.2d, v0.2d
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: nearbyint_v3f64:
@@ -970,9 +967,8 @@ define <3 x double> @roundeven_v3f64(<3 x double> %a) {
; CHECK-SD-NEXT: frintn v2.2d, v2.2d
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-SD-NEXT: frintn v0.2d, v0.2d
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: roundeven_v3f64:
@@ -1269,9 +1265,8 @@ define <3 x double> @rint_v3f64(<3 x double> %a) {
; CHECK-SD-NEXT: frintx v2.2d, v2.2d
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-SD-NEXT: frintx v0.2d, v0.2d
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: rint_v3f64:
@@ -1568,9 +1563,8 @@ define <3 x double> @round_v3f64(<3 x double> %a) {
; CHECK-SD-NEXT: frinta v2.2d, v2.2d
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-SD-NEXT: frinta v0.2d, v0.2d
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: round_v3f64:
@@ -1867,9 +1861,8 @@ define <3 x double> @trunc_v3f64(<3 x double> %a) {
; CHECK-SD-NEXT: frintz v2.2d, v2.2d
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-SD-NEXT: frintz v0.2d, v0.2d
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: trunc_v3f64:
diff --git a/llvm/test/CodeGen/AArch64/fdiv.ll b/llvm/test/CodeGen/AArch64/fdiv.ll
index 5bdccccc62b99..cad3a5618a14d 100644
--- a/llvm/test/CodeGen/AArch64/fdiv.ll
+++ b/llvm/test/CodeGen/AArch64/fdiv.ll
@@ -79,9 +79,8 @@ define <3 x double> @fdiv_v3f64(<3 x double> %a, <3 x double> %b) {
; CHECK-SD-NEXT: fdiv v2.2d, v2.2d, v5.2d
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-SD-NEXT: fdiv v0.2d, v0.2d, v3.2d
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: fdiv_v3f64:
diff --git a/llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll b/llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
index 9f3d1f8bf10f2..4973375f2447c 100644
--- a/llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
+++ b/llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
@@ -48,7 +48,7 @@ define {<8 x half>, <8 x half>} @vector_deinterleave_v8f16_v16f16(<16 x half> %v
define {<2 x float>, <2 x float>} @vector_deinterleave_v2f32_v4f32(<4 x float> %vec) {
; CHECK-SD-LABEL: vector_deinterleave_v2f32_v4f32:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: zip1 v2.2s, v0.2s, v1.2s
; CHECK-SD-NEXT: zip2 v1.2s, v0.2s, v1.2s
; CHECK-SD-NEXT: fmov d0, d2
@@ -236,12 +236,10 @@ define {<1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>} @vector_deinterleave4_v1i64_
; CHECK-LABEL: vector_deinterleave4_v1i64_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: mov v2.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1
-; CHECK-NEXT: ext v3.16b, v2.16b, v2.16b, #8
+; CHECK-NEXT: mov d3, v2.d[1]
; CHECK-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-NEXT: // kill: def $d3 killed $d3 killed $q3
; CHECK-NEXT: ret
%retval = call {<1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>} @llvm.vector.deinterleave4.v4i64(<4 x i64> %vec)
ret {<1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>} %retval
@@ -298,8 +296,8 @@ define {<8 x half>, <8 x half>, <8 x half>, <8 x half>} @vector_deinterleave4_v8
define {<2 x float>, <2 x float>, <2 x float>, <2 x float>} @vector_deinterleave4_v2f32_v8f32(<8 x float> %vec) {
; CHECK-LABEL: vector_deinterleave4_v2f32_v8f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-NEXT: ext v3.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d2, v1.d[1]
+; CHECK-NEXT: mov d3, v0.d[1]
; CHECK-NEXT: uzp1 v4.2s, v1.2s, v2.2s
; CHECK-NEXT: uzp1 v5.2s, v0.2s, v3.2s
; CHECK-NEXT: uzp2 v6.2s, v1.2s, v2.2s
@@ -333,12 +331,10 @@ define {<1 x double>, <1 x double>, <1 x double>, <1 x double>} @vector_deinterl
; CHECK-LABEL: vector_deinterleave4_v1f64_v4f64:
; CHECK: // %bb.0:
; CHECK-NEXT: mov v2.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1
-; CHECK-NEXT: ext v3.16b, v2.16b, v2.16b, #8
+; CHECK-NEXT: mov d3, v2.d[1]
; CHECK-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-NEXT: // kill: def $d3 killed $d3 killed $q3
; CHECK-NEXT: ret
%retval = call {<1 x double>, <1 x double>, <1 x double>, <1 x double>} @llvm.vector.deinterleave4.v4f64(<4 x double> %vec)
ret {<1 x double>, <1 x double>, <1 x double>, <1 x double>} %retval
diff --git a/llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll b/llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
index c8f0e78a9a224..a1f94a6a914b1 100644
--- a/llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
+++ b/llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
@@ -466,15 +466,12 @@ define <6 x double> @interleave3_v6f64(ptr %p, ptr %p0, <2 x double> %vec0, <2 x
; CHECK-NEXT: st3 { v0.2d, v1.2d, v2.2d }, [x8]
; CHECK-NEXT: ldp q0, q2, [sp]
; CHECK-NEXT: ldr q4, [sp, #32]
-; CHECK-NEXT: ext v5.16b, v4.16b, v4.16b, #8
+; CHECK-NEXT: mov d5, v4.d[1]
; CHECK-NEXT: // kill: def $d4 killed $d4 killed $q4
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: ext v3.16b, v2.16b, v2.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
+; CHECK-NEXT: mov d3, v2.d[1]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-NEXT: // kill: def $d5 killed $d5 killed $q5
-; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1
-; CHECK-NEXT: // kill: def $d3 killed $d3 killed $q3
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret
%retval = call <6 x double> @llvm.vector.interleave3.v6f64(<2 x double> %vec0, <2 x double> %vec1, <2 x double> %vec2)
diff --git a/llvm/test/CodeGen/AArch64/fminimummaximum.ll b/llvm/test/CodeGen/AArch64/fminimummaximum.ll
index fb12f8acf1745..f11f5f350770e 100644
--- a/llvm/test/CodeGen/AArch64/fminimummaximum.ll
+++ b/llvm/test/CodeGen/AArch64/fminimummaximum.ll
@@ -140,9 +140,8 @@ define <3 x double> @min_v3f64(<3 x double> %a, <3 x double> %b) {
; CHECK-SD-NEXT: fmin v2.2d, v2.2d, v5.2d
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-SD-NEXT: fmin v0.2d, v0.2d, v3.2d
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: min_v3f64:
@@ -177,9 +176,8 @@ define <3 x double> @max_v3f64(<3 x double> %a, <3 x double> %b) {
; CHECK-SD-NEXT: fmax v2.2d, v2.2d, v5.2d
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-SD-NEXT: fmax v0.2d, v0.2d, v3.2d
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: max_v3f64:
diff --git a/llvm/test/CodeGen/AArch64/fminmax.ll b/llvm/test/CodeGen/AArch64/fminmax.ll
index 64f0da8b4cd0f..6450ea312dad0 100644
--- a/llvm/test/CodeGen/AArch64/fminmax.ll
+++ b/llvm/test/CodeGen/AArch64/fminmax.ll
@@ -140,9 +140,8 @@ define <3 x double> @min_v3f64(<3 x double> %a, <3 x double> %b) {
; CHECK-SD-NEXT: fminnm v2.2d, v2.2d, v5.2d
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-SD-NEXT: fminnm v0.2d, v0.2d, v3.2d
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: min_v3f64:
@@ -177,9 +176,8 @@ define <3 x double> @max_v3f64(<3 x double> %a, <3 x double> %b) {
; CHECK-SD-NEXT: fmaxnm v2.2d, v2.2d, v5.2d
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-SD-NEXT: fmaxnm v0.2d, v0.2d, v3.2d
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: max_v3f64:
diff --git a/llvm/test/CodeGen/AArch64/fmla.ll b/llvm/test/CodeGen/AArch64/fmla.ll
index 807527ac13ad0..987e5675c17a5 100644
--- a/llvm/test/CodeGen/AArch64/fmla.ll
+++ b/llvm/test/CodeGen/AArch64/fmla.ll
@@ -85,9 +85,8 @@ define <3 x double> @fma_v3f64(<3 x double> %a, <3 x double> %b, <3 x double> %c
; CHECK-SD-NEXT: fmla v6.2d, v3.2d, v0.2d
; CHECK-SD-NEXT: ldr d3, [sp]
; CHECK-SD-NEXT: fmla v3.2d, v5.2d, v2.2d
+; CHECK-SD-NEXT: mov d1, v6.d[1]
; CHECK-SD-NEXT: fmov d0, d6
-; CHECK-SD-NEXT: ext v1.16b, v6.16b, v6.16b, #8
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: fmov d2, d3
; CHECK-SD-NEXT: ret
;
@@ -736,9 +735,8 @@ define <3 x double> @fmuladd_v3f64(<3 x double> %a, <3 x double> %b, <3 x double
; CHECK-SD-NEXT: fmla v6.2d, v3.2d, v0.2d
; CHECK-SD-NEXT: ldr d3, [sp]
; CHECK-SD-NEXT: fmla v3.2d, v5.2d, v2.2d
+; CHECK-SD-NEXT: mov d1, v6.d[1]
; CHECK-SD-NEXT: fmov d0, d6
-; CHECK-SD-NEXT: ext v1.16b, v6.16b, v6.16b, #8
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: fmov d2, d3
; CHECK-SD-NEXT: ret
;
@@ -1181,9 +1179,8 @@ define <3 x double> @fmul_v3f64(<3 x double> %a, <3 x double> %b, <3 x double> %
; CHECK-SD-NEXT: fmla v6.2d, v3.2d, v0.2d
; CHECK-SD-NEXT: ldr d3, [sp]
; CHECK-SD-NEXT: fmla v3.2d, v5.2d, v2.2d
+; CHECK-SD-NEXT: mov d1, v6.d[1]
; CHECK-SD-NEXT: fmov d0, d6
-; CHECK-SD-NEXT: ext v1.16b, v6.16b, v6.16b, #8
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: fmov d2, d3
; CHECK-SD-NEXT: ret
;
diff --git a/llvm/test/CodeGen/AArch64/fmul.ll b/llvm/test/CodeGen/AArch64/fmul.ll
index bd3d1353e643e..f5eea377a0707 100644
--- a/llvm/test/CodeGen/AArch64/fmul.ll
+++ b/llvm/test/CodeGen/AArch64/fmul.ll
@@ -79,9 +79,8 @@ define <3 x double> @fmul_v3f64(<3 x double> %a, <3 x double> %b) {
; CHECK-SD-NEXT: fmul v2.2d, v2.2d, v5.2d
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-SD-NEXT: fmul v0.2d, v0.2d, v3.2d
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: fmul_v3f64:
diff --git a/llvm/test/CodeGen/AArch64/fneg.ll b/llvm/test/CodeGen/AArch64/fneg.ll
index de2671afe60ab..39a83e52a44c3 100644
--- a/llvm/test/CodeGen/AArch64/fneg.ll
+++ b/llvm/test/CodeGen/AArch64/fneg.ll
@@ -77,9 +77,8 @@ define <3 x double> @fabs_v3f64(<3 x double> %a) {
; CHECK-SD-NEXT: fneg v2.2d, v2.2d
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-SD-NEXT: fneg v0.2d, v0.2d
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: fabs_v3f64:
diff --git a/llvm/test/CodeGen/AArch64/fp-maximumnum-minimumnum.ll b/llvm/test/CodeGen/AArch64/fp-maximumnum-minimumnum.ll
index 5353920ed5667..a3a09839c54c4 100644
--- a/llvm/test/CodeGen/AArch64/fp-maximumnum-minimumnum.ll
+++ b/llvm/test/CodeGen/AArch64/fp-maximumnum-minimumnum.ll
@@ -137,6 +137,7 @@
; CHECK-FP16-GI-NEXT: warning: Instruction selection used fallback path for min_v8f16
; CHECK-FP16-GI-NEXT: warning: Instruction selection used fallback path for min_v9f16
; CHECK-FP16-GI-NEXT: warning: Instruction selection used fallback path for min_v16f16
+;
;;;;;;;;;;;;;;;; max_f64
define double @max_nnan_f64(double %a, double %b) {
@@ -173,9 +174,8 @@ define <3 x double> @max_nnan_v3f64(<3 x double> %a, <3 x double> %b) {
; CHECK-NEXT: fmaxnm v2.2d, v2.2d, v5.2d
; CHECK-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v3.2d
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-NEXT: ret
entry:
%c = call nnan <3 x double> @llvm.maximumnum.v3f64(<3 x double> %a, <3 x double> %b)
@@ -710,9 +710,8 @@ define <3 x double> @min_nnan_v3f64(<3 x double> %a, <3 x double> %b) {
; CHECK-NEXT: fminnm v2.2d, v2.2d, v5.2d
; CHECK-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-NEXT: fminnm v0.2d, v0.2d, v3.2d
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-NEXT: ret
entry:
%c = call nnan <3 x double> @llvm.minimumnum.v3f64(<3 x double> %a, <3 x double> %b)
@@ -1316,9 +1315,8 @@ define <3 x double> @max_v3f64(<3 x double> %a, <3 x double> %b) {
; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v1.2d
; CHECK-NEXT: fminnm v1.2d, v5.2d, v5.2d
; CHECK-NEXT: fmaxnm v2.2d, v2.2d, v1.2d
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-NEXT: ret
entry:
@@ -1960,9 +1958,8 @@ define <3 x double> @min_v3f64(<3 x double> %a, <3 x double> %b) {
; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d
; CHECK-NEXT: fminnm v1.2d, v5.2d, v5.2d
; CHECK-NEXT: fminnm v2.2d, v2.2d, v1.2d
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll b/llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll
index 05422d3cc6051..cbcdb8596da6e 100644
--- a/llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll
+++ b/llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll
@@ -287,8 +287,7 @@ entry:
define <4 x half> @get_high(<8 x half> %a) #0 {
; CHECK-LABEL: get_high:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <8 x half> %a, <8 x half> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
diff --git a/llvm/test/CodeGen/AArch64/fpext.ll b/llvm/test/CodeGen/AArch64/fpext.ll
index 7085bfdc52f40..c0b883c806331 100644
--- a/llvm/test/CodeGen/AArch64/fpext.ll
+++ b/llvm/test/CodeGen/AArch64/fpext.ll
@@ -75,9 +75,8 @@ define <3 x double> @fpext_v3f32_v3f64(<3 x float> %a) {
; CHECK-SD-NEXT: fcvtl v3.2d, v0.2s
; CHECK-SD-NEXT: fcvtl2 v2.2d, v0.4s
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-SD-NEXT: mov d1, v3.d[1]
; CHECK-SD-NEXT: fmov d0, d3
-; CHECK-SD-NEXT: ext v1.16b, v3.16b, v3.16b, #8
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: fpext_v3f32_v3f64:
@@ -174,7 +173,7 @@ define <4 x fp128> @fpext_v4f32_v4f128(<4 x float> %a) {
; CHECK-SD-NEXT: .cfi_def_cfa_offset 80
; CHECK-SD-NEXT: .cfi_offset w30, -16
; CHECK-SD-NEXT: str q0, [sp, #48] // 16-byte Spill
-; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d0, v0.d[1]
; CHECK-SD-NEXT: str q0, [sp, #32] // 16-byte Spill
; CHECK-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-SD-NEXT: bl __extendsftf2
@@ -332,26 +331,15 @@ entry:
}
define <3 x double> @fpext_v3f16_v3f64(<3 x half> %a) {
-; CHECK-SD-LABEL: fpext_v3f16_v3f64:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-SD-NEXT: fcvtl v0.2d, v1.2s
-; CHECK-SD-NEXT: fcvtl2 v2.2d, v1.4s
-; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fpext_v3f16_v3f64:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-GI-NEXT: fcvtl v0.2d, v1.2s
-; CHECK-GI-NEXT: fcvtl2 v2.2d, v1.4s
-; CHECK-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fpext_v3f16_v3f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-NEXT: fcvtl v0.2d, v1.2s
+; CHECK-NEXT: fcvtl2 v2.2d, v1.4s
+; CHECK-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-NEXT: mov d1, v0.d[1]
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
entry:
%c = fpext <3 x half> %a to <3 x double>
ret <3 x double> %c
diff --git a/llvm/test/CodeGen/AArch64/fptoi.ll b/llvm/test/CodeGen/AArch64/fptoi.ll
index d82bcb90c8975..8e20323c82274 100644
--- a/llvm/test/CodeGen/AArch64/fptoi.ll
+++ b/llvm/test/CodeGen/AArch64/fptoi.ll
@@ -1363,118 +1363,36 @@ entry:
}
define <3 x i64> @fptos_v3f64_v3i64(<3 x double> %a) {
-; CHECK-NOFP16-SD-LABEL: fptos_v3f64_v3i64:
-; CHECK-NOFP16-SD: // %bb.0: // %entry
-; CHECK-NOFP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NOFP16-SD-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-NOFP16-SD-NEXT: // kill: def $d2 killed $d2 def $q2
-; CHECK-NOFP16-SD-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NOFP16-SD-NEXT: fcvtzs v2.2d, v2.2d
-; CHECK-NOFP16-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-NOFP16-SD-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-NOFP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NOFP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NOFP16-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
-; CHECK-NOFP16-SD-NEXT: ret
-;
-; CHECK-FP16-SD-LABEL: fptos_v3f64_v3i64:
-; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-FP16-SD-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-FP16-SD-NEXT: // kill: def $d2 killed $d2 def $q2
-; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-FP16-SD-NEXT: fcvtzs v2.2d, v2.2d
-; CHECK-FP16-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-FP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-FP16-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
-; CHECK-FP16-SD-NEXT: ret
-;
-; CHECK-NOFP16-GI-LABEL: fptos_v3f64_v3i64:
-; CHECK-NOFP16-GI: // %bb.0: // %entry
-; CHECK-NOFP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NOFP16-GI-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-NOFP16-GI-NEXT: // kill: def $d2 killed $d2 def $q2
-; CHECK-NOFP16-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NOFP16-GI-NEXT: fcvtzs v2.2d, v2.2d
-; CHECK-NOFP16-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-NOFP16-GI-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-NOFP16-GI-NEXT: mov d1, v0.d[1]
-; CHECK-NOFP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NOFP16-GI-NEXT: ret
-;
-; CHECK-FP16-GI-LABEL: fptos_v3f64_v3i64:
-; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-FP16-GI-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-FP16-GI-NEXT: // kill: def $d2 killed $d2 def $q2
-; CHECK-FP16-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v2.2d
-; CHECK-FP16-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-FP16-GI-NEXT: mov d1, v0.d[1]
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-FP16-GI-NEXT: ret
+; CHECK-LABEL: fptos_v3f64_v3i64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-NEXT: mov d1, v0.d[1]
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
entry:
%c = fptosi <3 x double> %a to <3 x i64>
ret <3 x i64> %c
}
define <3 x i64> @fptou_v3f64_v3i64(<3 x double> %a) {
-; CHECK-NOFP16-SD-LABEL: fptou_v3f64_v3i64:
-; CHECK-NOFP16-SD: // %bb.0: // %entry
-; CHECK-NOFP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NOFP16-SD-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-NOFP16-SD-NEXT: // kill: def $d2 killed $d2 def $q2
-; CHECK-NOFP16-SD-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NOFP16-SD-NEXT: fcvtzu v2.2d, v2.2d
-; CHECK-NOFP16-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-NOFP16-SD-NEXT: fcvtzu v0.2d, v0.2d
-; CHECK-NOFP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NOFP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NOFP16-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
-; CHECK-NOFP16-SD-NEXT: ret
-;
-; CHECK-FP16-SD-LABEL: fptou_v3f64_v3i64:
-; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-FP16-SD-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-FP16-SD-NEXT: // kill: def $d2 killed $d2 def $q2
-; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-FP16-SD-NEXT: fcvtzu v2.2d, v2.2d
-; CHECK-FP16-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-FP16-SD-NEXT: fcvtzu v0.2d, v0.2d
-; CHECK-FP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-FP16-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
-; CHECK-FP16-SD-NEXT: ret
-;
-; CHECK-NOFP16-GI-LABEL: fptou_v3f64_v3i64:
-; CHECK-NOFP16-GI: // %bb.0: // %entry
-; CHECK-NOFP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NOFP16-GI-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-NOFP16-GI-NEXT: // kill: def $d2 killed $d2 def $q2
-; CHECK-NOFP16-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NOFP16-GI-NEXT: fcvtzu v2.2d, v2.2d
-; CHECK-NOFP16-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-NOFP16-GI-NEXT: fcvtzu v0.2d, v0.2d
-; CHECK-NOFP16-GI-NEXT: mov d1, v0.d[1]
-; CHECK-NOFP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NOFP16-GI-NEXT: ret
-;
-; CHECK-FP16-GI-LABEL: fptou_v3f64_v3i64:
-; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-FP16-GI-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-FP16-GI-NEXT: // kill: def $d2 killed $d2 def $q2
-; CHECK-FP16-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-FP16-GI-NEXT: fcvtzu v2.2d, v2.2d
-; CHECK-FP16-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v0.2d
-; CHECK-FP16-GI-NEXT: mov d1, v0.d[1]
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-FP16-GI-NEXT: ret
+; CHECK-LABEL: fptou_v3f64_v3i64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: fcvtzu v2.2d, v2.2d
+; CHECK-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-NEXT: mov d1, v0.d[1]
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
entry:
%c = fptoui <3 x double> %a to <3 x i64>
ret <3 x i64> %c
@@ -3270,9 +3188,8 @@ define <3 x i64> @fptos_v3f32_v3i64(<3 x float> %a) {
; CHECK-NOFP16-SD-NEXT: fcvtzs v3.2d, v1.2d
; CHECK-NOFP16-SD-NEXT: fcvtzs v2.2d, v0.2d
; CHECK-NOFP16-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-NOFP16-SD-NEXT: mov d1, v3.d[1]
; CHECK-NOFP16-SD-NEXT: fmov d0, d3
-; CHECK-NOFP16-SD-NEXT: ext v1.16b, v3.16b, v3.16b, #8
-; CHECK-NOFP16-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-NOFP16-SD-NEXT: ret
;
; CHECK-FP16-SD-LABEL: fptos_v3f32_v3i64:
@@ -3282,9 +3199,8 @@ define <3 x i64> @fptos_v3f32_v3i64(<3 x float> %a) {
; CHECK-FP16-SD-NEXT: fcvtzs v3.2d, v1.2d
; CHECK-FP16-SD-NEXT: fcvtzs v2.2d, v0.2d
; CHECK-FP16-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-FP16-SD-NEXT: mov d1, v3.d[1]
; CHECK-FP16-SD-NEXT: fmov d0, d3
-; CHECK-FP16-SD-NEXT: ext v1.16b, v3.16b, v3.16b, #8
-; CHECK-FP16-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-NOFP16-GI-LABEL: fptos_v3f32_v3i64:
@@ -3323,9 +3239,8 @@ define <3 x i64> @fptou_v3f32_v3i64(<3 x float> %a) {
; CHECK-NOFP16-SD-NEXT: fcvtzu v3.2d, v1.2d
; CHECK-NOFP16-SD-NEXT: fcvtzu v2.2d, v0.2d
; CHECK-NOFP16-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-NOFP16-SD-NEXT: mov d1, v3.d[1]
; CHECK-NOFP16-SD-NEXT: fmov d0, d3
-; CHECK-NOFP16-SD-NEXT: ext v1.16b, v3.16b, v3.16b, #8
-; CHECK-NOFP16-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-NOFP16-SD-NEXT: ret
;
; CHECK-FP16-SD-LABEL: fptou_v3f32_v3i64:
@@ -3335,9 +3250,8 @@ define <3 x i64> @fptou_v3f32_v3i64(<3 x float> %a) {
; CHECK-FP16-SD-NEXT: fcvtzu v3.2d, v1.2d
; CHECK-FP16-SD-NEXT: fcvtzu v2.2d, v0.2d
; CHECK-FP16-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-FP16-SD-NEXT: mov d1, v3.d[1]
; CHECK-FP16-SD-NEXT: fmov d0, d3
-; CHECK-FP16-SD-NEXT: ext v1.16b, v3.16b, v3.16b, #8
-; CHECK-FP16-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-NOFP16-GI-LABEL: fptou_v3f32_v3i64:
@@ -4897,7 +4811,7 @@ entry:
define <8 x i64> @fptos_v8f16_v8i64(<8 x half> %a) {
; CHECK-NOFP16-SD-LABEL: fptos_v8f16_v8i64:
; CHECK-NOFP16-SD: // %bb.0: // %entry
-; CHECK-NOFP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NOFP16-SD-NEXT: mov d1, v0.d[1]
; CHECK-NOFP16-SD-NEXT: mov h4, v0.h[2]
; CHECK-NOFP16-SD-NEXT: mov h3, v0.h[1]
; CHECK-NOFP16-SD-NEXT: mov h7, v0.h[3]
@@ -4932,7 +4846,7 @@ define <8 x i64> @fptos_v8f16_v8i64(<8 x half> %a) {
;
; CHECK-FP16-SD-LABEL: fptos_v8f16_v8i64:
; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-FP16-SD-NEXT: mov d1, v0.d[1]
; CHECK-FP16-SD-NEXT: mov h4, v0.h[2]
; CHECK-FP16-SD-NEXT: mov h3, v0.h[1]
; CHECK-FP16-SD-NEXT: mov h7, v0.h[3]
@@ -4992,7 +4906,7 @@ entry:
define <8 x i64> @fptou_v8f16_v8i64(<8 x half> %a) {
; CHECK-NOFP16-SD-LABEL: fptou_v8f16_v8i64:
; CHECK-NOFP16-SD: // %bb.0: // %entry
-; CHECK-NOFP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NOFP16-SD-NEXT: mov d1, v0.d[1]
; CHECK-NOFP16-SD-NEXT: mov h4, v0.h[2]
; CHECK-NOFP16-SD-NEXT: mov h3, v0.h[1]
; CHECK-NOFP16-SD-NEXT: mov h7, v0.h[3]
@@ -5027,7 +4941,7 @@ define <8 x i64> @fptou_v8f16_v8i64(<8 x half> %a) {
;
; CHECK-FP16-SD-LABEL: fptou_v8f16_v8i64:
; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-FP16-SD-NEXT: mov d1, v0.d[1]
; CHECK-FP16-SD-NEXT: mov h4, v0.h[2]
; CHECK-FP16-SD-NEXT: mov h3, v0.h[1]
; CHECK-FP16-SD-NEXT: mov h7, v0.h[3]
@@ -5087,8 +5001,8 @@ entry:
define <16 x i64> @fptos_v16f16_v16i64(<16 x half> %a) {
; CHECK-NOFP16-SD-LABEL: fptos_v16f16_v16i64:
; CHECK-NOFP16-SD: // %bb.0: // %entry
-; CHECK-NOFP16-SD-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-NOFP16-SD-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-NOFP16-SD-NEXT: mov d2, v0.d[1]
+; CHECK-NOFP16-SD-NEXT: mov d3, v1.d[1]
; CHECK-NOFP16-SD-NEXT: mov h4, v0.h[1]
; CHECK-NOFP16-SD-NEXT: fcvt s5, h0
; CHECK-NOFP16-SD-NEXT: mov h18, v0.h[2]
@@ -5153,8 +5067,8 @@ define <16 x i64> @fptos_v16f16_v16i64(<16 x half> %a) {
;
; CHECK-FP16-SD-LABEL: fptos_v16f16_v16i64:
; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-FP16-SD-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-FP16-SD-NEXT: mov d2, v0.d[1]
+; CHECK-FP16-SD-NEXT: mov d3, v1.d[1]
; CHECK-FP16-SD-NEXT: mov h4, v0.h[1]
; CHECK-FP16-SD-NEXT: mov h5, v0.h[2]
; CHECK-FP16-SD-NEXT: fcvtzs x8, h0
@@ -5256,8 +5170,8 @@ entry:
define <16 x i64> @fptou_v16f16_v16i64(<16 x half> %a) {
; CHECK-NOFP16-SD-LABEL: fptou_v16f16_v16i64:
; CHECK-NOFP16-SD: // %bb.0: // %entry
-; CHECK-NOFP16-SD-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-NOFP16-SD-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-NOFP16-SD-NEXT: mov d2, v0.d[1]
+; CHECK-NOFP16-SD-NEXT: mov d3, v1.d[1]
; CHECK-NOFP16-SD-NEXT: mov h4, v0.h[1]
; CHECK-NOFP16-SD-NEXT: fcvt s5, h0
; CHECK-NOFP16-SD-NEXT: mov h18, v0.h[2]
@@ -5322,8 +5236,8 @@ define <16 x i64> @fptou_v16f16_v16i64(<16 x half> %a) {
;
; CHECK-FP16-SD-LABEL: fptou_v16f16_v16i64:
; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-FP16-SD-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-FP16-SD-NEXT: mov d2, v0.d[1]
+; CHECK-FP16-SD-NEXT: mov d3, v1.d[1]
; CHECK-FP16-SD-NEXT: mov h4, v0.h[1]
; CHECK-FP16-SD-NEXT: mov h5, v0.h[2]
; CHECK-FP16-SD-NEXT: fcvtzu x8, h0
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
index 6a06d99689df9..145aef9123a4e 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
@@ -1888,7 +1888,7 @@ define <4 x i32> @test_signed_v4f32_v4i32_duplicate(<4 x float> %f) {
define <4 x i50> @test_signed_v4f32_v4i50(<4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i50:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: mov x8, #562949953421311 // =0x1ffffffffffff
; CHECK-NEXT: mov x11, #-562949953421312 // =0xfffe000000000000
; CHECK-NEXT: fcvtzs x12, s0
@@ -1985,7 +1985,7 @@ define <4 x i100> @test_signed_v4f32_v4i100(<4 x float> %f) {
; CHECK-SD-NEXT: bl __fixsfti
; CHECK-SD-NEXT: fcmp s8, s9
; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d0, v0.d[1]
; CHECK-SD-NEXT: csel x8, xzr, x0, lt
; CHECK-SD-NEXT: csel x9, x25, x1, lt
; CHECK-SD-NEXT: fcmp s8, s10
@@ -2182,7 +2182,7 @@ define <4 x i128> @test_signed_v4f32_v4i128(<4 x float> %f) {
; CHECK-SD-NEXT: bl __fixsfti
; CHECK-SD-NEXT: fcmp s8, s9
; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d0, v0.d[1]
; CHECK-SD-NEXT: csel x8, xzr, x0, lt
; CHECK-SD-NEXT: csel x9, x25, x1, lt
; CHECK-SD-NEXT: fcmp s8, s10
@@ -3636,7 +3636,7 @@ define <8 x i32> @test_signed_v8f16_v8i32_duplicate(<8 x half> %f) {
define <8 x i50> @test_signed_v8f16_v8i50(<8 x half> %f) {
; CHECK-CVT-LABEL: test_signed_v8f16_v8i50:
; CHECK-CVT: // %bb.0:
-; CHECK-CVT-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-CVT-NEXT: mov d1, v0.d[1]
; CHECK-CVT-NEXT: mov x8, #562949953421311 // =0x1ffffffffffff
; CHECK-CVT-NEXT: mov x9, #-562949953421312 // =0xfffe000000000000
; CHECK-CVT-NEXT: mov h2, v1.h[1]
@@ -3697,7 +3697,7 @@ define <8 x i50> @test_signed_v8f16_v8i50(<8 x half> %f) {
;
; CHECK-FP16-LABEL: test_signed_v8f16_v8i50:
; CHECK-FP16: // %bb.0:
-; CHECK-FP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-FP16-NEXT: mov d1, v0.d[1]
; CHECK-FP16-NEXT: mov x8, #562949953421311 // =0x1ffffffffffff
; CHECK-FP16-NEXT: mov x9, #-562949953421312 // =0xfffe000000000000
; CHECK-FP16-NEXT: mov h2, v1.h[1]
@@ -3754,7 +3754,7 @@ define <8 x i50> @test_signed_v8f16_v8i50(<8 x half> %f) {
define <8 x i64> @test_signed_v8f16_v8i64(<8 x half> %f) {
; CHECK-SD-CVT-LABEL: test_signed_v8f16_v8i64:
; CHECK-SD-CVT: // %bb.0:
-; CHECK-SD-CVT-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-CVT-NEXT: mov d1, v0.d[1]
; CHECK-SD-CVT-NEXT: mov h4, v0.h[2]
; CHECK-SD-CVT-NEXT: mov h3, v0.h[1]
; CHECK-SD-CVT-NEXT: mov h7, v0.h[3]
@@ -3789,7 +3789,7 @@ define <8 x i64> @test_signed_v8f16_v8i64(<8 x half> %f) {
;
; CHECK-SD-FP16-LABEL: test_signed_v8f16_v8i64:
; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-FP16-NEXT: mov d1, v0.d[1]
; CHECK-SD-FP16-NEXT: mov h4, v0.h[2]
; CHECK-SD-FP16-NEXT: mov h3, v0.h[1]
; CHECK-SD-FP16-NEXT: mov h7, v0.h[3]
@@ -3860,7 +3860,7 @@ define <8 x i100> @test_signed_v8f16_v8i100(<8 x half> %f) {
; CHECK-NEXT: .cfi_offset b9, -112
; CHECK-NEXT: .cfi_offset b10, -128
; CHECK-NEXT: str q0, [sp, #48] // 16-byte Spill
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: mov x19, x8
; CHECK-NEXT: str q0, [sp, #32] // 16-byte Spill
; CHECK-NEXT: mov h0, v0.h[1]
@@ -3942,8 +3942,8 @@ define <8 x i100> @test_signed_v8f16_v8i100(<8 x half> %f) {
; CHECK-NEXT: csel x8, x23, x8, gt
; CHECK-NEXT: fcmp s8, s8
; CHECK-NEXT: fcvt s8, h0
-; CHECK-NEXT: csel x20, xzr, x8, vs
-; CHECK-NEXT: csel x21, xzr, x9, vs
+; CHECK-NEXT: csel x21, xzr, x8, vs
+; CHECK-NEXT: csel x28, xzr, x9, vs
; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: bl __fixsfti
; CHECK-NEXT: fcmp s8, s10
@@ -3955,7 +3955,7 @@ define <8 x i100> @test_signed_v8f16_v8i100(<8 x half> %f) {
; CHECK-NEXT: csinv x8, x8, xzr, le
; CHECK-NEXT: fcmp s8, s8
; CHECK-NEXT: fcvt s8, h0
-; CHECK-NEXT: csel x28, xzr, x8, vs
+; CHECK-NEXT: csel x20, xzr, x8, vs
; CHECK-NEXT: csel x24, xzr, x9, vs
; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: bl __fixsfti
@@ -3974,12 +3974,12 @@ define <8 x i100> @test_signed_v8f16_v8i100(<8 x half> %f) {
; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: bl __fixsfti
; CHECK-NEXT: ldr x9, [sp] // 8-byte Reload
-; CHECK-NEXT: extr x8, x24, x28, #28
+; CHECK-NEXT: extr x8, x24, x20, #28
; CHECK-NEXT: fcmp s8, s10
-; CHECK-NEXT: bfi x25, x21, #36, #28
-; CHECK-NEXT: lsr x11, x20, #28
+; CHECK-NEXT: bfi x25, x28, #36, #28
+; CHECK-NEXT: lsr x11, x21, #28
; CHECK-NEXT: stur x9, [x19, #75]
-; CHECK-NEXT: extr x9, x20, x21, #28
+; CHECK-NEXT: extr x9, x21, x28, #28
; CHECK-NEXT: stur x8, [x19, #41]
; CHECK-NEXT: csel x8, x22, x1, lt
; CHECK-NEXT: str x9, [x19, #16]
@@ -3998,7 +3998,7 @@ define <8 x i100> @test_signed_v8f16_v8i100(<8 x half> %f) {
; CHECK-NEXT: csel x8, xzr, x8, vs
; CHECK-NEXT: ldr x13, [sp, #24] // 8-byte Reload
; CHECK-NEXT: csel x9, xzr, x9, vs
-; CHECK-NEXT: bfi x8, x28, #36, #28
+; CHECK-NEXT: bfi x8, x20, #36, #28
; CHECK-NEXT: extr x10, x14, x12, #28
; CHECK-NEXT: bfi x27, x12, #36, #28
; CHECK-NEXT: ldr x12, [sp, #72] // 8-byte Reload
@@ -4057,7 +4057,7 @@ define <8 x i128> @test_signed_v8f16_v8i128(<8 x half> %f) {
; CHECK-SD-NEXT: .cfi_offset b9, -112
; CHECK-SD-NEXT: .cfi_offset b10, -128
; CHECK-SD-NEXT: str q0, [sp, #48] // 16-byte Spill
-; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d0, v0.d[1]
; CHECK-SD-NEXT: mov x19, x8
; CHECK-SD-NEXT: fcvt s8, h0
; CHECK-SD-NEXT: str q0, [sp, #32] // 16-byte Spill
diff --git a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
index d4feab2ea5d9b..083a84292029d 100644
--- a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
@@ -1550,7 +1550,7 @@ define <4 x i32> @test_unsigned_v4f32_v4i32_duplicate(<4 x float> %f) {
define <4 x i50> @test_unsigned_v4f32_v4i50(<4 x float> %f) {
; CHECK-LABEL: test_unsigned_v4f32_v4i50:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: mov s3, v0.s[1]
; CHECK-NEXT: mov x8, #1125899906842623 // =0x3ffffffffffff
; CHECK-NEXT: fcvtzu x11, s0
@@ -1629,7 +1629,7 @@ define <4 x i100> @test_unsigned_v4f32_v4i100(<4 x float> %f) {
; CHECK-SD-NEXT: bl __fixunssfti
; CHECK-SD-NEXT: fcmp s8, #0.0
; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d0, v0.d[1]
; CHECK-SD-NEXT: csel x8, xzr, x0, lt
; CHECK-SD-NEXT: csel x9, xzr, x1, lt
; CHECK-SD-NEXT: fcmp s8, s9
@@ -1784,7 +1784,7 @@ define <4 x i128> @test_unsigned_v4f32_v4i128(<4 x float> %f) {
; CHECK-SD-NEXT: bl __fixunssfti
; CHECK-SD-NEXT: fcmp s8, #0.0
; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d0, v0.d[1]
; CHECK-SD-NEXT: csel x8, xzr, x1, lt
; CHECK-SD-NEXT: csel x9, xzr, x0, lt
; CHECK-SD-NEXT: fcmp s8, s9
@@ -2939,7 +2939,7 @@ define <8 x i32> @test_unsigned_v8f16_v8i32_duplicate(<8 x half> %f) {
define <8 x i50> @test_unsigned_v8f16_v8i50(<8 x half> %f) {
; CHECK-CVT-LABEL: test_unsigned_v8f16_v8i50:
; CHECK-CVT: // %bb.0:
-; CHECK-CVT-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-CVT-NEXT: mov d1, v0.d[1]
; CHECK-CVT-NEXT: mov h5, v0.h[1]
; CHECK-CVT-NEXT: mov x8, #1125899906842623 // =0x3ffffffffffff
; CHECK-CVT-NEXT: mov h6, v0.h[2]
@@ -2983,7 +2983,7 @@ define <8 x i50> @test_unsigned_v8f16_v8i50(<8 x half> %f) {
;
; CHECK-FP16-LABEL: test_unsigned_v8f16_v8i50:
; CHECK-FP16: // %bb.0:
-; CHECK-FP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-FP16-NEXT: mov d1, v0.d[1]
; CHECK-FP16-NEXT: mov x8, #1125899906842623 // =0x3ffffffffffff
; CHECK-FP16-NEXT: fcvtzu x13, h0
; CHECK-FP16-NEXT: mov h2, v1.h[1]
@@ -3023,7 +3023,7 @@ define <8 x i50> @test_unsigned_v8f16_v8i50(<8 x half> %f) {
define <8 x i64> @test_unsigned_v8f16_v8i64(<8 x half> %f) {
; CHECK-SD-CVT-LABEL: test_unsigned_v8f16_v8i64:
; CHECK-SD-CVT: // %bb.0:
-; CHECK-SD-CVT-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-CVT-NEXT: mov d1, v0.d[1]
; CHECK-SD-CVT-NEXT: mov h4, v0.h[2]
; CHECK-SD-CVT-NEXT: mov h3, v0.h[1]
; CHECK-SD-CVT-NEXT: mov h7, v0.h[3]
@@ -3058,7 +3058,7 @@ define <8 x i64> @test_unsigned_v8f16_v8i64(<8 x half> %f) {
;
; CHECK-SD-FP16-LABEL: test_unsigned_v8f16_v8i64:
; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-FP16-NEXT: mov d1, v0.d[1]
; CHECK-SD-FP16-NEXT: mov h4, v0.h[2]
; CHECK-SD-FP16-NEXT: mov h3, v0.h[1]
; CHECK-SD-FP16-NEXT: mov h7, v0.h[3]
@@ -3127,7 +3127,7 @@ define <8 x i100> @test_unsigned_v8f16_v8i100(<8 x half> %f) {
; CHECK-NEXT: .cfi_offset b8, -104
; CHECK-NEXT: .cfi_offset b9, -112
; CHECK-NEXT: str q0, [sp, #48] // 16-byte Spill
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: mov x19, x8
; CHECK-NEXT: str q0, [sp, #32] // 16-byte Spill
; CHECK-NEXT: mov h0, v0.h[1]
@@ -3291,7 +3291,7 @@ define <8 x i128> @test_unsigned_v8f16_v8i128(<8 x half> %f) {
; CHECK-SD-NEXT: .cfi_offset b8, -104
; CHECK-SD-NEXT: .cfi_offset b9, -112
; CHECK-SD-NEXT: str q0, [sp, #48] // 16-byte Spill
-; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d0, v0.d[1]
; CHECK-SD-NEXT: mov x19, x8
; CHECK-SD-NEXT: fcvt s8, h0
; CHECK-SD-NEXT: str q0, [sp, #32] // 16-byte Spill
diff --git a/llvm/test/CodeGen/AArch64/freeze.ll b/llvm/test/CodeGen/AArch64/freeze.ll
index 136ac8b0a2aa1..3476dc0c81573 100644
--- a/llvm/test/CodeGen/AArch64/freeze.ll
+++ b/llvm/test/CodeGen/AArch64/freeze.ll
@@ -242,9 +242,8 @@ define <3 x i64> @freeze_v3i64() {
; CHECK-SD-LABEL: freeze_v3i64:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: add v0.2d, v0.2d, v0.2d
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: fmov d2, d0
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: freeze_v3i64:
@@ -296,10 +295,9 @@ define <3 x ptr> @freeze_v3p0() {
; CHECK-SD-NEXT: mov w8, #4 // =0x4
; CHECK-SD-NEXT: dup v2.2d, x8
; CHECK-SD-NEXT: add v0.2d, v0.2d, v2.2d
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: add d2, d0, d2
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: freeze_v3p0:
diff --git a/llvm/test/CodeGen/AArch64/fsqrt.ll b/llvm/test/CodeGen/AArch64/fsqrt.ll
index 6c5fd8e52b017..7ba763727a3c8 100644
--- a/llvm/test/CodeGen/AArch64/fsqrt.ll
+++ b/llvm/test/CodeGen/AArch64/fsqrt.ll
@@ -73,9 +73,8 @@ define <3 x double> @sqrt_v3f64(<3 x double> %a) {
; CHECK-SD-NEXT: fsqrt v2.2d, v2.2d
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-SD-NEXT: fsqrt v0.2d, v0.2d
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: sqrt_v3f64:
diff --git a/llvm/test/CodeGen/AArch64/highextractbitcast.ll b/llvm/test/CodeGen/AArch64/highextractbitcast.ll
index de2911b8a5127..df5801b9af938 100644
--- a/llvm/test/CodeGen/AArch64/highextractbitcast.ll
+++ b/llvm/test/CodeGen/AArch64/highextractbitcast.ll
@@ -94,9 +94,9 @@ define <4 x i32> @test_smull_high_s16_bitcasta2(<2 x i64> %a, <8 x i16> %b) #0 {
; CHECK-BE-NEXT: rev64 v1.8h, v1.8h
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: mov d0, v0.d[1]
; CHECK-BE-NEXT: rev64 v0.4h, v0.4h
-; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: mov d1, v1.d[1]
; CHECK-BE-NEXT: smull v0.4s, v0.4h, v1.4h
; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
@@ -121,8 +121,8 @@ define <4 x i32> @test_smull_high_s16_bitcastb2(<8 x i16> %a, <16 x i8> %b) #0 {
; CHECK-BE-NEXT: rev64 v0.8h, v0.8h
; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: mov d1, v1.d[1]
+; CHECK-BE-NEXT: mov d0, v0.d[1]
; CHECK-BE-NEXT: rev16 v1.8b, v1.8b
; CHECK-BE-NEXT: smull v0.4s, v0.4h, v1.4h
; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
@@ -140,8 +140,8 @@ entry:
define <4 x i32> @test_smull_high_s16_bitcasta1_wrongindex(<2 x i64> %aa, <8 x i16> %b) #0 {
; CHECK-LE-LABEL: test_smull_high_s16_bitcasta1_wrongindex:
; CHECK-LE: // %bb.0: // %entry
-; CHECK-LE-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-LE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECK-LE-NEXT: mov d2, v0.d[1]
+; CHECK-LE-NEXT: mov d1, v1.d[1]
; CHECK-LE-NEXT: ext v0.8b, v0.8b, v2.8b, #4
; CHECK-LE-NEXT: smull v0.4s, v0.4h, v1.4h
; CHECK-LE-NEXT: ret
@@ -153,7 +153,7 @@ define <4 x i32> @test_smull_high_s16_bitcasta1_wrongindex(<2 x i64> %aa, <8 x i
; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #4
-; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: mov d1, v1.d[1]
; CHECK-BE-NEXT: smull v0.4s, v0.4h, v1.4h
; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
@@ -176,8 +176,8 @@ entry:
define <4 x i32> @test_smull_high_s16_bitcastb1_wrongindex(<8 x i16> %a, <16 x i8> %bb) #0 {
; CHECK-LE-LABEL: test_smull_high_s16_bitcastb1_wrongindex:
; CHECK-LE: // %bb.0: // %entry
-; CHECK-LE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-LE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-LE-NEXT: mov d2, v1.d[1]
+; CHECK-LE-NEXT: mov d0, v0.d[1]
; CHECK-LE-NEXT: ext v1.8b, v1.8b, v2.8b, #6
; CHECK-LE-NEXT: smull v0.4s, v0.4h, v1.4h
; CHECK-LE-NEXT: ret
@@ -188,7 +188,7 @@ define <4 x i32> @test_smull_high_s16_bitcastb1_wrongindex(<8 x i16> %a, <16 x i
; CHECK-BE-NEXT: rev64 v1.8h, v1.8h
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: mov d0, v0.d[1]
; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #6
; CHECK-BE-NEXT: smull v0.4s, v0.4h, v1.4h
; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
@@ -210,12 +210,12 @@ entry:
}
define <4 x i32> @test_smull_high_s16_bitcasta2_wrongindex(<4 x i32> %a, <8 x i16> %b) #0 {
-; CHECK-LE-LABEL: test_smull_high_s16_bitcasta2_wrongindex:
-; CHECK-LE: // %bb.0: // %entry
-; CHECK-LE-NEXT: ext v0.16b, v0.16b, v0.16b, #4
-; CHECK-LE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-LE-NEXT: smull v0.4s, v0.4h, v1.4h
-; CHECK-LE-NEXT: ret
+; CHECK-LABEL: test_smull_high_s16_bitcasta2_wrongindex:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #4
+; CHECK-NEXT: mov d1, v1.d[1]
+; CHECK-NEXT: smull v0.4s, v0.4h, v1.4h
+; CHECK-NEXT: ret
;
; CHECK-BE-LABEL: test_smull_high_s16_bitcasta2_wrongindex:
; CHECK-BE: // %bb.0: // %entry
@@ -224,19 +224,12 @@ define <4 x i32> @test_smull_high_s16_bitcasta2_wrongindex(<4 x i32> %a, <8 x i1
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #4
-; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: mov d1, v1.d[1]
; CHECK-BE-NEXT: rev32 v0.4h, v0.4h
; CHECK-BE-NEXT: smull v0.4s, v0.4h, v1.4h
; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT: ret
-;
-; CHECK-GI-LABEL: test_smull_high_s16_bitcasta2_wrongindex:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #4
-; CHECK-GI-NEXT: mov d1, v1.d[1]
-; CHECK-GI-NEXT: smull v0.4s, v0.4h, v1.4h
-; CHECK-GI-NEXT: ret
entry:
%s1a = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 1, i32 2>
%s1 = bitcast <2 x i32> %s1a to <4 x i16>
@@ -248,7 +241,7 @@ entry:
define <4 x i32> @test_smull_high_s16_bitcastb2_wrongindex(<8 x i16> %a, <16 x i8> %b) #0 {
; CHECK-LE-LABEL: test_smull_high_s16_bitcastb2_wrongindex:
; CHECK-LE: // %bb.0: // %entry
-; CHECK-LE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-LE-NEXT: mov d0, v0.d[1]
; CHECK-LE-NEXT: ext v1.16b, v1.16b, v1.16b, #4
; CHECK-LE-NEXT: smull v0.4s, v0.4h, v1.4h
; CHECK-LE-NEXT: ret
@@ -260,7 +253,7 @@ define <4 x i32> @test_smull_high_s16_bitcastb2_wrongindex(<8 x i16> %a, <16 x i
; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #4
-; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: mov d0, v0.d[1]
; CHECK-BE-NEXT: rev16 v1.8b, v1.8b
; CHECK-BE-NEXT: smull v0.4s, v0.4h, v1.4h
; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
@@ -343,12 +336,12 @@ entry:
}
define <4 x i32> @test_smull_high_s16_splata2(<4 x i32> %a, <8 x i16> %b) #0 {
-; CHECK-LE-LABEL: test_smull_high_s16_splata2:
-; CHECK-LE: // %bb.0: // %entry
-; CHECK-LE-NEXT: dup v0.2s, v0.s[3]
-; CHECK-LE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-LE-NEXT: smull v0.4s, v0.4h, v1.4h
-; CHECK-LE-NEXT: ret
+; CHECK-LABEL: test_smull_high_s16_splata2:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v0.2s, v0.s[3]
+; CHECK-NEXT: mov d1, v1.d[1]
+; CHECK-NEXT: smull v0.4s, v0.4h, v1.4h
+; CHECK-NEXT: ret
;
; CHECK-BE-LABEL: test_smull_high_s16_splata2:
; CHECK-BE: // %bb.0: // %entry
@@ -357,19 +350,12 @@ define <4 x i32> @test_smull_high_s16_splata2(<4 x i32> %a, <8 x i16> %b) #0 {
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-BE-NEXT: dup v0.2s, v0.s[3]
-; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: mov d1, v1.d[1]
; CHECK-BE-NEXT: rev32 v0.4h, v0.4h
; CHECK-BE-NEXT: smull v0.4s, v0.4h, v1.4h
; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT: ret
-;
-; CHECK-GI-LABEL: test_smull_high_s16_splata2:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: dup v0.2s, v0.s[3]
-; CHECK-GI-NEXT: mov d1, v1.d[1]
-; CHECK-GI-NEXT: smull v0.4s, v0.4h, v1.4h
-; CHECK-GI-NEXT: ret
entry:
%s1a = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 3, i32 3>
%s1 = bitcast <2 x i32> %s1a to <4 x i16>
@@ -379,12 +365,12 @@ entry:
}
define <4 x i32> @test_smull_high_s16_splatb2(<8 x i16> %a, <16 x i8> %b) #0 {
-; CHECK-LE-LABEL: test_smull_high_s16_splatb2:
-; CHECK-LE: // %bb.0: // %entry
-; CHECK-LE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-LE-NEXT: dup v1.8b, v1.b[3]
-; CHECK-LE-NEXT: smull v0.4s, v0.4h, v1.4h
-; CHECK-LE-NEXT: ret
+; CHECK-LABEL: test_smull_high_s16_splatb2:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov d0, v0.d[1]
+; CHECK-NEXT: dup v1.8b, v1.b[3]
+; CHECK-NEXT: smull v0.4s, v0.4h, v1.4h
+; CHECK-NEXT: ret
;
; CHECK-BE-LABEL: test_smull_high_s16_splatb2:
; CHECK-BE: // %bb.0: // %entry
@@ -393,19 +379,12 @@ define <4 x i32> @test_smull_high_s16_splatb2(<8 x i16> %a, <16 x i8> %b) #0 {
; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT: dup v1.8b, v1.b[3]
-; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: mov d0, v0.d[1]
; CHECK-BE-NEXT: rev16 v1.8b, v1.8b
; CHECK-BE-NEXT: smull v0.4s, v0.4h, v1.4h
; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT: ret
-;
-; CHECK-GI-LABEL: test_smull_high_s16_splatb2:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
-; CHECK-GI-NEXT: dup v1.8b, v1.b[3]
-; CHECK-GI-NEXT: smull v0.4s, v0.4h, v1.4h
-; CHECK-GI-NEXT: ret
entry:
%s1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%s2a = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
diff --git a/llvm/test/CodeGen/AArch64/icmp.ll b/llvm/test/CodeGen/AArch64/icmp.ll
index 7195e2b2f1255..312ea4cb9eaa1 100644
--- a/llvm/test/CodeGen/AArch64/icmp.ll
+++ b/llvm/test/CodeGen/AArch64/icmp.ll
@@ -1142,9 +1142,8 @@ define <3 x i64> @v3i64_i64(<3 x i64> %a, <3 x i64> %b, <3 x i64> %d, <3 x i64>
; CHECK-SD-NEXT: bsl v0.16b, v6.16b, v1.16b
; CHECK-SD-NEXT: cmgt v1.2d, v5.2d, v2.2d
; CHECK-SD-NEXT: mov v2.16b, v1.16b
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: bsl v2.16b, v17.16b, v16.16b
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-SD-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/insert-subvector.ll b/llvm/test/CodeGen/AArch64/insert-subvector.ll
index 88b6ea4f0cb19..1aa8f861964cd 100644
--- a/llvm/test/CodeGen/AArch64/insert-subvector.ll
+++ b/llvm/test/CodeGen/AArch64/insert-subvector.ll
@@ -340,7 +340,7 @@ define <8 x i8> @load_v8i8_4_2(float %tmp, <8 x i8> %b, ptr %a) {
define <16 x i8> @load_v16i8_8_1(float %tmp, <16 x i8> %b, ptr %a) {
; CHECK-LABEL: load_v16i8_8_1:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT: mov d1, v1.d[1]
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: mov v0.d[1], v1.d[0]
; CHECK-NEXT: ret
@@ -557,7 +557,7 @@ define <4 x i16> @load_v4i16_2_2(float %tmp, <4 x i16> %b, ptr %a) {
define <8 x i16> @load_v8i16_4_1(float %tmp, <8 x i16> %b, ptr %a) {
; CHECK-LABEL: load_v8i16_4_1:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT: mov d1, v1.d[1]
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: mov v0.d[1], v1.d[0]
; CHECK-NEXT: ret
@@ -585,7 +585,7 @@ define <8 x i16> @load_v8i16_4_2(float %tmp, <8 x i16> %b, ptr %a) {
define <4 x i32> @load_v4i32_2_1(float %tmp, <4 x i32> %b, ptr %a) {
; CHECK-LABEL: load_v4i32_2_1:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT: mov d1, v1.d[1]
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: mov v0.d[1], v1.d[0]
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/insertextract.ll b/llvm/test/CodeGen/AArch64/insertextract.ll
index facee0829611f..8b65000bd1a1e 100644
--- a/llvm/test/CodeGen/AArch64/insertextract.ll
+++ b/llvm/test/CodeGen/AArch64/insertextract.ll
@@ -60,9 +60,8 @@ define <3 x double> @insert_v3f64_0(<3 x double> %a, double %b, i32 %c) {
; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
; CHECK-SD-NEXT: // kill: def $d3 killed $d3 def $q3
; CHECK-SD-NEXT: mov v0.d[0], v3.d[0]
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: insert_v3f64_0:
@@ -99,9 +98,8 @@ define <3 x double> @insert_v3f64_c(<3 x double> %a, double %b, i32 %c) {
; CHECK-SD-NEXT: str d3, [x8, x9, lsl #3]
; CHECK-SD-NEXT: ldr q0, [sp]
; CHECK-SD-NEXT: ldr d2, [sp, #16]
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: add sp, sp, #32
; CHECK-SD-NEXT: ret
;
@@ -1182,9 +1180,8 @@ define <3 x i64> @insert_v3i64_0(<3 x i64> %a, i64 %b, i32 %c) {
; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
; CHECK-SD-NEXT: mov v0.d[0], x0
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: insert_v3i64_0:
@@ -1221,9 +1218,8 @@ define <3 x i64> @insert_v3i64_c(<3 x i64> %a, i64 %b, i32 %c) {
; CHECK-SD-NEXT: str x0, [x8, x9, lsl #3]
; CHECK-SD-NEXT: ldr q0, [sp]
; CHECK-SD-NEXT: ldr d2, [sp, #16]
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: add sp, sp, #32
; CHECK-SD-NEXT: ret
;
diff --git a/llvm/test/CodeGen/AArch64/itofp.ll b/llvm/test/CodeGen/AArch64/itofp.ll
index 7a963cceb8119..c61b38d73c29d 100644
--- a/llvm/test/CodeGen/AArch64/itofp.ll
+++ b/llvm/test/CodeGen/AArch64/itofp.ll
@@ -1191,118 +1191,36 @@ entry:
}
define <3 x double> @stofp_v3i64_v3f64(<3 x i64> %a) {
-; CHECK-NOFP16-SD-LABEL: stofp_v3i64_v3f64:
-; CHECK-NOFP16-SD: // %bb.0: // %entry
-; CHECK-NOFP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NOFP16-SD-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-NOFP16-SD-NEXT: // kill: def $d2 killed $d2 def $q2
-; CHECK-NOFP16-SD-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NOFP16-SD-NEXT: scvtf v2.2d, v2.2d
-; CHECK-NOFP16-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-NOFP16-SD-NEXT: scvtf v0.2d, v0.2d
-; CHECK-NOFP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NOFP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NOFP16-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
-; CHECK-NOFP16-SD-NEXT: ret
-;
-; CHECK-FP16-SD-LABEL: stofp_v3i64_v3f64:
-; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-FP16-SD-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-FP16-SD-NEXT: // kill: def $d2 killed $d2 def $q2
-; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-FP16-SD-NEXT: scvtf v2.2d, v2.2d
-; CHECK-FP16-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-FP16-SD-NEXT: scvtf v0.2d, v0.2d
-; CHECK-FP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-FP16-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
-; CHECK-FP16-SD-NEXT: ret
-;
-; CHECK-NOFP16-GI-LABEL: stofp_v3i64_v3f64:
-; CHECK-NOFP16-GI: // %bb.0: // %entry
-; CHECK-NOFP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NOFP16-GI-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-NOFP16-GI-NEXT: // kill: def $d2 killed $d2 def $q2
-; CHECK-NOFP16-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NOFP16-GI-NEXT: scvtf v2.2d, v2.2d
-; CHECK-NOFP16-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-NOFP16-GI-NEXT: scvtf v0.2d, v0.2d
-; CHECK-NOFP16-GI-NEXT: mov d1, v0.d[1]
-; CHECK-NOFP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NOFP16-GI-NEXT: ret
-;
-; CHECK-FP16-GI-LABEL: stofp_v3i64_v3f64:
-; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-FP16-GI-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-FP16-GI-NEXT: // kill: def $d2 killed $d2 def $q2
-; CHECK-FP16-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-FP16-GI-NEXT: scvtf v2.2d, v2.2d
-; CHECK-FP16-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-FP16-GI-NEXT: scvtf v0.2d, v0.2d
-; CHECK-FP16-GI-NEXT: mov d1, v0.d[1]
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-FP16-GI-NEXT: ret
+; CHECK-LABEL: stofp_v3i64_v3f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: scvtf v2.2d, v2.2d
+; CHECK-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-NEXT: scvtf v0.2d, v0.2d
+; CHECK-NEXT: mov d1, v0.d[1]
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
entry:
%c = sitofp <3 x i64> %a to <3 x double>
ret <3 x double> %c
}
define <3 x double> @utofp_v3i64_v3f64(<3 x i64> %a) {
-; CHECK-NOFP16-SD-LABEL: utofp_v3i64_v3f64:
-; CHECK-NOFP16-SD: // %bb.0: // %entry
-; CHECK-NOFP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NOFP16-SD-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-NOFP16-SD-NEXT: // kill: def $d2 killed $d2 def $q2
-; CHECK-NOFP16-SD-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NOFP16-SD-NEXT: ucvtf v2.2d, v2.2d
-; CHECK-NOFP16-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-NOFP16-SD-NEXT: ucvtf v0.2d, v0.2d
-; CHECK-NOFP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NOFP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NOFP16-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
-; CHECK-NOFP16-SD-NEXT: ret
-;
-; CHECK-FP16-SD-LABEL: utofp_v3i64_v3f64:
-; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-FP16-SD-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-FP16-SD-NEXT: // kill: def $d2 killed $d2 def $q2
-; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-FP16-SD-NEXT: ucvtf v2.2d, v2.2d
-; CHECK-FP16-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-FP16-SD-NEXT: ucvtf v0.2d, v0.2d
-; CHECK-FP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-FP16-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
-; CHECK-FP16-SD-NEXT: ret
-;
-; CHECK-NOFP16-GI-LABEL: utofp_v3i64_v3f64:
-; CHECK-NOFP16-GI: // %bb.0: // %entry
-; CHECK-NOFP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NOFP16-GI-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-NOFP16-GI-NEXT: // kill: def $d2 killed $d2 def $q2
-; CHECK-NOFP16-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NOFP16-GI-NEXT: ucvtf v2.2d, v2.2d
-; CHECK-NOFP16-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-NOFP16-GI-NEXT: ucvtf v0.2d, v0.2d
-; CHECK-NOFP16-GI-NEXT: mov d1, v0.d[1]
-; CHECK-NOFP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NOFP16-GI-NEXT: ret
-;
-; CHECK-FP16-GI-LABEL: utofp_v3i64_v3f64:
-; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-FP16-GI-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-FP16-GI-NEXT: // kill: def $d2 killed $d2 def $q2
-; CHECK-FP16-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-FP16-GI-NEXT: ucvtf v2.2d, v2.2d
-; CHECK-FP16-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-FP16-GI-NEXT: ucvtf v0.2d, v0.2d
-; CHECK-FP16-GI-NEXT: mov d1, v0.d[1]
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-FP16-GI-NEXT: ret
+; CHECK-LABEL: utofp_v3i64_v3f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ucvtf v2.2d, v2.2d
+; CHECK-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-NEXT: ucvtf v0.2d, v0.2d
+; CHECK-NEXT: mov d1, v0.d[1]
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
entry:
%c = uitofp <3 x i64> %a to <3 x double>
ret <3 x double> %c
@@ -1353,102 +1271,32 @@ entry:
}
define <3 x double> @stofp_v3i32_v3f64(<3 x i32> %a) {
-; CHECK-NOFP16-SD-LABEL: stofp_v3i32_v3f64:
-; CHECK-NOFP16-SD: // %bb.0: // %entry
-; CHECK-NOFP16-SD-NEXT: sshll v1.2d, v0.2s, #0
-; CHECK-NOFP16-SD-NEXT: sshll2 v0.2d, v0.4s, #0
-; CHECK-NOFP16-SD-NEXT: scvtf v3.2d, v1.2d
-; CHECK-NOFP16-SD-NEXT: scvtf v2.2d, v0.2d
-; CHECK-NOFP16-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-NOFP16-SD-NEXT: fmov d0, d3
-; CHECK-NOFP16-SD-NEXT: ext v1.16b, v3.16b, v3.16b, #8
-; CHECK-NOFP16-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
-; CHECK-NOFP16-SD-NEXT: ret
-;
-; CHECK-FP16-SD-LABEL: stofp_v3i32_v3f64:
-; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: sshll v1.2d, v0.2s, #0
-; CHECK-FP16-SD-NEXT: sshll2 v0.2d, v0.4s, #0
-; CHECK-FP16-SD-NEXT: scvtf v3.2d, v1.2d
-; CHECK-FP16-SD-NEXT: scvtf v2.2d, v0.2d
-; CHECK-FP16-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-FP16-SD-NEXT: fmov d0, d3
-; CHECK-FP16-SD-NEXT: ext v1.16b, v3.16b, v3.16b, #8
-; CHECK-FP16-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
-; CHECK-FP16-SD-NEXT: ret
-;
-; CHECK-NOFP16-GI-LABEL: stofp_v3i32_v3f64:
-; CHECK-NOFP16-GI: // %bb.0: // %entry
-; CHECK-NOFP16-GI-NEXT: sshll v1.2d, v0.2s, #0
-; CHECK-NOFP16-GI-NEXT: sshll2 v0.2d, v0.4s, #0
-; CHECK-NOFP16-GI-NEXT: scvtf v3.2d, v1.2d
-; CHECK-NOFP16-GI-NEXT: scvtf v2.2d, v0.2d
-; CHECK-NOFP16-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-NOFP16-GI-NEXT: mov d1, v3.d[1]
-; CHECK-NOFP16-GI-NEXT: fmov d0, d3
-; CHECK-NOFP16-GI-NEXT: ret
-;
-; CHECK-FP16-GI-LABEL: stofp_v3i32_v3f64:
-; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: sshll v1.2d, v0.2s, #0
-; CHECK-FP16-GI-NEXT: sshll2 v0.2d, v0.4s, #0
-; CHECK-FP16-GI-NEXT: scvtf v3.2d, v1.2d
-; CHECK-FP16-GI-NEXT: scvtf v2.2d, v0.2d
-; CHECK-FP16-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-FP16-GI-NEXT: mov d1, v3.d[1]
-; CHECK-FP16-GI-NEXT: fmov d0, d3
-; CHECK-FP16-GI-NEXT: ret
+; CHECK-LABEL: stofp_v3i32_v3f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sshll v1.2d, v0.2s, #0
+; CHECK-NEXT: sshll2 v0.2d, v0.4s, #0
+; CHECK-NEXT: scvtf v3.2d, v1.2d
+; CHECK-NEXT: scvtf v2.2d, v0.2d
+; CHECK-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-NEXT: mov d1, v3.d[1]
+; CHECK-NEXT: fmov d0, d3
+; CHECK-NEXT: ret
entry:
%c = sitofp <3 x i32> %a to <3 x double>
ret <3 x double> %c
}
define <3 x double> @utofp_v3i32_v3f64(<3 x i32> %a) {
-; CHECK-NOFP16-SD-LABEL: utofp_v3i32_v3f64:
-; CHECK-NOFP16-SD: // %bb.0: // %entry
-; CHECK-NOFP16-SD-NEXT: ushll v1.2d, v0.2s, #0
-; CHECK-NOFP16-SD-NEXT: ushll2 v0.2d, v0.4s, #0
-; CHECK-NOFP16-SD-NEXT: ucvtf v3.2d, v1.2d
-; CHECK-NOFP16-SD-NEXT: ucvtf v2.2d, v0.2d
-; CHECK-NOFP16-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-NOFP16-SD-NEXT: fmov d0, d3
-; CHECK-NOFP16-SD-NEXT: ext v1.16b, v3.16b, v3.16b, #8
-; CHECK-NOFP16-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
-; CHECK-NOFP16-SD-NEXT: ret
-;
-; CHECK-FP16-SD-LABEL: utofp_v3i32_v3f64:
-; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: ushll v1.2d, v0.2s, #0
-; CHECK-FP16-SD-NEXT: ushll2 v0.2d, v0.4s, #0
-; CHECK-FP16-SD-NEXT: ucvtf v3.2d, v1.2d
-; CHECK-FP16-SD-NEXT: ucvtf v2.2d, v0.2d
-; CHECK-FP16-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-FP16-SD-NEXT: fmov d0, d3
-; CHECK-FP16-SD-NEXT: ext v1.16b, v3.16b, v3.16b, #8
-; CHECK-FP16-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
-; CHECK-FP16-SD-NEXT: ret
-;
-; CHECK-NOFP16-GI-LABEL: utofp_v3i32_v3f64:
-; CHECK-NOFP16-GI: // %bb.0: // %entry
-; CHECK-NOFP16-GI-NEXT: ushll v1.2d, v0.2s, #0
-; CHECK-NOFP16-GI-NEXT: ushll2 v0.2d, v0.4s, #0
-; CHECK-NOFP16-GI-NEXT: ucvtf v3.2d, v1.2d
-; CHECK-NOFP16-GI-NEXT: ucvtf v2.2d, v0.2d
-; CHECK-NOFP16-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-NOFP16-GI-NEXT: mov d1, v3.d[1]
-; CHECK-NOFP16-GI-NEXT: fmov d0, d3
-; CHECK-NOFP16-GI-NEXT: ret
-;
-; CHECK-FP16-GI-LABEL: utofp_v3i32_v3f64:
-; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: ushll v1.2d, v0.2s, #0
-; CHECK-FP16-GI-NEXT: ushll2 v0.2d, v0.4s, #0
-; CHECK-FP16-GI-NEXT: ucvtf v3.2d, v1.2d
-; CHECK-FP16-GI-NEXT: ucvtf v2.2d, v0.2d
-; CHECK-FP16-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-FP16-GI-NEXT: mov d1, v3.d[1]
-; CHECK-FP16-GI-NEXT: fmov d0, d3
-; CHECK-FP16-GI-NEXT: ret
+; CHECK-LABEL: utofp_v3i32_v3f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ushll v1.2d, v0.2s, #0
+; CHECK-NEXT: ushll2 v0.2d, v0.4s, #0
+; CHECK-NEXT: ucvtf v3.2d, v1.2d
+; CHECK-NEXT: ucvtf v2.2d, v0.2d
+; CHECK-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-NEXT: mov d1, v3.d[1]
+; CHECK-NEXT: fmov d0, d3
+; CHECK-NEXT: ret
entry:
%c = uitofp <3 x i32> %a to <3 x double>
ret <3 x double> %c
@@ -1709,110 +1557,34 @@ entry:
}
define <3 x double> @stofp_v3i16_v3f64(<3 x i16> %a) {
-; CHECK-NOFP16-SD-LABEL: stofp_v3i16_v3f64:
-; CHECK-NOFP16-SD: // %bb.0: // %entry
-; CHECK-NOFP16-SD-NEXT: sshll v1.4s, v0.4h, #0
-; CHECK-NOFP16-SD-NEXT: sshll v0.2d, v1.2s, #0
-; CHECK-NOFP16-SD-NEXT: sshll2 v1.2d, v1.4s, #0
-; CHECK-NOFP16-SD-NEXT: scvtf v0.2d, v0.2d
-; CHECK-NOFP16-SD-NEXT: scvtf v2.2d, v1.2d
-; CHECK-NOFP16-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-NOFP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NOFP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NOFP16-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
-; CHECK-NOFP16-SD-NEXT: ret
-;
-; CHECK-FP16-SD-LABEL: stofp_v3i16_v3f64:
-; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: sshll v1.4s, v0.4h, #0
-; CHECK-FP16-SD-NEXT: sshll v0.2d, v1.2s, #0
-; CHECK-FP16-SD-NEXT: sshll2 v1.2d, v1.4s, #0
-; CHECK-FP16-SD-NEXT: scvtf v0.2d, v0.2d
-; CHECK-FP16-SD-NEXT: scvtf v2.2d, v1.2d
-; CHECK-FP16-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-FP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-FP16-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
-; CHECK-FP16-SD-NEXT: ret
-;
-; CHECK-NOFP16-GI-LABEL: stofp_v3i16_v3f64:
-; CHECK-NOFP16-GI: // %bb.0: // %entry
-; CHECK-NOFP16-GI-NEXT: sshll v1.4s, v0.4h, #0
-; CHECK-NOFP16-GI-NEXT: sshll v0.2d, v1.2s, #0
-; CHECK-NOFP16-GI-NEXT: sshll2 v1.2d, v1.4s, #0
-; CHECK-NOFP16-GI-NEXT: scvtf v0.2d, v0.2d
-; CHECK-NOFP16-GI-NEXT: scvtf v2.2d, v1.2d
-; CHECK-NOFP16-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-NOFP16-GI-NEXT: mov d1, v0.d[1]
-; CHECK-NOFP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NOFP16-GI-NEXT: ret
-;
-; CHECK-FP16-GI-LABEL: stofp_v3i16_v3f64:
-; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: sshll v1.4s, v0.4h, #0
-; CHECK-FP16-GI-NEXT: sshll v0.2d, v1.2s, #0
-; CHECK-FP16-GI-NEXT: sshll2 v1.2d, v1.4s, #0
-; CHECK-FP16-GI-NEXT: scvtf v0.2d, v0.2d
-; CHECK-FP16-GI-NEXT: scvtf v2.2d, v1.2d
-; CHECK-FP16-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-FP16-GI-NEXT: mov d1, v0.d[1]
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-FP16-GI-NEXT: ret
+; CHECK-LABEL: stofp_v3i16_v3f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sshll v1.4s, v0.4h, #0
+; CHECK-NEXT: sshll v0.2d, v1.2s, #0
+; CHECK-NEXT: sshll2 v1.2d, v1.4s, #0
+; CHECK-NEXT: scvtf v0.2d, v0.2d
+; CHECK-NEXT: scvtf v2.2d, v1.2d
+; CHECK-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-NEXT: mov d1, v0.d[1]
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
entry:
%c = sitofp <3 x i16> %a to <3 x double>
ret <3 x double> %c
}
define <3 x double> @utofp_v3i16_v3f64(<3 x i16> %a) {
-; CHECK-NOFP16-SD-LABEL: utofp_v3i16_v3f64:
-; CHECK-NOFP16-SD: // %bb.0: // %entry
-; CHECK-NOFP16-SD-NEXT: ushll v1.4s, v0.4h, #0
-; CHECK-NOFP16-SD-NEXT: ushll v0.2d, v1.2s, #0
-; CHECK-NOFP16-SD-NEXT: ushll2 v1.2d, v1.4s, #0
-; CHECK-NOFP16-SD-NEXT: ucvtf v0.2d, v0.2d
-; CHECK-NOFP16-SD-NEXT: ucvtf v2.2d, v1.2d
-; CHECK-NOFP16-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-NOFP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NOFP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NOFP16-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
-; CHECK-NOFP16-SD-NEXT: ret
-;
-; CHECK-FP16-SD-LABEL: utofp_v3i16_v3f64:
-; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: ushll v1.4s, v0.4h, #0
-; CHECK-FP16-SD-NEXT: ushll v0.2d, v1.2s, #0
-; CHECK-FP16-SD-NEXT: ushll2 v1.2d, v1.4s, #0
-; CHECK-FP16-SD-NEXT: ucvtf v0.2d, v0.2d
-; CHECK-FP16-SD-NEXT: ucvtf v2.2d, v1.2d
-; CHECK-FP16-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-FP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-FP16-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
-; CHECK-FP16-SD-NEXT: ret
-;
-; CHECK-NOFP16-GI-LABEL: utofp_v3i16_v3f64:
-; CHECK-NOFP16-GI: // %bb.0: // %entry
-; CHECK-NOFP16-GI-NEXT: ushll v1.4s, v0.4h, #0
-; CHECK-NOFP16-GI-NEXT: ushll v0.2d, v1.2s, #0
-; CHECK-NOFP16-GI-NEXT: ushll2 v1.2d, v1.4s, #0
-; CHECK-NOFP16-GI-NEXT: ucvtf v0.2d, v0.2d
-; CHECK-NOFP16-GI-NEXT: ucvtf v2.2d, v1.2d
-; CHECK-NOFP16-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-NOFP16-GI-NEXT: mov d1, v0.d[1]
-; CHECK-NOFP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NOFP16-GI-NEXT: ret
-;
-; CHECK-FP16-GI-LABEL: utofp_v3i16_v3f64:
-; CHECK-FP16-GI: // %bb.0: // %entry
-; CHECK-FP16-GI-NEXT: ushll v1.4s, v0.4h, #0
-; CHECK-FP16-GI-NEXT: ushll v0.2d, v1.2s, #0
-; CHECK-FP16-GI-NEXT: ushll2 v1.2d, v1.4s, #0
-; CHECK-FP16-GI-NEXT: ucvtf v0.2d, v0.2d
-; CHECK-FP16-GI-NEXT: ucvtf v2.2d, v1.2d
-; CHECK-FP16-GI-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-FP16-GI-NEXT: mov d1, v0.d[1]
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-FP16-GI-NEXT: ret
+; CHECK-LABEL: utofp_v3i16_v3f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ushll v1.4s, v0.4h, #0
+; CHECK-NEXT: ushll v0.2d, v1.2s, #0
+; CHECK-NEXT: ushll2 v1.2d, v1.4s, #0
+; CHECK-NEXT: ucvtf v0.2d, v0.2d
+; CHECK-NEXT: ucvtf v2.2d, v1.2d
+; CHECK-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-NEXT: mov d1, v0.d[1]
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
entry:
%c = uitofp <3 x i16> %a to <3 x double>
ret <3 x double> %c
@@ -2313,9 +2085,8 @@ define <3 x double> @stofp_v3i8_v3f64(<3 x i8> %a) {
; CHECK-NOFP16-SD-NEXT: sshll v0.2d, v0.2s, #0
; CHECK-NOFP16-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-NOFP16-SD-NEXT: scvtf v0.2d, v0.2d
-; CHECK-NOFP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NOFP16-SD-NEXT: mov d1, v0.d[1]
; CHECK-NOFP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NOFP16-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-NOFP16-SD-NEXT: ret
;
; CHECK-FP16-SD-LABEL: stofp_v3i8_v3f64:
@@ -2332,9 +2103,8 @@ define <3 x double> @stofp_v3i8_v3f64(<3 x i8> %a) {
; CHECK-FP16-SD-NEXT: sshll v0.2d, v0.2s, #0
; CHECK-FP16-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-FP16-SD-NEXT: scvtf v0.2d, v0.2d
-; CHECK-FP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-FP16-SD-NEXT: mov d1, v0.d[1]
; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-FP16-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-NOFP16-GI-LABEL: stofp_v3i8_v3f64:
@@ -2399,9 +2169,8 @@ define <3 x double> @utofp_v3i8_v3f64(<3 x i8> %a) {
; CHECK-NOFP16-SD-NEXT: ucvtf v0.2d, v0.2d
; CHECK-NOFP16-SD-NEXT: ucvtf v2.2d, v1.2d
; CHECK-NOFP16-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-NOFP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NOFP16-SD-NEXT: mov d1, v0.d[1]
; CHECK-NOFP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NOFP16-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-NOFP16-SD-NEXT: ret
;
; CHECK-FP16-SD-LABEL: utofp_v3i8_v3f64:
@@ -2417,9 +2186,8 @@ define <3 x double> @utofp_v3i8_v3f64(<3 x i8> %a) {
; CHECK-FP16-SD-NEXT: ucvtf v0.2d, v0.2d
; CHECK-FP16-SD-NEXT: ucvtf v2.2d, v1.2d
; CHECK-FP16-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-FP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-FP16-SD-NEXT: mov d1, v0.d[1]
; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-FP16-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-NOFP16-GI-LABEL: utofp_v3i8_v3f64:
@@ -2474,7 +2242,7 @@ define <4 x double> @stofp_v4i8_v4f64(<4 x i8> %a) {
; CHECK-NOFP16-SD-LABEL: stofp_v4i8_v4f64:
; CHECK-NOFP16-SD: // %bb.0: // %entry
; CHECK-NOFP16-SD-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-NOFP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NOFP16-SD-NEXT: mov d1, v0.d[1]
; CHECK-NOFP16-SD-NEXT: shl v0.2s, v0.2s, #24
; CHECK-NOFP16-SD-NEXT: sshr v0.2s, v0.2s, #24
; CHECK-NOFP16-SD-NEXT: shl v1.2s, v1.2s, #24
@@ -2488,7 +2256,7 @@ define <4 x double> @stofp_v4i8_v4f64(<4 x i8> %a) {
; CHECK-FP16-SD-LABEL: stofp_v4i8_v4f64:
; CHECK-FP16-SD: // %bb.0: // %entry
; CHECK-FP16-SD-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-FP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-FP16-SD-NEXT: mov d1, v0.d[1]
; CHECK-FP16-SD-NEXT: shl v0.2s, v0.2s, #24
; CHECK-FP16-SD-NEXT: sshr v0.2s, v0.2s, #24
; CHECK-FP16-SD-NEXT: shl v1.2s, v1.2s, #24
@@ -2534,7 +2302,7 @@ define <4 x double> @utofp_v4i8_v4f64(<4 x i8> %a) {
; CHECK-NOFP16-SD: // %bb.0: // %entry
; CHECK-NOFP16-SD-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-NOFP16-SD-NEXT: movi d1, #0x0000ff000000ff
-; CHECK-NOFP16-SD-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-NOFP16-SD-NEXT: mov d2, v0.d[1]
; CHECK-NOFP16-SD-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NOFP16-SD-NEXT: and v1.8b, v2.8b, v1.8b
; CHECK-NOFP16-SD-NEXT: ushll v0.2d, v0.2s, #0
@@ -2547,7 +2315,7 @@ define <4 x double> @utofp_v4i8_v4f64(<4 x i8> %a) {
; CHECK-FP16-SD: // %bb.0: // %entry
; CHECK-FP16-SD-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-FP16-SD-NEXT: movi d1, #0x0000ff000000ff
-; CHECK-FP16-SD-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-FP16-SD-NEXT: mov d2, v0.d[1]
; CHECK-FP16-SD-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-FP16-SD-NEXT: and v1.8b, v2.8b, v1.8b
; CHECK-FP16-SD-NEXT: ushll v0.2d, v0.2s, #0
@@ -2767,7 +2535,7 @@ entry:
define <16 x double> @stofp_v16i8_v16f64(<16 x i8> %a) {
; CHECK-NOFP16-SD-LABEL: stofp_v16i8_v16f64:
; CHECK-NOFP16-SD: // %bb.0: // %entry
-; CHECK-NOFP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NOFP16-SD-NEXT: mov d1, v0.d[1]
; CHECK-NOFP16-SD-NEXT: mov b2, v0.b[0]
; CHECK-NOFP16-SD-NEXT: mov b3, v0.b[2]
; CHECK-NOFP16-SD-NEXT: mov b4, v0.b[4]
@@ -2820,7 +2588,7 @@ define <16 x double> @stofp_v16i8_v16f64(<16 x i8> %a) {
;
; CHECK-FP16-SD-LABEL: stofp_v16i8_v16f64:
; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-FP16-SD-NEXT: mov d1, v0.d[1]
; CHECK-FP16-SD-NEXT: mov b2, v0.b[0]
; CHECK-FP16-SD-NEXT: mov b3, v0.b[2]
; CHECK-FP16-SD-NEXT: mov b4, v0.b[4]
@@ -2930,7 +2698,7 @@ entry:
define <16 x double> @utofp_v16i8_v16f64(<16 x i8> %a) {
; CHECK-NOFP16-SD-LABEL: utofp_v16i8_v16f64:
; CHECK-NOFP16-SD: // %bb.0: // %entry
-; CHECK-NOFP16-SD-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-NOFP16-SD-NEXT: mov d2, v0.d[1]
; CHECK-NOFP16-SD-NEXT: mov b3, v0.b[0]
; CHECK-NOFP16-SD-NEXT: mov b4, v0.b[2]
; CHECK-NOFP16-SD-NEXT: mov b5, v0.b[4]
@@ -2976,7 +2744,7 @@ define <16 x double> @utofp_v16i8_v16f64(<16 x i8> %a) {
;
; CHECK-FP16-SD-LABEL: utofp_v16i8_v16f64:
; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-FP16-SD-NEXT: mov d2, v0.d[1]
; CHECK-FP16-SD-NEXT: mov b3, v0.b[0]
; CHECK-FP16-SD-NEXT: mov b4, v0.b[2]
; CHECK-FP16-SD-NEXT: mov b5, v0.b[4]
@@ -3079,7 +2847,7 @@ entry:
define <32 x double> @stofp_v32i8_v32f64(<32 x i8> %a) {
; CHECK-NOFP16-SD-LABEL: stofp_v32i8_v32f64:
; CHECK-NOFP16-SD: // %bb.0: // %entry
-; CHECK-NOFP16-SD-NEXT: ext v3.16b, v0.16b, v0.16b, #8
+; CHECK-NOFP16-SD-NEXT: mov d3, v0.d[1]
; CHECK-NOFP16-SD-NEXT: mov b5, v1.b[6]
; CHECK-NOFP16-SD-NEXT: mov b17, v1.b[4]
; CHECK-NOFP16-SD-NEXT: mov b20, v1.b[2]
@@ -3087,7 +2855,7 @@ define <32 x double> @stofp_v32i8_v32f64(<32 x i8> %a) {
; CHECK-NOFP16-SD-NEXT: mov b18, v0.b[0]
; CHECK-NOFP16-SD-NEXT: mov b19, v0.b[6]
; CHECK-NOFP16-SD-NEXT: mov b22, v0.b[4]
-; CHECK-NOFP16-SD-NEXT: ext v16.16b, v1.16b, v1.16b, #8
+; CHECK-NOFP16-SD-NEXT: mov d16, v1.d[1]
; CHECK-NOFP16-SD-NEXT: mov b2, v3.b[0]
; CHECK-NOFP16-SD-NEXT: mov b4, v3.b[2]
; CHECK-NOFP16-SD-NEXT: mov b6, v3.b[4]
@@ -3189,7 +2957,7 @@ define <32 x double> @stofp_v32i8_v32f64(<32 x i8> %a) {
;
; CHECK-FP16-SD-LABEL: stofp_v32i8_v32f64:
; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: ext v3.16b, v0.16b, v0.16b, #8
+; CHECK-FP16-SD-NEXT: mov d3, v0.d[1]
; CHECK-FP16-SD-NEXT: mov b5, v1.b[6]
; CHECK-FP16-SD-NEXT: mov b17, v1.b[4]
; CHECK-FP16-SD-NEXT: mov b20, v1.b[2]
@@ -3197,7 +2965,7 @@ define <32 x double> @stofp_v32i8_v32f64(<32 x i8> %a) {
; CHECK-FP16-SD-NEXT: mov b18, v0.b[0]
; CHECK-FP16-SD-NEXT: mov b19, v0.b[6]
; CHECK-FP16-SD-NEXT: mov b22, v0.b[4]
-; CHECK-FP16-SD-NEXT: ext v16.16b, v1.16b, v1.16b, #8
+; CHECK-FP16-SD-NEXT: mov d16, v1.d[1]
; CHECK-FP16-SD-NEXT: mov b2, v3.b[0]
; CHECK-FP16-SD-NEXT: mov b4, v3.b[2]
; CHECK-FP16-SD-NEXT: mov b6, v3.b[4]
@@ -3418,7 +3186,7 @@ define <32 x double> @utofp_v32i8_v32f64(<32 x i8> %a) {
; CHECK-NOFP16-SD: // %bb.0: // %entry
; CHECK-NOFP16-SD-NEXT: mov b6, v1.b[6]
; CHECK-NOFP16-SD-NEXT: mov b7, v1.b[4]
-; CHECK-NOFP16-SD-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-NOFP16-SD-NEXT: mov d3, v1.d[1]
; CHECK-NOFP16-SD-NEXT: mov b16, v1.b[2]
; CHECK-NOFP16-SD-NEXT: mov b17, v1.b[0]
; CHECK-NOFP16-SD-NEXT: mov b19, v0.b[6]
@@ -3426,7 +3194,7 @@ define <32 x double> @utofp_v32i8_v32f64(<32 x i8> %a) {
; CHECK-NOFP16-SD-NEXT: movi d5, #0x0000ff000000ff
; CHECK-NOFP16-SD-NEXT: mov b24, v0.b[2]
; CHECK-NOFP16-SD-NEXT: mov b25, v0.b[0]
-; CHECK-NOFP16-SD-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-NOFP16-SD-NEXT: mov d2, v0.d[1]
; CHECK-NOFP16-SD-NEXT: mov v6.b[4], v1.b[7]
; CHECK-NOFP16-SD-NEXT: mov v7.b[4], v1.b[5]
; CHECK-NOFP16-SD-NEXT: mov b18, v3.b[0]
@@ -3513,7 +3281,7 @@ define <32 x double> @utofp_v32i8_v32f64(<32 x i8> %a) {
; CHECK-FP16-SD: // %bb.0: // %entry
; CHECK-FP16-SD-NEXT: mov b6, v1.b[6]
; CHECK-FP16-SD-NEXT: mov b7, v1.b[4]
-; CHECK-FP16-SD-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-FP16-SD-NEXT: mov d3, v1.d[1]
; CHECK-FP16-SD-NEXT: mov b16, v1.b[2]
; CHECK-FP16-SD-NEXT: mov b17, v1.b[0]
; CHECK-FP16-SD-NEXT: mov b19, v0.b[6]
@@ -3521,7 +3289,7 @@ define <32 x double> @utofp_v32i8_v32f64(<32 x i8> %a) {
; CHECK-FP16-SD-NEXT: movi d5, #0x0000ff000000ff
; CHECK-FP16-SD-NEXT: mov b24, v0.b[2]
; CHECK-FP16-SD-NEXT: mov b25, v0.b[0]
-; CHECK-FP16-SD-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-FP16-SD-NEXT: mov d2, v0.d[1]
; CHECK-FP16-SD-NEXT: mov v6.b[4], v1.b[7]
; CHECK-FP16-SD-NEXT: mov v7.b[4], v1.b[5]
; CHECK-FP16-SD-NEXT: mov b18, v3.b[0]
@@ -5093,7 +4861,7 @@ entry:
define <16 x float> @stofp_v16i8_v16f32(<16 x i8> %a) {
; CHECK-NOFP16-SD-LABEL: stofp_v16i8_v16f32:
; CHECK-NOFP16-SD: // %bb.0: // %entry
-; CHECK-NOFP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NOFP16-SD-NEXT: mov d1, v0.d[1]
; CHECK-NOFP16-SD-NEXT: zip1 v2.8b, v0.8b, v0.8b
; CHECK-NOFP16-SD-NEXT: zip2 v0.8b, v0.8b, v0.8b
; CHECK-NOFP16-SD-NEXT: zip1 v3.8b, v1.8b, v0.8b
@@ -5118,7 +4886,7 @@ define <16 x float> @stofp_v16i8_v16f32(<16 x i8> %a) {
;
; CHECK-FP16-SD-LABEL: stofp_v16i8_v16f32:
; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-FP16-SD-NEXT: mov d1, v0.d[1]
; CHECK-FP16-SD-NEXT: zip1 v2.8b, v0.8b, v0.8b
; CHECK-FP16-SD-NEXT: zip2 v0.8b, v0.8b, v0.8b
; CHECK-FP16-SD-NEXT: zip1 v3.8b, v1.8b, v0.8b
@@ -5176,7 +4944,7 @@ entry:
define <16 x float> @utofp_v16i8_v16f32(<16 x i8> %a) {
; CHECK-NOFP16-SD-LABEL: utofp_v16i8_v16f32:
; CHECK-NOFP16-SD: // %bb.0: // %entry
-; CHECK-NOFP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NOFP16-SD-NEXT: mov d1, v0.d[1]
; CHECK-NOFP16-SD-NEXT: zip1 v2.8b, v0.8b, v0.8b
; CHECK-NOFP16-SD-NEXT: zip2 v0.8b, v0.8b, v0.8b
; CHECK-NOFP16-SD-NEXT: zip1 v3.8b, v1.8b, v0.8b
@@ -5197,7 +4965,7 @@ define <16 x float> @utofp_v16i8_v16f32(<16 x i8> %a) {
;
; CHECK-FP16-SD-LABEL: utofp_v16i8_v16f32:
; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-FP16-SD-NEXT: mov d1, v0.d[1]
; CHECK-FP16-SD-NEXT: zip1 v2.8b, v0.8b, v0.8b
; CHECK-FP16-SD-NEXT: zip2 v0.8b, v0.8b, v0.8b
; CHECK-FP16-SD-NEXT: zip1 v3.8b, v1.8b, v0.8b
@@ -5251,8 +5019,8 @@ entry:
define <32 x float> @stofp_v32i8_v32f32(<32 x i8> %a) {
; CHECK-NOFP16-SD-LABEL: stofp_v32i8_v32f32:
; CHECK-NOFP16-SD: // %bb.0: // %entry
-; CHECK-NOFP16-SD-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-NOFP16-SD-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-NOFP16-SD-NEXT: mov d2, v0.d[1]
+; CHECK-NOFP16-SD-NEXT: mov d3, v1.d[1]
; CHECK-NOFP16-SD-NEXT: zip1 v4.8b, v0.8b, v0.8b
; CHECK-NOFP16-SD-NEXT: zip2 v0.8b, v0.8b, v0.8b
; CHECK-NOFP16-SD-NEXT: shl v4.4h, v4.4h, #8
@@ -5287,9 +5055,9 @@ define <32 x float> @stofp_v32i8_v32f32(<32 x i8> %a) {
; CHECK-NOFP16-SD-NEXT: sshll v7.4s, v7.4h, #0
; CHECK-NOFP16-SD-NEXT: sshll v19.4s, v3.4h, #0
; CHECK-NOFP16-SD-NEXT: scvtf v1.4s, v16.4s
-; CHECK-NOFP16-SD-NEXT: scvtf v4.4s, v5.4s
; CHECK-NOFP16-SD-NEXT: scvtf v2.4s, v6.4s
; CHECK-NOFP16-SD-NEXT: scvtf v3.4s, v17.4s
+; CHECK-NOFP16-SD-NEXT: scvtf v4.4s, v5.4s
; CHECK-NOFP16-SD-NEXT: scvtf v5.4s, v18.4s
; CHECK-NOFP16-SD-NEXT: scvtf v6.4s, v7.4s
; CHECK-NOFP16-SD-NEXT: scvtf v7.4s, v19.4s
@@ -5297,8 +5065,8 @@ define <32 x float> @stofp_v32i8_v32f32(<32 x i8> %a) {
;
; CHECK-FP16-SD-LABEL: stofp_v32i8_v32f32:
; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-FP16-SD-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-FP16-SD-NEXT: mov d2, v0.d[1]
+; CHECK-FP16-SD-NEXT: mov d3, v1.d[1]
; CHECK-FP16-SD-NEXT: zip1 v4.8b, v0.8b, v0.8b
; CHECK-FP16-SD-NEXT: zip2 v0.8b, v0.8b, v0.8b
; CHECK-FP16-SD-NEXT: shl v4.4h, v4.4h, #8
@@ -5333,9 +5101,9 @@ define <32 x float> @stofp_v32i8_v32f32(<32 x i8> %a) {
; CHECK-FP16-SD-NEXT: sshll v7.4s, v7.4h, #0
; CHECK-FP16-SD-NEXT: sshll v19.4s, v3.4h, #0
; CHECK-FP16-SD-NEXT: scvtf v1.4s, v16.4s
-; CHECK-FP16-SD-NEXT: scvtf v4.4s, v5.4s
; CHECK-FP16-SD-NEXT: scvtf v2.4s, v6.4s
; CHECK-FP16-SD-NEXT: scvtf v3.4s, v17.4s
+; CHECK-FP16-SD-NEXT: scvtf v4.4s, v5.4s
; CHECK-FP16-SD-NEXT: scvtf v5.4s, v18.4s
; CHECK-FP16-SD-NEXT: scvtf v6.4s, v7.4s
; CHECK-FP16-SD-NEXT: scvtf v7.4s, v19.4s
@@ -5396,8 +5164,8 @@ entry:
define <32 x float> @utofp_v32i8_v32f32(<32 x i8> %a) {
; CHECK-NOFP16-SD-LABEL: utofp_v32i8_v32f32:
; CHECK-NOFP16-SD: // %bb.0: // %entry
-; CHECK-NOFP16-SD-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-NOFP16-SD-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-NOFP16-SD-NEXT: mov d2, v0.d[1]
+; CHECK-NOFP16-SD-NEXT: mov d3, v1.d[1]
; CHECK-NOFP16-SD-NEXT: zip1 v4.8b, v0.8b, v0.8b
; CHECK-NOFP16-SD-NEXT: zip2 v0.8b, v0.8b, v0.8b
; CHECK-NOFP16-SD-NEXT: bic v4.4h, #255, lsl #8
@@ -5434,8 +5202,8 @@ define <32 x float> @utofp_v32i8_v32f32(<32 x i8> %a) {
;
; CHECK-FP16-SD-LABEL: utofp_v32i8_v32f32:
; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-FP16-SD-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-FP16-SD-NEXT: mov d2, v0.d[1]
+; CHECK-FP16-SD-NEXT: mov d3, v1.d[1]
; CHECK-FP16-SD-NEXT: zip1 v4.8b, v0.8b, v0.8b
; CHECK-FP16-SD-NEXT: zip2 v0.8b, v0.8b, v0.8b
; CHECK-FP16-SD-NEXT: bic v4.4h, #255, lsl #8
diff --git a/llvm/test/CodeGen/AArch64/neon-abd.ll b/llvm/test/CodeGen/AArch64/neon-abd.ll
index 8c3dec85af8b3..e6c931c6d1834 100644
--- a/llvm/test/CodeGen/AArch64/neon-abd.ll
+++ b/llvm/test/CodeGen/AArch64/neon-abd.ll
@@ -597,7 +597,7 @@ define <8 x i32> @sabd_8h_bv_imm(<8 x i16> %a) {
; CHECK-LABEL: sabd_8h_bv_imm:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x9, #549747425280 // =0x7fff800000
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: adrp x8, .LCPI45_0
; CHECK-NEXT: movk x9, #69, lsl #48
; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI45_0]
@@ -619,7 +619,7 @@ define <8 x i32> @sabd_8h_bv_imm(<8 x i16> %a) {
define <8 x i32> @uabd_8h_bv_imm(<8 x i16> %a) {
; CHECK-LABEL: uabd_8h_bv_imm:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: adrp x8, .LCPI46_0
; CHECK-NEXT: adrp x9, .LCPI46_1
; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI46_0]
diff --git a/llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll b/llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
index dfff35d9eb1b2..709d3d387d3a1 100644
--- a/llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
+++ b/llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
@@ -113,10 +113,10 @@ define <2 x i32> @udot_narrow(<2 x i32> %acc, <8 x i8> %u, <8 x i8> %s) {
; CHECK-NODOT-NEXT: ushll v2.4s, v1.4h, #0
; CHECK-NODOT-NEXT: uaddw v0.4s, v0.4s, v1.4h
; CHECK-NODOT-NEXT: ushll2 v3.4s, v1.8h, #0
-; CHECK-NODOT-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-NODOT-NEXT: ext v2.16b, v2.16b, v2.16b, #8
+; CHECK-NODOT-NEXT: mov d1, v1.d[1]
+; CHECK-NODOT-NEXT: mov d2, v2.d[1]
; CHECK-NODOT-NEXT: add v0.2s, v2.2s, v0.2s
-; CHECK-NODOT-NEXT: ext v2.16b, v3.16b, v3.16b, #8
+; CHECK-NODOT-NEXT: mov d2, v3.d[1]
; CHECK-NODOT-NEXT: uaddw v0.4s, v0.4s, v1.4h
; CHECK-NODOT-NEXT: add v0.2s, v2.2s, v0.2s
; CHECK-NODOT-NEXT: ret
@@ -172,10 +172,10 @@ define <2 x i32> @sdot_narrow(<2 x i32> %acc, <8 x i8> %u, <8 x i8> %s) {
; CHECK-NODOT-NEXT: sshll v2.4s, v1.4h, #0
; CHECK-NODOT-NEXT: saddw v0.4s, v0.4s, v1.4h
; CHECK-NODOT-NEXT: sshll2 v3.4s, v1.8h, #0
-; CHECK-NODOT-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-NODOT-NEXT: ext v2.16b, v2.16b, v2.16b, #8
+; CHECK-NODOT-NEXT: mov d1, v1.d[1]
+; CHECK-NODOT-NEXT: mov d2, v2.d[1]
; CHECK-NODOT-NEXT: add v0.2s, v2.2s, v0.2s
-; CHECK-NODOT-NEXT: ext v2.16b, v3.16b, v3.16b, #8
+; CHECK-NODOT-NEXT: mov d2, v3.d[1]
; CHECK-NODOT-NEXT: saddw v0.4s, v0.4s, v1.4h
; CHECK-NODOT-NEXT: add v0.2s, v2.2s, v0.2s
; CHECK-NODOT-NEXT: ret
@@ -324,11 +324,11 @@ define <2 x i32> @usdot_narrow(<2 x i32> %acc, <8 x i8> %u, <8 x i8> %s) #0{
; CHECK-NODOT-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NODOT-NEXT: smull v3.4s, v2.4h, v1.4h
; CHECK-NODOT-NEXT: smlal v0.4s, v2.4h, v1.4h
-; CHECK-NODOT-NEXT: ext v4.16b, v1.16b, v1.16b, #8
-; CHECK-NODOT-NEXT: ext v5.16b, v2.16b, v2.16b, #8
+; CHECK-NODOT-NEXT: mov d4, v1.d[1]
+; CHECK-NODOT-NEXT: mov d5, v2.d[1]
; CHECK-NODOT-NEXT: smull2 v1.4s, v2.8h, v1.8h
-; CHECK-NODOT-NEXT: ext v3.16b, v3.16b, v3.16b, #8
-; CHECK-NODOT-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECK-NODOT-NEXT: mov d3, v3.d[1]
+; CHECK-NODOT-NEXT: mov d1, v1.d[1]
; CHECK-NODOT-NEXT: add v0.2s, v3.2s, v0.2s
; CHECK-NODOT-NEXT: smlal v0.4s, v5.4h, v4.4h
; CHECK-NODOT-NEXT: add v0.2s, v1.2s, v0.2s
@@ -341,11 +341,11 @@ define <2 x i32> @usdot_narrow(<2 x i32> %acc, <8 x i8> %u, <8 x i8> %s) #0{
; CHECK-DOT-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-DOT-NEXT: smull v3.4s, v2.4h, v1.4h
; CHECK-DOT-NEXT: smlal v0.4s, v2.4h, v1.4h
-; CHECK-DOT-NEXT: ext v4.16b, v1.16b, v1.16b, #8
-; CHECK-DOT-NEXT: ext v5.16b, v2.16b, v2.16b, #8
+; CHECK-DOT-NEXT: mov d4, v1.d[1]
+; CHECK-DOT-NEXT: mov d5, v2.d[1]
; CHECK-DOT-NEXT: smull2 v1.4s, v2.8h, v1.8h
-; CHECK-DOT-NEXT: ext v3.16b, v3.16b, v3.16b, #8
-; CHECK-DOT-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECK-DOT-NEXT: mov d3, v3.d[1]
+; CHECK-DOT-NEXT: mov d1, v1.d[1]
; CHECK-DOT-NEXT: add v0.2s, v3.2s, v0.2s
; CHECK-DOT-NEXT: smlal v0.4s, v5.4h, v4.4h
; CHECK-DOT-NEXT: add v0.2s, v1.2s, v0.2s
@@ -490,11 +490,11 @@ define <2 x i32> @sudot_narrow(<2 x i32> %acc, <8 x i8> %u, <8 x i8> %s) #0{
; CHECK-NODOT-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NODOT-NEXT: smull v3.4s, v2.4h, v1.4h
; CHECK-NODOT-NEXT: smlal v0.4s, v2.4h, v1.4h
-; CHECK-NODOT-NEXT: ext v4.16b, v1.16b, v1.16b, #8
-; CHECK-NODOT-NEXT: ext v5.16b, v2.16b, v2.16b, #8
+; CHECK-NODOT-NEXT: mov d4, v1.d[1]
+; CHECK-NODOT-NEXT: mov d5, v2.d[1]
; CHECK-NODOT-NEXT: smull2 v1.4s, v2.8h, v1.8h
-; CHECK-NODOT-NEXT: ext v3.16b, v3.16b, v3.16b, #8
-; CHECK-NODOT-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECK-NODOT-NEXT: mov d3, v3.d[1]
+; CHECK-NODOT-NEXT: mov d1, v1.d[1]
; CHECK-NODOT-NEXT: add v0.2s, v3.2s, v0.2s
; CHECK-NODOT-NEXT: smlal v0.4s, v5.4h, v4.4h
; CHECK-NODOT-NEXT: add v0.2s, v1.2s, v0.2s
@@ -507,11 +507,11 @@ define <2 x i32> @sudot_narrow(<2 x i32> %acc, <8 x i8> %u, <8 x i8> %s) #0{
; CHECK-DOT-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-DOT-NEXT: smull v3.4s, v2.4h, v1.4h
; CHECK-DOT-NEXT: smlal v0.4s, v2.4h, v1.4h
-; CHECK-DOT-NEXT: ext v4.16b, v1.16b, v1.16b, #8
-; CHECK-DOT-NEXT: ext v5.16b, v2.16b, v2.16b, #8
+; CHECK-DOT-NEXT: mov d4, v1.d[1]
+; CHECK-DOT-NEXT: mov d5, v2.d[1]
; CHECK-DOT-NEXT: smull2 v1.4s, v2.8h, v1.8h
-; CHECK-DOT-NEXT: ext v3.16b, v3.16b, v3.16b, #8
-; CHECK-DOT-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECK-DOT-NEXT: mov d3, v3.d[1]
+; CHECK-DOT-NEXT: mov d1, v1.d[1]
; CHECK-DOT-NEXT: add v0.2s, v3.2s, v0.2s
; CHECK-DOT-NEXT: smlal v0.4s, v5.4h, v4.4h
; CHECK-DOT-NEXT: add v0.2s, v1.2s, v0.2s
@@ -876,10 +876,10 @@ define <2 x i32> @udot_no_bin_op_narrow(<2 x i32> %acc, <8 x i8> %a){
; CHECK-NODOT-NEXT: ushll v2.4s, v1.4h, #0
; CHECK-NODOT-NEXT: uaddw v0.4s, v0.4s, v1.4h
; CHECK-NODOT-NEXT: ushll2 v3.4s, v1.8h, #0
-; CHECK-NODOT-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-NODOT-NEXT: ext v2.16b, v2.16b, v2.16b, #8
+; CHECK-NODOT-NEXT: mov d1, v1.d[1]
+; CHECK-NODOT-NEXT: mov d2, v2.d[1]
; CHECK-NODOT-NEXT: add v0.2s, v2.2s, v0.2s
-; CHECK-NODOT-NEXT: ext v2.16b, v3.16b, v3.16b, #8
+; CHECK-NODOT-NEXT: mov d2, v3.d[1]
; CHECK-NODOT-NEXT: uaddw v0.4s, v0.4s, v1.4h
; CHECK-NODOT-NEXT: add v0.2s, v2.2s, v0.2s
; CHECK-NODOT-NEXT: ret
@@ -908,10 +908,10 @@ define <2 x i32> @sdot_no_bin_op_narrow(<2 x i32> %acc, <8 x i8> %a){
; CHECK-NODOT-NEXT: sshll v2.4s, v1.4h, #0
; CHECK-NODOT-NEXT: saddw v0.4s, v0.4s, v1.4h
; CHECK-NODOT-NEXT: sshll2 v3.4s, v1.8h, #0
-; CHECK-NODOT-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-NODOT-NEXT: ext v2.16b, v2.16b, v2.16b, #8
+; CHECK-NODOT-NEXT: mov d1, v1.d[1]
+; CHECK-NODOT-NEXT: mov d2, v2.d[1]
; CHECK-NODOT-NEXT: add v0.2s, v2.2s, v0.2s
-; CHECK-NODOT-NEXT: ext v2.16b, v3.16b, v3.16b, #8
+; CHECK-NODOT-NEXT: mov d2, v3.d[1]
; CHECK-NODOT-NEXT: saddw v0.4s, v0.4s, v1.4h
; CHECK-NODOT-NEXT: add v0.2s, v2.2s, v0.2s
; CHECK-NODOT-NEXT: ret
@@ -1036,7 +1036,7 @@ define <2 x i32> @not_udot_narrow(<2 x i32> %acc, <4 x i8> %u, <4 x i8> %s) {
; CHECK-COMMON-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-COMMON-NEXT: umull v3.4s, v2.4h, v1.4h
; CHECK-COMMON-NEXT: umlal v0.4s, v2.4h, v1.4h
-; CHECK-COMMON-NEXT: ext v1.16b, v3.16b, v3.16b, #8
+; CHECK-COMMON-NEXT: mov d1, v3.d[1]
; CHECK-COMMON-NEXT: add v0.2s, v1.2s, v0.2s
; CHECK-COMMON-NEXT: ret
%u.wide = zext <4 x i8> %u to <4 x i32>
@@ -1461,19 +1461,19 @@ define <2 x i32> @udot_v16i8tov2i32(<2 x i32> %acc, <16 x i8> %input) {
; CHECK-NODOT-NEXT: ushll v3.4s, v2.4h, #0
; CHECK-NODOT-NEXT: uaddw v0.4s, v0.4s, v2.4h
; CHECK-NODOT-NEXT: ushll2 v4.4s, v2.8h, #0
-; CHECK-NODOT-NEXT: ext v2.16b, v2.16b, v2.16b, #8
-; CHECK-NODOT-NEXT: ext v3.16b, v3.16b, v3.16b, #8
+; CHECK-NODOT-NEXT: mov d2, v2.d[1]
+; CHECK-NODOT-NEXT: mov d3, v3.d[1]
; CHECK-NODOT-NEXT: add v0.2s, v3.2s, v0.2s
-; CHECK-NODOT-NEXT: ext v3.16b, v4.16b, v4.16b, #8
+; CHECK-NODOT-NEXT: mov d3, v4.d[1]
; CHECK-NODOT-NEXT: uaddw v0.4s, v0.4s, v2.4h
; CHECK-NODOT-NEXT: ushll v2.4s, v1.4h, #0
; CHECK-NODOT-NEXT: add v0.2s, v3.2s, v0.2s
-; CHECK-NODOT-NEXT: ext v2.16b, v2.16b, v2.16b, #8
+; CHECK-NODOT-NEXT: mov d2, v2.d[1]
; CHECK-NODOT-NEXT: ushll2 v3.4s, v1.8h, #0
; CHECK-NODOT-NEXT: uaddw v0.4s, v0.4s, v1.4h
-; CHECK-NODOT-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECK-NODOT-NEXT: mov d1, v1.d[1]
; CHECK-NODOT-NEXT: add v0.2s, v2.2s, v0.2s
-; CHECK-NODOT-NEXT: ext v2.16b, v3.16b, v3.16b, #8
+; CHECK-NODOT-NEXT: mov d2, v3.d[1]
; CHECK-NODOT-NEXT: uaddw v0.4s, v0.4s, v1.4h
; CHECK-NODOT-NEXT: add v0.2s, v2.2s, v0.2s
; CHECK-NODOT-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/neon-scalar-copy.ll b/llvm/test/CodeGen/AArch64/neon-scalar-copy.ll
index 4a45484d17a95..387f3c250a701 100644
--- a/llvm/test/CodeGen/AArch64/neon-scalar-copy.ll
+++ b/llvm/test/CodeGen/AArch64/neon-scalar-copy.ll
@@ -1,142 +1,133 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -asm-verbose=false < %s | FileCheck %s
define float @test_dup_sv2S(<2 x float> %v) #0 {
- ; CHECK-LABEL: test_dup_sv2S:
- ; CHECK-NEXT: mov s{{[0-9]+}}, {{v[0-9]+}}.s[1]
- ; CHECK-NEXT: ret
+; CHECK-LABEL: test_dup_sv2S:
+; CHECK: mov s0, v0.s[1]
+; CHECK-NEXT: ret
%tmp1 = extractelement <2 x float> %v, i32 1
ret float %tmp1
}
define float @test_dup_sv2S_0(<2 x float> %v) #0 {
- ; CHECK-LABEL: test_dup_sv2S_0:
- ; CHECK-NOT: dup {{[vsd][0-9]+}}
- ; CHECK-NOT: ins {{[vsd][0-9]+}}
- ; CHECK-NEXT: ret
+; CHECK-LABEL: test_dup_sv2S_0:
+; CHECK: ret
%tmp1 = extractelement <2 x float> %v, i32 0
ret float %tmp1
}
define float @test_dup_sv4S(<4 x float> %v) #0 {
- ; CHECK-LABEL: test_dup_sv4S:
- ; CHECK-NEXT: mov s{{[0-9]+}}, {{v[0-9]+}}.s[1]
- ; CHECK-NEXT: ret
+; CHECK-LABEL: test_dup_sv4S:
+; CHECK: mov s0, v0.s[1]
+; CHECK-NEXT: ret
%tmp1 = extractelement <4 x float> %v, i32 1
ret float %tmp1
}
define float @test_dup_sv4S_0(<4 x float> %v) #0 {
- ; CHECK-LABEL: test_dup_sv4S_0:
- ; CHECK-NOT: dup {{[vsd][0-9]+}}
- ; CHECK-NOT: ins {{[vsd][0-9]+}}
- ; CHECK-NEXT: ret
+; CHECK-LABEL: test_dup_sv4S_0:
+; CHECK: ret
%tmp1 = extractelement <4 x float> %v, i32 0
ret float %tmp1
}
define double @test_dup_dvD(<1 x double> %v) #0 {
- ; CHECK-LABEL: test_dup_dvD:
- ; CHECK-NOT: dup {{[vsd][0-9]+}}
- ; CHECK-NOT: ins {{[vsd][0-9]+}}
- ; CHECK-NEXT: ret
+; CHECK-LABEL: test_dup_dvD:
+; CHECK: ret
%tmp1 = extractelement <1 x double> %v, i32 0
ret double %tmp1
}
define double @test_dup_dv2D(<2 x double> %v) #0 {
- ; CHECK-LABEL: test_dup_dv2D:
- ; CHECK-NEXT: mov d{{[0-9]+}}, {{v[0-9]+}}.d[1]
- ; CHECK-NEXT: ret
+; CHECK-LABEL: test_dup_dv2D:
+; CHECK: mov d0, v0.d[1]
+; CHECK-NEXT: ret
%tmp1 = extractelement <2 x double> %v, i32 1
ret double %tmp1
}
define double @test_dup_dv2D_0(<2 x double> %v) #0 {
- ; CHECK-LABEL: test_dup_dv2D_0:
- ; CHECK-NOT: dup {{[vsd][0-9]+}}
- ; CHECK-NOT: ins {{[vsd][0-9]+}}
- ; CHECK-NEXT: ret
+; CHECK-LABEL: test_dup_dv2D_0:
+; CHECK: ret
%tmp1 = extractelement <2 x double> %v, i32 0
ret double %tmp1
}
define half @test_dup_hv8H(<8 x half> %v) #0 {
- ; CHECK-LABEL: test_dup_hv8H:
- ; CHECK-NEXT: mov h{{[0-9]+}}, {{v[0-9]+}}.h[1]
- ; CHECK-NEXT: ret
+; CHECK-LABEL: test_dup_hv8H:
+; CHECK: mov h0, v0.h[1]
+; CHECK-NEXT: ret
%tmp1 = extractelement <8 x half> %v, i32 1
ret half %tmp1
}
define half @test_dup_hv8H_0(<8 x half> %v) #0 {
- ; CHECK-LABEL: test_dup_hv8H_0:
- ; CHECK-NOT: dup {{[vsdh][0-9]+}}
- ; CHECK-NOT: ins {{[vsdh][0-9]+}}
- ; CHECK-NEXT: ret
+; CHECK-LABEL: test_dup_hv8H_0:
+; CHECK: ret
%tmp1 = extractelement <8 x half> %v, i32 0
ret half %tmp1
}
define <1 x i8> @test_vector_dup_bv16B(<16 x i8> %v1) #0 {
- ; CHECK-LABEL: test_vector_dup_bv16B:
- ; CHECK-NEXT: dup v0.8b, v0.b[14]
- ; CHECK-NEXT: ret
- %shuffle.i = shufflevector <16 x i8> %v1, <16 x i8> undef, <1 x i32> <i32 14>
+; CHECK-LABEL: test_vector_dup_bv16B:
+; CHECK: dup v0.8b, v0.b[14]
+; CHECK-NEXT: ret
+ %shuffle.i = shufflevector <16 x i8> %v1, <16 x i8> undef, <1 x i32> <i32 14>
ret <1 x i8> %shuffle.i
}
define <1 x i8> @test_vector_dup_bv8B(<8 x i8> %v1) #0 {
- ; CHECK-LABEL: test_vector_dup_bv8B:
- ; CHECK-NEXT: dup v0.8b, v0.b[7]
- ; CHECK-NEXT: ret
- %shuffle.i = shufflevector <8 x i8> %v1, <8 x i8> undef, <1 x i32> <i32 7>
+; CHECK-LABEL: test_vector_dup_bv8B:
+; CHECK: dup v0.8b, v0.b[7]
+; CHECK-NEXT: ret
+ %shuffle.i = shufflevector <8 x i8> %v1, <8 x i8> undef, <1 x i32> <i32 7>
ret <1 x i8> %shuffle.i
}
define <1 x i16> @test_vector_dup_hv8H(<8 x i16> %v1) #0 {
- ; CHECK-LABEL: test_vector_dup_hv8H:
- ; CHECK-NEXT: dup v0.4h, v0.h[7]
- ; CHECK-NEXT: ret
- %shuffle.i = shufflevector <8 x i16> %v1, <8 x i16> undef, <1 x i32> <i32 7>
+; CHECK-LABEL: test_vector_dup_hv8H:
+; CHECK: dup v0.4h, v0.h[7]
+; CHECK-NEXT: ret
+ %shuffle.i = shufflevector <8 x i16> %v1, <8 x i16> undef, <1 x i32> <i32 7>
ret <1 x i16> %shuffle.i
}
define <1 x i16> @test_vector_dup_hv4H(<4 x i16> %v1) #0 {
- ; CHECK-LABEL: test_vector_dup_hv4H:
- ; CHECK-NEXT: dup v0.4h, v0.h[3]
- ; CHECK-NEXT: ret
- %shuffle.i = shufflevector <4 x i16> %v1, <4 x i16> undef, <1 x i32> <i32 3>
+; CHECK-LABEL: test_vector_dup_hv4H:
+; CHECK: dup v0.4h, v0.h[3]
+; CHECK-NEXT: ret
+ %shuffle.i = shufflevector <4 x i16> %v1, <4 x i16> undef, <1 x i32> <i32 3>
ret <1 x i16> %shuffle.i
}
define <1 x i32> @test_vector_dup_sv4S(<4 x i32> %v1) #0 {
- ; CHECK-LABEL: test_vector_dup_sv4S:
- ; CHECK-NEXT: dup v0.2s, v0.s[3]
- ; CHECK-NEXT: ret
- %shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <1 x i32> <i32 3>
+; CHECK-LABEL: test_vector_dup_sv4S:
+; CHECK: dup v0.2s, v0.s[3]
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <1 x i32> <i32 3>
ret <1 x i32> %shuffle
}
define <1 x i32> @test_vector_dup_sv2S(<2 x i32> %v1) #0 {
- ; CHECK-LABEL: test_vector_dup_sv2S:
- ; CHECK-NEXT: dup v0.2s, v0.s[1]
- ; CHECK-NEXT: ret
- %shuffle = shufflevector <2 x i32> %v1, <2 x i32> undef, <1 x i32> <i32 1>
+; CHECK-LABEL: test_vector_dup_sv2S:
+; CHECK: dup v0.2s, v0.s[1]
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <2 x i32> %v1, <2 x i32> undef, <1 x i32> <i32 1>
ret <1 x i32> %shuffle
}
define <1 x i64> @test_vector_dup_dv2D(<2 x i64> %v1) #0 {
- ; CHECK-LABEL: test_vector_dup_dv2D:
- ; CHECK-NEXT: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #8
- ; CHECK-NEXT: ret
- %shuffle.i = shufflevector <2 x i64> %v1, <2 x i64> undef, <1 x i32> <i32 1>
+; CHECK-LABEL: test_vector_dup_dv2D:
+; CHECK: mov d0, v0.d[1]
+; CHECK-NEXT: ret
+ %shuffle.i = shufflevector <2 x i64> %v1, <2 x i64> undef, <1 x i32> <i32 1>
ret <1 x i64> %shuffle.i
}
define <1 x i64> @test_vector_copy_dup_dv2D(<1 x i64> %a, <2 x i64> %c) #0 {
- ; CHECK-LABEL: test_vector_copy_dup_dv2D:
- ; CHECK-NEXT: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #8
- ; CHECK-NEXT: ret
+; CHECK-LABEL: test_vector_copy_dup_dv2D:
+; CHECK: mov d0, v1.d[1]
+; CHECK-NEXT: ret
%vget_lane = extractelement <2 x i64> %c, i32 1
%vset_lane = insertelement <1 x i64> undef, i64 %vget_lane, i32 0
ret <1 x i64> %vset_lane
@@ -146,7 +137,7 @@ define <1 x i64> @test_vector_copy_dup_dv2D(<1 x i64> %a, <2 x i64> %c) #0 {
; as long as we don't crash (since it could be dynamically unreachable).
define i32 @test_out_of_range_extract(<4 x i32> %vec) {
; CHECK-LABEL: test_out_of_range_extract:
-; CHECK: ret
+; CHECK: ret
%elt = extractelement <4 x i32> %vec, i32 4
ret i32 %elt
}
@@ -155,7 +146,7 @@ define i32 @test_out_of_range_extract(<4 x i32> %vec) {
; as long as we don't crash (since it could be dynamically unreachable).
define void @test_out_of_range_insert(<4 x i32> %vec, i32 %elt) {
; CHECK-LABEL: test_out_of_range_insert:
-; CHECK: ret
+; CHECK: ret
insertelement <4 x i32> %vec, i32 %elt, i32 4
ret void
}
diff --git a/llvm/test/CodeGen/AArch64/nontemporal-load.ll b/llvm/test/CodeGen/AArch64/nontemporal-load.ll
index 62b3e5651423f..662a95e4477b7 100644
--- a/llvm/test/CodeGen/AArch64/nontemporal-load.ll
+++ b/llvm/test/CodeGen/AArch64/nontemporal-load.ll
@@ -543,12 +543,10 @@ define <5 x double> @test_ldnp_v5f64(ptr %A) {
; CHECK-LE: ; %bb.0:
; CHECK-LE-NEXT: ldnp q0, q2, [x0]
; CHECK-LE-NEXT: ldr d4, [x0, #32]
-; CHECK-LE-NEXT: ext.16b v1, v0, v0, #8
-; CHECK-LE-NEXT: ext.16b v3, v2, v2, #8
+; CHECK-LE-NEXT: mov d1, v0[1]
+; CHECK-LE-NEXT: mov d3, v2[1]
; CHECK-LE-NEXT: ; kill: def $d0 killed $d0 killed $q0
; CHECK-LE-NEXT: ; kill: def $d2 killed $d2 killed $q2
-; CHECK-LE-NEXT: ; kill: def $d1 killed $d1 killed $q1
-; CHECK-LE-NEXT: ; kill: def $d3 killed $d3 killed $q3
; CHECK-LE-NEXT: ret
;
; CHECK-BE-LABEL: test_ldnp_v5f64:
@@ -558,12 +556,10 @@ define <5 x double> @test_ldnp_v5f64(ptr %A) {
; CHECK-BE-NEXT: ldr d4, [x0, #32]
; CHECK-BE-NEXT: ld1 { v2.2d }, [x8]
; CHECK-BE-NEXT: // kill: def $d4 killed $d4 killed $q4
-; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: mov d1, v0.d[1]
; CHECK-BE-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-BE-NEXT: ext v3.16b, v2.16b, v2.16b, #8
-; CHECK-BE-NEXT: // kill: def $d1 killed $d1 killed $q1
+; CHECK-BE-NEXT: mov d3, v2.d[1]
; CHECK-BE-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-BE-NEXT: // kill: def $d3 killed $d3 killed $q3
; CHECK-BE-NEXT: ret
%lv = load<5 x double>, ptr %A, align 8, !nontemporal !0
ret <5 x double> %lv
diff --git a/llvm/test/CodeGen/AArch64/ptradd.ll b/llvm/test/CodeGen/AArch64/ptradd.ll
index fc364357436e2..7f7d79db65ed3 100644
--- a/llvm/test/CodeGen/AArch64/ptradd.ll
+++ b/llvm/test/CodeGen/AArch64/ptradd.ll
@@ -76,15 +76,14 @@ define <3 x ptr> @vector_gep_v3i32(<3 x ptr> %b, <3 x i32> %off) {
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-SD-NEXT: ext v4.16b, v3.16b, v3.16b, #8
+; CHECK-SD-NEXT: mov d4, v3.d[1]
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
; CHECK-SD-NEXT: saddw v2.2d, v2.2d, v4.2s
; CHECK-SD-NEXT: saddw v0.2d, v0.2d, v3.2s
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: vector_gep_v3i32:
@@ -250,9 +249,8 @@ define <3 x ptr> @vector_gep_v3i64_base(ptr %b, <3 x i64> %off) {
; CHECK-SD-NEXT: dup v1.2d, x0
; CHECK-SD-NEXT: add d2, d3, d2
; CHECK-SD-NEXT: add v0.2d, v1.2d, v0.2d
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: vector_gep_v3i64_base:
diff --git a/llvm/test/CodeGen/AArch64/reduce-and.ll b/llvm/test/CodeGen/AArch64/reduce-and.ll
index 8ca521327c2e3..ad82befff4654 100644
--- a/llvm/test/CodeGen/AArch64/reduce-and.ll
+++ b/llvm/test/CodeGen/AArch64/reduce-and.ll
@@ -294,7 +294,7 @@ define i8 @test_redand_v8i8(<8 x i8> %a) {
define i8 @test_redand_v16i8(<16 x i8> %a) {
; CHECK-LABEL: test_redand_v16i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: and x8, x8, x8, lsr #32
@@ -331,7 +331,7 @@ define i8 @test_redand_v32i8(<32 x i8> %a) {
; CHECK-LABEL: test_redand_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: and x8, x8, x8, lsr #32
@@ -392,7 +392,7 @@ define i16 @test_redand_v4i16(<4 x i16> %a) {
define i16 @test_redand_v8i16(<8 x i16> %a) {
; CHECK-LABEL: test_redand_v8i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: and x8, x8, x8, lsr #32
@@ -420,7 +420,7 @@ define i16 @test_redand_v16i16(<16 x i16> %a) {
; CHECK-LABEL: test_redand_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: and x8, x8, x8, lsr #32
@@ -467,7 +467,7 @@ define i32 @test_redand_v2i32(<2 x i32> %a) {
define i32 @test_redand_v4i32(<4 x i32> %a) {
; CHECK-LABEL: test_redand_v4i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: lsr x9, x8, #32
@@ -490,7 +490,7 @@ define i32 @test_redand_v8i32(<8 x i32> %a) {
; CHECK-LABEL: test_redand_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: lsr x9, x8, #32
@@ -513,7 +513,7 @@ define i32 @test_redand_v8i32(<8 x i32> %a) {
define i64 @test_redand_v2i64(<2 x i64> %a) {
; CHECK-LABEL: test_redand_v2i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ret
@@ -532,7 +532,7 @@ define i64 @test_redand_v4i64(<4 x i64> %a) {
; CHECK-LABEL: test_redand_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/reduce-or.ll b/llvm/test/CodeGen/AArch64/reduce-or.ll
index f5291f5debb40..a4d10bd934cff 100644
--- a/llvm/test/CodeGen/AArch64/reduce-or.ll
+++ b/llvm/test/CodeGen/AArch64/reduce-or.ll
@@ -295,7 +295,7 @@ define i8 @test_redor_v8i8(<8 x i8> %a) {
define i8 @test_redor_v16i8(<16 x i8> %a) {
; CHECK-LABEL: test_redor_v16i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: orr x8, x8, x8, lsr #32
@@ -332,7 +332,7 @@ define i8 @test_redor_v32i8(<32 x i8> %a) {
; CHECK-LABEL: test_redor_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: orr x8, x8, x8, lsr #32
@@ -393,7 +393,7 @@ define i16 @test_redor_v4i16(<4 x i16> %a) {
define i16 @test_redor_v8i16(<8 x i16> %a) {
; CHECK-LABEL: test_redor_v8i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: orr x8, x8, x8, lsr #32
@@ -421,7 +421,7 @@ define i16 @test_redor_v16i16(<16 x i16> %a) {
; CHECK-LABEL: test_redor_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: orr x8, x8, x8, lsr #32
@@ -468,7 +468,7 @@ define i32 @test_redor_v2i32(<2 x i32> %a) {
define i32 @test_redor_v4i32(<4 x i32> %a) {
; CHECK-LABEL: test_redor_v4i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: lsr x9, x8, #32
@@ -491,7 +491,7 @@ define i32 @test_redor_v8i32(<8 x i32> %a) {
; CHECK-LABEL: test_redor_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: lsr x9, x8, #32
@@ -514,7 +514,7 @@ define i32 @test_redor_v8i32(<8 x i32> %a) {
define i64 @test_redor_v2i64(<2 x i64> %a) {
; CHECK-LABEL: test_redor_v2i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ret
@@ -533,7 +533,7 @@ define i64 @test_redor_v4i64(<4 x i64> %a) {
; CHECK-LABEL: test_redor_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/reduce-xor.ll b/llvm/test/CodeGen/AArch64/reduce-xor.ll
index df8485b91468f..fdd419864cc9f 100644
--- a/llvm/test/CodeGen/AArch64/reduce-xor.ll
+++ b/llvm/test/CodeGen/AArch64/reduce-xor.ll
@@ -284,7 +284,7 @@ define i8 @test_redxor_v8i8(<8 x i8> %a) {
define i8 @test_redxor_v16i8(<16 x i8> %a) {
; CHECK-LABEL: test_redxor_v16i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: eor x8, x8, x8, lsr #32
@@ -321,7 +321,7 @@ define i8 @test_redxor_v32i8(<32 x i8> %a) {
; CHECK-LABEL: test_redxor_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: eor x8, x8, x8, lsr #32
@@ -382,7 +382,7 @@ define i16 @test_redxor_v4i16(<4 x i16> %a) {
define i16 @test_redxor_v8i16(<8 x i16> %a) {
; CHECK-LABEL: test_redxor_v8i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: eor x8, x8, x8, lsr #32
@@ -410,7 +410,7 @@ define i16 @test_redxor_v16i16(<16 x i16> %a) {
; CHECK-LABEL: test_redxor_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: eor x8, x8, x8, lsr #32
@@ -457,7 +457,7 @@ define i32 @test_redxor_v2i32(<2 x i32> %a) {
define i32 @test_redxor_v4i32(<4 x i32> %a) {
; CHECK-LABEL: test_redxor_v4i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: lsr x9, x8, #32
@@ -480,7 +480,7 @@ define i32 @test_redxor_v8i32(<8 x i32> %a) {
; CHECK-LABEL: test_redxor_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: lsr x9, x8, #32
@@ -503,7 +503,7 @@ define i32 @test_redxor_v8i32(<8 x i32> %a) {
define i64 @test_redxor_v2i64(<2 x i64> %a) {
; CHECK-LABEL: test_redxor_v2i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ret
@@ -522,7 +522,7 @@ define i64 @test_redxor_v4i64(<4 x i64> %a) {
; CHECK-LABEL: test_redxor_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/sext.ll b/llvm/test/CodeGen/AArch64/sext.ll
index e6af0256fe6e2..278731ad0663a 100644
--- a/llvm/test/CodeGen/AArch64/sext.ll
+++ b/llvm/test/CodeGen/AArch64/sext.ll
@@ -273,9 +273,8 @@ define <3 x i64> @sext_v3i8_v3i64(<3 x i8> %a) {
; CHECK-SD-NEXT: shl v0.2d, v0.2d, #56
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-SD-NEXT: sshr v0.2d, v0.2d, #56
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: sext_v3i8_v3i64:
@@ -324,9 +323,8 @@ define <3 x i64> @sext_v3i16_v3i64(<3 x i16> %a) {
; CHECK-SD-NEXT: sshll v0.2d, v2.2s, #0
; CHECK-SD-NEXT: sshll2 v2.2d, v2.4s, #0
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: sext_v3i16_v3i64:
@@ -350,9 +348,8 @@ define <3 x i64> @sext_v3i32_v3i64(<3 x i32> %a) {
; CHECK-SD-NEXT: sshll v3.2d, v0.2s, #0
; CHECK-SD-NEXT: sshll2 v2.2d, v0.4s, #0
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-SD-NEXT: mov d1, v3.d[1]
; CHECK-SD-NEXT: fmov d0, d3
-; CHECK-SD-NEXT: ext v1.16b, v3.16b, v3.16b, #8
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: sext_v3i32_v3i64:
@@ -435,9 +432,8 @@ define <3 x i64> @sext_v3i10_v3i64(<3 x i10> %a) {
; CHECK-SD-NEXT: shl v0.2d, v0.2d, #54
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-SD-NEXT: sshr v0.2d, v0.2d, #54
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: sext_v3i10_v3i64:
diff --git a/llvm/test/CodeGen/AArch64/st1-lane.ll b/llvm/test/CodeGen/AArch64/st1-lane.ll
index a210339a3968e..a212376afe000 100644
--- a/llvm/test/CodeGen/AArch64/st1-lane.ll
+++ b/llvm/test/CodeGen/AArch64/st1-lane.ll
@@ -108,21 +108,13 @@ define void @v8bf16(<8 x bfloat> %a, ptr %p1, ptr %p2) {
define ptr @post_v2i64(<2 x i64> %a, ptr %p1, ptr %p2) {
-; CHECK-SD-LABEL: post_v2i64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: str d0, [x0]
-; CHECK-SD-NEXT: str d1, [x1], #8
-; CHECK-SD-NEXT: mov x0, x1
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: post_v2i64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: str d0, [x0]
-; CHECK-GI-NEXT: str d1, [x1], #8
-; CHECK-GI-NEXT: mov x0, x1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: post_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov d1, v0.d[1]
+; CHECK-NEXT: str d0, [x0]
+; CHECK-NEXT: str d1, [x1], #8
+; CHECK-NEXT: mov x0, x1
+; CHECK-NEXT: ret
%s1 = shufflevector <2 x i64> %a, <2 x i64> poison, <1 x i32> <i32 0>
store <1 x i64> %s1, ptr %p1, align 8
%s2 = shufflevector <2 x i64> %a, <2 x i64> poison, <1 x i32> <i32 1>
@@ -132,21 +124,13 @@ define ptr @post_v2i64(<2 x i64> %a, ptr %p1, ptr %p2) {
}
define ptr @post_v4i32(<4 x i32> %a, ptr %p1, ptr %p2) {
-; CHECK-SD-LABEL: post_v4i32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: str d0, [x0]
-; CHECK-SD-NEXT: str d1, [x1], #8
-; CHECK-SD-NEXT: mov x0, x1
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: post_v4i32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: str d0, [x0]
-; CHECK-GI-NEXT: str d1, [x1], #8
-; CHECK-GI-NEXT: mov x0, x1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: post_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov d1, v0.d[1]
+; CHECK-NEXT: str d0, [x0]
+; CHECK-NEXT: str d1, [x1], #8
+; CHECK-NEXT: mov x0, x1
+; CHECK-NEXT: ret
%s1 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 0, i32 1>
store <2 x i32> %s1, ptr %p1, align 8
%s2 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 2, i32 3>
@@ -156,21 +140,13 @@ define ptr @post_v4i32(<4 x i32> %a, ptr %p1, ptr %p2) {
}
define ptr @post_v8i16(<8 x i16> %a, ptr %p1, ptr %p2) {
-; CHECK-SD-LABEL: post_v8i16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: str d0, [x0]
-; CHECK-SD-NEXT: str d1, [x1], #8
-; CHECK-SD-NEXT: mov x0, x1
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: post_v8i16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: str d0, [x0]
-; CHECK-GI-NEXT: str d1, [x1], #8
-; CHECK-GI-NEXT: mov x0, x1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: post_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov d1, v0.d[1]
+; CHECK-NEXT: str d0, [x0]
+; CHECK-NEXT: str d1, [x1], #8
+; CHECK-NEXT: mov x0, x1
+; CHECK-NEXT: ret
%s1 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
store <4 x i16> %s1, ptr %p1, align 8
%s2 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -180,21 +156,13 @@ define ptr @post_v8i16(<8 x i16> %a, ptr %p1, ptr %p2) {
}
define ptr @post_v16i8(<16 x i8> %a, ptr %p1, ptr %p2) {
-; CHECK-SD-LABEL: post_v16i8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: str d0, [x0]
-; CHECK-SD-NEXT: str d1, [x1], #8
-; CHECK-SD-NEXT: mov x0, x1
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: post_v16i8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: str d0, [x0]
-; CHECK-GI-NEXT: str d1, [x1], #8
-; CHECK-GI-NEXT: mov x0, x1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: post_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov d1, v0.d[1]
+; CHECK-NEXT: str d0, [x0]
+; CHECK-NEXT: str d1, [x1], #8
+; CHECK-NEXT: mov x0, x1
+; CHECK-NEXT: ret
%s1 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
store <8 x i8> %s1, ptr %p1, align 8
%s2 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -204,21 +172,13 @@ define ptr @post_v16i8(<16 x i8> %a, ptr %p1, ptr %p2) {
}
define ptr @post_v2f64(<2 x double> %a, ptr %p1, ptr %p2) {
-; CHECK-SD-LABEL: post_v2f64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: str d0, [x0]
-; CHECK-SD-NEXT: str d1, [x1], #8
-; CHECK-SD-NEXT: mov x0, x1
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: post_v2f64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: str d0, [x0]
-; CHECK-GI-NEXT: str d1, [x1], #8
-; CHECK-GI-NEXT: mov x0, x1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: post_v2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov d1, v0.d[1]
+; CHECK-NEXT: str d0, [x0]
+; CHECK-NEXT: str d1, [x1], #8
+; CHECK-NEXT: mov x0, x1
+; CHECK-NEXT: ret
%s1 = shufflevector <2 x double> %a, <2 x double> poison, <1 x i32> <i32 0>
store <1 x double> %s1, ptr %p1, align 8
%s2 = shufflevector <2 x double> %a, <2 x double> poison, <1 x i32> <i32 1>
@@ -228,21 +188,13 @@ define ptr @post_v2f64(<2 x double> %a, ptr %p1, ptr %p2) {
}
define ptr @post_v4f32(<4 x float> %a, ptr %p1, ptr %p2) {
-; CHECK-SD-LABEL: post_v4f32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: str d0, [x0]
-; CHECK-SD-NEXT: str d1, [x1], #8
-; CHECK-SD-NEXT: mov x0, x1
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: post_v4f32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: str d0, [x0]
-; CHECK-GI-NEXT: str d1, [x1], #8
-; CHECK-GI-NEXT: mov x0, x1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: post_v4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov d1, v0.d[1]
+; CHECK-NEXT: str d0, [x0]
+; CHECK-NEXT: str d1, [x1], #8
+; CHECK-NEXT: mov x0, x1
+; CHECK-NEXT: ret
%s1 = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 0, i32 1>
store <2 x float> %s1, ptr %p1, align 8
%s2 = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 2, i32 3>
@@ -252,21 +204,13 @@ define ptr @post_v4f32(<4 x float> %a, ptr %p1, ptr %p2) {
}
define ptr @post_v8f16(<8 x half> %a, ptr %p1, ptr %p2) {
-; CHECK-SD-LABEL: post_v8f16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: str d0, [x0]
-; CHECK-SD-NEXT: str d1, [x1], #8
-; CHECK-SD-NEXT: mov x0, x1
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: post_v8f16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: str d0, [x0]
-; CHECK-GI-NEXT: str d1, [x1], #8
-; CHECK-GI-NEXT: mov x0, x1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: post_v8f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov d1, v0.d[1]
+; CHECK-NEXT: str d0, [x0]
+; CHECK-NEXT: str d1, [x1], #8
+; CHECK-NEXT: mov x0, x1
+; CHECK-NEXT: ret
%s1 = shufflevector <8 x half> %a, <8 x half> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
store <4 x half> %s1, ptr %p1, align 8
%s2 = shufflevector <8 x half> %a, <8 x half> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -276,21 +220,13 @@ define ptr @post_v8f16(<8 x half> %a, ptr %p1, ptr %p2) {
}
define ptr @post_v8bf16(<8 x bfloat> %a, ptr %p1, ptr %p2) {
-; CHECK-SD-LABEL: post_v8bf16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: str d0, [x0]
-; CHECK-SD-NEXT: str d1, [x1], #8
-; CHECK-SD-NEXT: mov x0, x1
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: post_v8bf16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: str d0, [x0]
-; CHECK-GI-NEXT: str d1, [x1], #8
-; CHECK-GI-NEXT: mov x0, x1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: post_v8bf16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov d1, v0.d[1]
+; CHECK-NEXT: str d0, [x0]
+; CHECK-NEXT: str d1, [x1], #8
+; CHECK-NEXT: mov x0, x1
+; CHECK-NEXT: ret
%s1 = shufflevector <8 x bfloat> %a, <8 x bfloat> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
store <4 x bfloat> %s1, ptr %p1, align 8
%s2 = shufflevector <8 x bfloat> %a, <8 x bfloat> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll
index 6b082b1762cc8..da00e6003df12 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll
@@ -27,8 +27,7 @@ define <4 x i8> @extract_subvector_v8i8(<8 x i8> %op) vscale_range(2,0) #0 {
define <8 x i8> @extract_subvector_v16i8(<16 x i8> %op) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v16i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
%ret = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %op, i64 8)
ret <8 x i8> %ret
@@ -185,8 +184,7 @@ define <2 x i16> @extract_subvector_v4i16(<4 x i16> %op) vscale_range(2,0) #0 {
define <4 x i16> @extract_subvector_v8i16(<8 x i16> %op) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v8i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
%ret = call <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16> %op, i64 4)
ret <4 x i16> %ret
@@ -300,8 +298,7 @@ define <1 x i32> @extract_subvector_v2i32(<2 x i32> %op) vscale_range(2,0) #0 {
define <2 x i32> @extract_subvector_v4i32(<4 x i32> %op) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v4i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
%ret = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %op, i64 2)
ret <2 x i32> %ret
@@ -404,8 +401,7 @@ define void @extract_subvector_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 {
define <1 x i64> @extract_subvector_v2i64(<2 x i64> %op) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v2i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
%ret = call <1 x i64> @llvm.vector.extract.v1i64.v2i64(<2 x i64> %op, i64 1)
ret <1 x i64> %ret
@@ -531,8 +527,7 @@ define <2 x half> @extract_subvector_v4f16(<4 x half> %op) vscale_range(16,0) #0
define <4 x half> @extract_subvector_v8f16(<8 x half> %op) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v8f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
%ret = call <4 x half> @llvm.vector.extract.v4f16.v8f16(<8 x half> %op, i64 4)
ret <4 x half> %ret
@@ -646,8 +641,7 @@ define <1 x float> @extract_subvector_v2f32(<2 x float> %op) vscale_range(2,0) #
define <2 x float> @extract_subvector_v4f32(<4 x float> %op) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v4f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
%ret = call <2 x float> @llvm.vector.extract.v2f32.v4f32(<4 x float> %op, i64 2)
ret <2 x float> %ret
@@ -750,8 +744,7 @@ define void @extract_subvector_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 {
define <1 x double> @extract_subvector_v2f64(<2 x double> %op) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v2f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: ret
%ret = call <1 x double> @llvm.vector.extract.v1f64.v2f64(<2 x double> %op, i64 1)
ret <1 x double> %ret
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
index 1690c3c5a75f7..e59b508fb1f13 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
@@ -253,7 +253,7 @@ define void @fcvtzu_v8f16_v8i64(ptr %a, ptr %b) #0 {
; VBITS_GE_256-NEXT: ldr q0, [x0]
; VBITS_GE_256-NEXT: ptrue p0.d, vl4
; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: uunpklo z0.s, z0.h
; VBITS_GE_256-NEXT: uunpklo z1.s, z1.h
; VBITS_GE_256-NEXT: uunpklo z0.d, z0.s
@@ -1140,7 +1140,7 @@ define void @fcvtzs_v8f16_v8i64(ptr %a, ptr %b) #0 {
; VBITS_GE_256-NEXT: ldr q0, [x0]
; VBITS_GE_256-NEXT: ptrue p0.d, vl4
; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: uunpklo z0.s, z0.h
; VBITS_GE_256-NEXT: uunpklo z1.s, z1.h
; VBITS_GE_256-NEXT: uunpklo z0.d, z0.s
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
index d2fa65599b973..83d29b08a67c3 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
@@ -157,7 +157,7 @@ define void @sext_v16i8_v16i32(<16 x i8> %a, ptr %out) #0 {
; VBITS_GE_256-LABEL: sext_v16i8_v16i32:
; VBITS_GE_256: // %bb.0:
; VBITS_GE_256-NEXT: // kill: def $q0 killed $q0 def $z0
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: ptrue p0.s, vl8
; VBITS_GE_256-NEXT: mov x8, #8 // =0x8
; VBITS_GE_256-NEXT: sunpklo z0.h, z0.b
@@ -245,7 +245,7 @@ define void @sext_v8i8_v8i64(<8 x i8> %a, ptr %out) #0 {
; VBITS_GE_256-NEXT: sshll v0.8h, v0.8b, #0
; VBITS_GE_256-NEXT: ptrue p0.d, vl4
; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: sunpklo z0.s, z0.h
; VBITS_GE_256-NEXT: sunpklo z1.s, z1.h
; VBITS_GE_256-NEXT: sunpklo z0.d, z0.s
@@ -407,7 +407,7 @@ define void @sext_v8i16_v8i64(<8 x i16> %a, ptr %out) #0 {
; VBITS_GE_256-LABEL: sext_v8i16_v8i64:
; VBITS_GE_256: // %bb.0:
; VBITS_GE_256-NEXT: // kill: def $q0 killed $q0 def $z0
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: ptrue p0.d, vl4
; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
; VBITS_GE_256-NEXT: sunpklo z0.s, z0.h
@@ -656,7 +656,7 @@ define void @zext_v16i8_v16i32(<16 x i8> %a, ptr %out) #0 {
; VBITS_GE_256-LABEL: zext_v16i8_v16i32:
; VBITS_GE_256: // %bb.0:
; VBITS_GE_256-NEXT: // kill: def $q0 killed $q0 def $z0
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: ptrue p0.s, vl8
; VBITS_GE_256-NEXT: mov x8, #8 // =0x8
; VBITS_GE_256-NEXT: uunpklo z0.h, z0.b
@@ -744,7 +744,7 @@ define void @zext_v8i8_v8i64(<8 x i8> %a, ptr %out) #0 {
; VBITS_GE_256-NEXT: ushll v0.8h, v0.8b, #0
; VBITS_GE_256-NEXT: ptrue p0.d, vl4
; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: uunpklo z0.s, z0.h
; VBITS_GE_256-NEXT: uunpklo z1.s, z1.h
; VBITS_GE_256-NEXT: uunpklo z0.d, z0.s
@@ -906,7 +906,7 @@ define void @zext_v8i16_v8i64(<8 x i16> %a, ptr %out) #0 {
; VBITS_GE_256-LABEL: zext_v8i16_v8i64:
; VBITS_GE_256: // %bb.0:
; VBITS_GE_256-NEXT: // kill: def $q0 killed $q0 def $z0
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: ptrue p0.d, vl4
; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
; VBITS_GE_256-NEXT: uunpklo z0.s, z0.h
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll
index 5753e5972f9c8..6f4f25890d46a 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll
@@ -255,7 +255,7 @@ define void @ucvtf_v8i16_v8f64(ptr %a, ptr %b) #0 {
; VBITS_GE_256-NEXT: ldr q0, [x0]
; VBITS_GE_256-NEXT: ptrue p0.d, vl4
; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: uunpklo z0.s, z0.h
; VBITS_GE_256-NEXT: uunpklo z1.s, z1.h
; VBITS_GE_256-NEXT: uunpklo z0.d, z0.s
@@ -1176,7 +1176,7 @@ define void @scvtf_v8i16_v8f64(ptr %a, ptr %b) #0 {
; VBITS_GE_256-NEXT: ldr q0, [x0]
; VBITS_GE_256-NEXT: ptrue p0.d, vl4
; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: sunpklo z0.s, z0.h
; VBITS_GE_256-NEXT: sunpklo z1.s, z1.h
; VBITS_GE_256-NEXT: sunpklo z0.d, z0.s
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
index 8789167e611e4..91d0a9ad37dc9 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
@@ -7673,7 +7673,7 @@ define void @masked_load_sext_v16i8i32(ptr %ap, ptr %bp, ptr %c) #0 {
; VBITS_GE_256-NEXT: .LBB14_18: // %cond.load57
; VBITS_GE_256-NEXT: ld1 { v0.b }[15], [x0]
; VBITS_GE_256-NEXT: .LBB14_19: // %else58
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: sunpklo z0.h, z0.b
; VBITS_GE_256-NEXT: mov x8, #8 // =0x8
; VBITS_GE_256-NEXT: ptrue p0.s, vl8
@@ -7834,7 +7834,7 @@ define void @masked_load_sext_v16i8i32(ptr %ap, ptr %bp, ptr %c) #0 {
; CHECK-EXPAND-NEXT: ld1b { z0.b }, p0/z, [x0]
; CHECK-EXPAND-NEXT: ptrue p0.s, vl8
; CHECK-EXPAND-NEXT: expand z0.b, p1, z0.b
-; CHECK-EXPAND-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-EXPAND-NEXT: mov d1, v0.d[1]
; CHECK-EXPAND-NEXT: sunpklo z0.h, z0.b
; CHECK-EXPAND-NEXT: sunpklo z1.h, z1.b
; CHECK-EXPAND-NEXT: sunpklo z0.s, z0.h
@@ -7889,7 +7889,7 @@ define void @masked_load_sext_v8i8i64(ptr %ap, ptr %bp, ptr %c) #0 {
; VBITS_GE_256-NEXT: sshll v0.8h, v0.8b, #0
; VBITS_GE_256-NEXT: ptrue p0.d, vl4
; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: sunpklo z0.s, z0.h
; VBITS_GE_256-NEXT: sunpklo z1.s, z1.h
; VBITS_GE_256-NEXT: sunpklo z0.d, z0.s
@@ -7984,7 +7984,7 @@ define void @masked_load_sext_v8i8i64(ptr %ap, ptr %bp, ptr %c) #0 {
; CHECK-EXPAND-NEXT: ptrue p0.d, vl4
; CHECK-EXPAND-NEXT: expand z0.b, p1, z0.b
; CHECK-EXPAND-NEXT: sshll v0.8h, v0.8b, #0
-; CHECK-EXPAND-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-EXPAND-NEXT: mov d1, v0.d[1]
; CHECK-EXPAND-NEXT: sunpklo z0.s, z0.h
; CHECK-EXPAND-NEXT: sunpklo z1.s, z1.h
; CHECK-EXPAND-NEXT: sunpklo z0.d, z0.s
@@ -8500,7 +8500,7 @@ define void @masked_load_sext_v8i16i64(ptr %ap, ptr %bp, ptr %c) #0 {
; VBITS_GE_256-NEXT: .LBB17_10: // %cond.load25
; VBITS_GE_256-NEXT: ld1 { v0.h }[7], [x0]
; VBITS_GE_256-NEXT: .LBB17_11: // %else26
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: sunpklo z0.s, z0.h
; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
; VBITS_GE_256-NEXT: ptrue p0.d, vl4
@@ -8595,7 +8595,7 @@ define void @masked_load_sext_v8i16i64(ptr %ap, ptr %bp, ptr %c) #0 {
; CHECK-EXPAND-NEXT: ld1h { z0.h }, p0/z, [x0]
; CHECK-EXPAND-NEXT: ptrue p0.d, vl4
; CHECK-EXPAND-NEXT: expand z0.h, p1, z0.h
-; CHECK-EXPAND-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-EXPAND-NEXT: mov d1, v0.d[1]
; CHECK-EXPAND-NEXT: sunpklo z0.s, z0.h
; CHECK-EXPAND-NEXT: sunpklo z1.s, z1.h
; CHECK-EXPAND-NEXT: sunpklo z0.d, z0.s
@@ -9879,7 +9879,7 @@ define void @masked_load_zext_v16i8i32(ptr %ap, ptr %bp, ptr %c) #0 {
; VBITS_GE_256-NEXT: .LBB20_18: // %cond.load57
; VBITS_GE_256-NEXT: ld1 { v0.b }[15], [x0]
; VBITS_GE_256-NEXT: .LBB20_19: // %else58
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: uunpklo z0.h, z0.b
; VBITS_GE_256-NEXT: mov x8, #8 // =0x8
; VBITS_GE_256-NEXT: ptrue p0.s, vl8
@@ -10040,7 +10040,7 @@ define void @masked_load_zext_v16i8i32(ptr %ap, ptr %bp, ptr %c) #0 {
; CHECK-EXPAND-NEXT: ld1b { z0.b }, p0/z, [x0]
; CHECK-EXPAND-NEXT: ptrue p0.s, vl8
; CHECK-EXPAND-NEXT: expand z0.b, p1, z0.b
-; CHECK-EXPAND-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-EXPAND-NEXT: mov d1, v0.d[1]
; CHECK-EXPAND-NEXT: uunpklo z0.h, z0.b
; CHECK-EXPAND-NEXT: uunpklo z1.h, z1.b
; CHECK-EXPAND-NEXT: uunpklo z0.s, z0.h
@@ -10095,7 +10095,7 @@ define void @masked_load_zext_v8i8i64(ptr %ap, ptr %bp, ptr %c) #0 {
; VBITS_GE_256-NEXT: ushll v0.8h, v0.8b, #0
; VBITS_GE_256-NEXT: ptrue p0.d, vl4
; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: uunpklo z0.s, z0.h
; VBITS_GE_256-NEXT: uunpklo z1.s, z1.h
; VBITS_GE_256-NEXT: uunpklo z0.d, z0.s
@@ -10190,7 +10190,7 @@ define void @masked_load_zext_v8i8i64(ptr %ap, ptr %bp, ptr %c) #0 {
; CHECK-EXPAND-NEXT: ptrue p0.d, vl4
; CHECK-EXPAND-NEXT: expand z0.b, p1, z0.b
; CHECK-EXPAND-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-EXPAND-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-EXPAND-NEXT: mov d1, v0.d[1]
; CHECK-EXPAND-NEXT: uunpklo z0.s, z0.h
; CHECK-EXPAND-NEXT: uunpklo z1.s, z1.h
; CHECK-EXPAND-NEXT: uunpklo z0.d, z0.s
@@ -10706,7 +10706,7 @@ define void @masked_load_zext_v8i16i64(ptr %ap, ptr %bp, ptr %c) #0 {
; VBITS_GE_256-NEXT: .LBB23_10: // %cond.load25
; VBITS_GE_256-NEXT: ld1 { v0.h }[7], [x0]
; VBITS_GE_256-NEXT: .LBB23_11: // %else26
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: uunpklo z0.s, z0.h
; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
; VBITS_GE_256-NEXT: ptrue p0.d, vl4
@@ -10801,7 +10801,7 @@ define void @masked_load_zext_v8i16i64(ptr %ap, ptr %bp, ptr %c) #0 {
; CHECK-EXPAND-NEXT: ld1h { z0.h }, p0/z, [x0]
; CHECK-EXPAND-NEXT: ptrue p0.d, vl4
; CHECK-EXPAND-NEXT: expand z0.h, p1, z0.h
-; CHECK-EXPAND-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-EXPAND-NEXT: mov d1, v0.d[1]
; CHECK-EXPAND-NEXT: uunpklo z0.s, z0.h
; CHECK-EXPAND-NEXT: uunpklo z1.s, z1.h
; CHECK-EXPAND-NEXT: uunpklo z0.d, z0.s
@@ -12077,7 +12077,7 @@ define void @masked_load_sext_v16i8i32_m32(ptr %ap, ptr %bp, ptr %c) #0 {
; VBITS_GE_256-NEXT: .LBB26_18: // %cond.load57
; VBITS_GE_256-NEXT: ld1 { v0.b }[15], [x0]
; VBITS_GE_256-NEXT: .LBB26_19: // %else58
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: sunpklo z0.h, z0.b
; VBITS_GE_256-NEXT: mov x8, #8 // =0x8
; VBITS_GE_256-NEXT: sunpklo z1.h, z1.b
@@ -12288,7 +12288,7 @@ define void @masked_load_sext_v16i8i32_m32(ptr %ap, ptr %bp, ptr %c) #0 {
; CHECK-EXPAND-NEXT: whilelo p1.b, xzr, x9
; CHECK-EXPAND-NEXT: ld1b { z0.b }, p1/z, [x0]
; CHECK-EXPAND-NEXT: expand z0.b, p2, z0.b
-; CHECK-EXPAND-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-EXPAND-NEXT: mov d1, v0.d[1]
; CHECK-EXPAND-NEXT: sunpklo z0.h, z0.b
; CHECK-EXPAND-NEXT: sunpklo z1.h, z1.b
; CHECK-EXPAND-NEXT: sunpklo z0.s, z0.h
@@ -12368,7 +12368,7 @@ define void @masked_load_sext_v8i8i64_m64(ptr %ap, ptr %bp, ptr %c) #0 {
; VBITS_GE_256-NEXT: .LBB27_11: // %else26
; VBITS_GE_256-NEXT: sshll v0.8h, v0.8b, #0
; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: sunpklo z0.s, z0.h
; VBITS_GE_256-NEXT: sunpklo z1.s, z1.h
; VBITS_GE_256-NEXT: sunpklo z0.d, z0.s
@@ -12494,7 +12494,7 @@ define void @masked_load_sext_v8i8i64_m64(ptr %ap, ptr %bp, ptr %c) #0 {
; CHECK-EXPAND-NEXT: ld1b { z0.b }, p1/z, [x0]
; CHECK-EXPAND-NEXT: expand z0.b, p2, z0.b
; CHECK-EXPAND-NEXT: sshll v0.8h, v0.8b, #0
-; CHECK-EXPAND-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-EXPAND-NEXT: mov d1, v0.d[1]
; CHECK-EXPAND-NEXT: sunpklo z0.s, z0.h
; CHECK-EXPAND-NEXT: sunpklo z1.s, z1.h
; CHECK-EXPAND-NEXT: sunpklo z0.d, z0.s
@@ -13023,7 +13023,7 @@ define void @masked_load_sext_v8i16i64_m64(ptr %ap, ptr %bp, ptr %c) #0 {
; VBITS_GE_256-NEXT: .LBB29_10: // %cond.load25
; VBITS_GE_256-NEXT: ld1 { v0.h }[7], [x0]
; VBITS_GE_256-NEXT: .LBB29_11: // %else26
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: sunpklo z0.s, z0.h
; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
; VBITS_GE_256-NEXT: sunpklo z1.s, z1.h
@@ -13147,7 +13147,7 @@ define void @masked_load_sext_v8i16i64_m64(ptr %ap, ptr %bp, ptr %c) #0 {
; CHECK-EXPAND-NEXT: whilelo p1.h, xzr, x9
; CHECK-EXPAND-NEXT: ld1h { z0.h }, p1/z, [x0]
; CHECK-EXPAND-NEXT: expand z0.h, p2, z0.h
-; CHECK-EXPAND-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-EXPAND-NEXT: mov d1, v0.d[1]
; CHECK-EXPAND-NEXT: sunpklo z0.s, z0.h
; CHECK-EXPAND-NEXT: sunpklo z1.s, z1.h
; CHECK-EXPAND-NEXT: sunpklo z0.d, z0.s
@@ -14441,7 +14441,7 @@ define void @masked_load_zext_v16i8i32_m32(ptr %ap, ptr %bp, ptr %c) #0 {
; VBITS_GE_256-NEXT: .LBB32_18: // %cond.load57
; VBITS_GE_256-NEXT: ld1 { v0.b }[15], [x0]
; VBITS_GE_256-NEXT: .LBB32_19: // %else58
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: uunpklo z0.h, z0.b
; VBITS_GE_256-NEXT: mov x8, #8 // =0x8
; VBITS_GE_256-NEXT: uunpklo z1.h, z1.b
@@ -14652,7 +14652,7 @@ define void @masked_load_zext_v16i8i32_m32(ptr %ap, ptr %bp, ptr %c) #0 {
; CHECK-EXPAND-NEXT: whilelo p1.b, xzr, x9
; CHECK-EXPAND-NEXT: ld1b { z0.b }, p1/z, [x0]
; CHECK-EXPAND-NEXT: expand z0.b, p2, z0.b
-; CHECK-EXPAND-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-EXPAND-NEXT: mov d1, v0.d[1]
; CHECK-EXPAND-NEXT: uunpklo z0.h, z0.b
; CHECK-EXPAND-NEXT: uunpklo z1.h, z1.b
; CHECK-EXPAND-NEXT: uunpklo z0.s, z0.h
@@ -14732,7 +14732,7 @@ define void @masked_load_zext_v8i8i64_m64(ptr %ap, ptr %bp, ptr %c) #0 {
; VBITS_GE_256-NEXT: .LBB33_11: // %else26
; VBITS_GE_256-NEXT: ushll v0.8h, v0.8b, #0
; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: uunpklo z0.s, z0.h
; VBITS_GE_256-NEXT: uunpklo z1.s, z1.h
; VBITS_GE_256-NEXT: uunpklo z0.d, z0.s
@@ -14858,7 +14858,7 @@ define void @masked_load_zext_v8i8i64_m64(ptr %ap, ptr %bp, ptr %c) #0 {
; CHECK-EXPAND-NEXT: ld1b { z0.b }, p1/z, [x0]
; CHECK-EXPAND-NEXT: expand z0.b, p2, z0.b
; CHECK-EXPAND-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-EXPAND-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-EXPAND-NEXT: mov d1, v0.d[1]
; CHECK-EXPAND-NEXT: uunpklo z0.s, z0.h
; CHECK-EXPAND-NEXT: uunpklo z1.s, z1.h
; CHECK-EXPAND-NEXT: uunpklo z0.d, z0.s
@@ -15387,7 +15387,7 @@ define void @masked_load_zext_v8i16i64_m64(ptr %ap, ptr %bp, ptr %c) #0 {
; VBITS_GE_256-NEXT: .LBB35_10: // %cond.load25
; VBITS_GE_256-NEXT: ld1 { v0.h }[7], [x0]
; VBITS_GE_256-NEXT: .LBB35_11: // %else26
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: uunpklo z0.s, z0.h
; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
; VBITS_GE_256-NEXT: uunpklo z1.s, z1.h
@@ -15511,7 +15511,7 @@ define void @masked_load_zext_v8i16i64_m64(ptr %ap, ptr %bp, ptr %c) #0 {
; CHECK-EXPAND-NEXT: whilelo p1.h, xzr, x9
; CHECK-EXPAND-NEXT: ld1h { z0.h }, p1/z, [x0]
; CHECK-EXPAND-NEXT: expand z0.h, p2, z0.h
-; CHECK-EXPAND-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-EXPAND-NEXT: mov d1, v0.d[1]
; CHECK-EXPAND-NEXT: uunpklo z0.s, z0.h
; CHECK-EXPAND-NEXT: uunpklo z1.s, z1.h
; CHECK-EXPAND-NEXT: uunpklo z0.d, z0.s
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
index d49e0498aa908..06039a4eb7af0 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
@@ -215,7 +215,7 @@ define void @masked_gather_v8i16(ptr %a, ptr %b) #0 {
; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
; VBITS_GE_256-NEXT: cmeq v0.8h, v0.8h, #0
; VBITS_GE_256-NEXT: sunpklo z1.s, z0.h
-; VBITS_GE_256-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d0, v0.d[1]
; VBITS_GE_256-NEXT: sunpklo z1.d, z1.s
; VBITS_GE_256-NEXT: sunpklo z0.s, z0.h
; VBITS_GE_256-NEXT: cmpne p1.d, p0/z, z1.d, #0
@@ -622,7 +622,7 @@ define void @masked_gather_v8f16(ptr %a, ptr %b) #0 {
; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
; VBITS_GE_256-NEXT: fcmeq v0.8h, v0.8h, #0.0
; VBITS_GE_256-NEXT: sunpklo z1.s, z0.h
-; VBITS_GE_256-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d0, v0.d[1]
; VBITS_GE_256-NEXT: sunpklo z1.d, z1.s
; VBITS_GE_256-NEXT: sunpklo z0.s, z0.h
; VBITS_GE_256-NEXT: cmpne p1.d, p0/z, z1.d, #0
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
index 2a3a8d00641ac..a898151a12ace 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
@@ -408,7 +408,7 @@ define void @masked_load_sext_v16i8i32(ptr %ap, ptr %bp, ptr %c) #0 {
; VBITS_GE_256-NEXT: cmpeq p1.b, p0/z, z0.b, #0
; VBITS_GE_256-NEXT: ptrue p0.s, vl8
; VBITS_GE_256-NEXT: ld1b { z0.b }, p1/z, [x0]
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: sunpklo z0.h, z0.b
; VBITS_GE_256-NEXT: sunpklo z1.h, z1.b
; VBITS_GE_256-NEXT: sunpklo z0.s, z0.h
@@ -443,7 +443,7 @@ define void @masked_load_sext_v8i8i64(ptr %ap, ptr %bp, ptr %c) #0 {
; VBITS_GE_256-NEXT: ptrue p0.d, vl4
; VBITS_GE_256-NEXT: ld1b { z0.b }, p1/z, [x0]
; VBITS_GE_256-NEXT: sshll v0.8h, v0.8b, #0
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: sunpklo z0.s, z0.h
; VBITS_GE_256-NEXT: sunpklo z1.s, z1.h
; VBITS_GE_256-NEXT: sunpklo z0.d, z0.s
@@ -510,7 +510,7 @@ define void @masked_load_sext_v8i16i64(ptr %ap, ptr %bp, ptr %c) #0 {
; VBITS_GE_256-NEXT: cmpeq p1.h, p0/z, z0.h, #0
; VBITS_GE_256-NEXT: ptrue p0.d, vl4
; VBITS_GE_256-NEXT: ld1h { z0.h }, p1/z, [x0]
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: sunpklo z0.s, z0.h
; VBITS_GE_256-NEXT: sunpklo z1.s, z1.h
; VBITS_GE_256-NEXT: sunpklo z0.d, z0.s
@@ -610,7 +610,7 @@ define void @masked_load_zext_v16i8i32(ptr %ap, ptr %bp, ptr %c) #0 {
; VBITS_GE_256-NEXT: cmpeq p1.b, p0/z, z0.b, #0
; VBITS_GE_256-NEXT: ptrue p0.s, vl8
; VBITS_GE_256-NEXT: ld1b { z0.b }, p1/z, [x0]
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: uunpklo z0.h, z0.b
; VBITS_GE_256-NEXT: uunpklo z1.h, z1.b
; VBITS_GE_256-NEXT: uunpklo z0.s, z0.h
@@ -645,7 +645,7 @@ define void @masked_load_zext_v8i8i64(ptr %ap, ptr %bp, ptr %c) #0 {
; VBITS_GE_256-NEXT: ptrue p0.d, vl4
; VBITS_GE_256-NEXT: ld1b { z0.b }, p1/z, [x0]
; VBITS_GE_256-NEXT: ushll v0.8h, v0.8b, #0
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: uunpklo z0.s, z0.h
; VBITS_GE_256-NEXT: uunpklo z1.s, z1.h
; VBITS_GE_256-NEXT: uunpklo z0.d, z0.s
@@ -712,7 +712,7 @@ define void @masked_load_zext_v8i16i64(ptr %ap, ptr %bp, ptr %c) #0 {
; VBITS_GE_256-NEXT: cmpeq p1.h, p0/z, z0.h, #0
; VBITS_GE_256-NEXT: ptrue p0.d, vl4
; VBITS_GE_256-NEXT: ld1h { z0.h }, p1/z, [x0]
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: uunpklo z0.s, z0.h
; VBITS_GE_256-NEXT: uunpklo z1.s, z1.h
; VBITS_GE_256-NEXT: uunpklo z0.d, z0.s
@@ -831,7 +831,7 @@ define void @masked_load_sext_v16i8i32_m32(ptr %ap, ptr %bp, ptr %c) #0 {
; VBITS_GE_256-NEXT: mov v1.d[1], v0.d[0]
; VBITS_GE_256-NEXT: cmpne p2.b, p1/z, z1.b, #0
; VBITS_GE_256-NEXT: ld1b { z0.b }, p2/z, [x0]
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: sunpklo z0.h, z0.b
; VBITS_GE_256-NEXT: sunpklo z1.h, z1.b
; VBITS_GE_256-NEXT: sunpklo z0.s, z0.h
@@ -877,7 +877,7 @@ define void @masked_load_sext_v8i8i64_m64(ptr %ap, ptr %bp, ptr %c) #0 {
; VBITS_GE_256-NEXT: cmpne p2.b, p1/z, z0.b, #0
; VBITS_GE_256-NEXT: ld1b { z0.b }, p2/z, [x0]
; VBITS_GE_256-NEXT: sshll v0.8h, v0.8b, #0
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: sunpklo z0.s, z0.h
; VBITS_GE_256-NEXT: sunpklo z1.s, z1.h
; VBITS_GE_256-NEXT: sunpklo z0.d, z0.s
@@ -965,7 +965,7 @@ define void @masked_load_sext_v8i16i64_m64(ptr %ap, ptr %bp, ptr %c) #0 {
; VBITS_GE_256-NEXT: uzp1 z0.h, z1.h, z1.h
; VBITS_GE_256-NEXT: cmpne p2.h, p1/z, z0.h, #0
; VBITS_GE_256-NEXT: ld1h { z0.h }, p2/z, [x0]
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: sunpklo z0.s, z0.h
; VBITS_GE_256-NEXT: sunpklo z1.s, z1.h
; VBITS_GE_256-NEXT: sunpklo z0.d, z0.s
@@ -1093,7 +1093,7 @@ define void @masked_load_zext_v16i8i32_m32(ptr %ap, ptr %bp, ptr %c) #0 {
; VBITS_GE_256-NEXT: mov v1.d[1], v0.d[0]
; VBITS_GE_256-NEXT: cmpne p2.b, p1/z, z1.b, #0
; VBITS_GE_256-NEXT: ld1b { z0.b }, p2/z, [x0]
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: uunpklo z0.h, z0.b
; VBITS_GE_256-NEXT: uunpklo z1.h, z1.b
; VBITS_GE_256-NEXT: uunpklo z0.s, z0.h
@@ -1139,7 +1139,7 @@ define void @masked_load_zext_v8i8i64_m64(ptr %ap, ptr %bp, ptr %c) #0 {
; VBITS_GE_256-NEXT: cmpne p2.b, p1/z, z0.b, #0
; VBITS_GE_256-NEXT: ld1b { z0.b }, p2/z, [x0]
; VBITS_GE_256-NEXT: ushll v0.8h, v0.8b, #0
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: uunpklo z0.s, z0.h
; VBITS_GE_256-NEXT: uunpklo z1.s, z1.h
; VBITS_GE_256-NEXT: uunpklo z0.d, z0.s
@@ -1227,7 +1227,7 @@ define void @masked_load_zext_v8i16i64_m64(ptr %ap, ptr %bp, ptr %c) #0 {
; VBITS_GE_256-NEXT: uzp1 z0.h, z1.h, z1.h
; VBITS_GE_256-NEXT: cmpne p2.h, p1/z, z0.h, #0
; VBITS_GE_256-NEXT: ld1h { z0.h }, p2/z, [x0]
-; VBITS_GE_256-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v0.d[1]
; VBITS_GE_256-NEXT: uunpklo z0.s, z0.h
; VBITS_GE_256-NEXT: uunpklo z1.s, z1.h
; VBITS_GE_256-NEXT: uunpklo z0.d, z0.s
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
index 48d9d587164cf..b551cdf2110f5 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
@@ -204,10 +204,10 @@ define void @masked_scatter_v8i16(ptr %a, ptr %b) #0 {
; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
; VBITS_GE_256-NEXT: cmeq v1.8h, v0.8h, #0
; VBITS_GE_256-NEXT: uunpklo z3.s, z0.h
-; VBITS_GE_256-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d0, v0.d[1]
; VBITS_GE_256-NEXT: ld1d { z4.d }, p0/z, [x1, x8, lsl #3]
; VBITS_GE_256-NEXT: sunpklo z2.s, z1.h
-; VBITS_GE_256-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v1.d[1]
; VBITS_GE_256-NEXT: uunpklo z3.d, z3.s
; VBITS_GE_256-NEXT: uunpklo z0.s, z0.h
; VBITS_GE_256-NEXT: sunpklo z2.d, z2.s
@@ -580,10 +580,10 @@ define void @masked_scatter_v8f16(ptr %a, ptr %b) #0 {
; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
; VBITS_GE_256-NEXT: fcmeq v1.8h, v0.8h, #0.0
; VBITS_GE_256-NEXT: uunpklo z3.s, z0.h
-; VBITS_GE_256-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; VBITS_GE_256-NEXT: mov d0, v0.d[1]
; VBITS_GE_256-NEXT: ld1d { z4.d }, p0/z, [x1, x8, lsl #3]
; VBITS_GE_256-NEXT: sunpklo z2.s, z1.h
-; VBITS_GE_256-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; VBITS_GE_256-NEXT: mov d1, v1.d[1]
; VBITS_GE_256-NEXT: uunpklo z3.d, z3.s
; VBITS_GE_256-NEXT: uunpklo z0.s, z0.h
; VBITS_GE_256-NEXT: sunpklo z2.d, z2.s
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll b/llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll
index 9372f2a82a795..88c0b34366809 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll
@@ -54,7 +54,7 @@ declare <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half>)
define <8 x i64> @llrint_v8i64_v8f16(<8 x half> %x) nounwind {
; CHECK-LABEL: llrint_v8i64_v8f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: frintx v0.4h, v0.4h
; CHECK-NEXT: frintx v1.4h, v1.4h
; CHECK-NEXT: mov h3, v0.h[2]
@@ -88,56 +88,56 @@ declare <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half>)
define <16 x i64> @llrint_v16i64_v16f16(<16 x half> %x) nounwind {
; CHECK-LABEL: llrint_v16i64_v16f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-NEXT: ext v3.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: frintx v0.4h, v0.4h
+; CHECK-NEXT: mov d2, v1.d[1]
; CHECK-NEXT: frintx v1.4h, v1.4h
+; CHECK-NEXT: mov d3, v0.d[1]
+; CHECK-NEXT: frintx v0.4h, v0.4h
; CHECK-NEXT: frintx v2.4h, v2.4h
+; CHECK-NEXT: mov h5, v1.h[1]
; CHECK-NEXT: frintx v3.4h, v3.4h
-; CHECK-NEXT: mov h5, v0.h[2]
; CHECK-NEXT: mov h4, v1.h[2]
-; CHECK-NEXT: mov h6, v0.h[1]
+; CHECK-NEXT: mov h6, v0.h[2]
; CHECK-NEXT: fcvtzs x8, h1
-; CHECK-NEXT: mov h16, v0.h[3]
+; CHECK-NEXT: mov h7, v0.h[3]
+; CHECK-NEXT: mov h16, v0.h[1]
; CHECK-NEXT: fcvtzs x9, h0
-; CHECK-NEXT: mov h7, v1.h[1]
; CHECK-NEXT: mov h1, v1.h[3]
; CHECK-NEXT: mov h0, v2.h[3]
; CHECK-NEXT: mov h17, v2.h[2]
; CHECK-NEXT: fcvtzs x12, h5
; CHECK-NEXT: mov h5, v3.h[2]
+; CHECK-NEXT: fcvtzs x10, h4
; CHECK-NEXT: fcvtzs x11, h2
; CHECK-NEXT: mov h18, v3.h[3]
; CHECK-NEXT: fcvtzs x14, h3
; CHECK-NEXT: mov h3, v3.h[1]
-; CHECK-NEXT: mov h19, v2.h[1]
-; CHECK-NEXT: fcvtzs x10, h4
-; CHECK-NEXT: fmov d4, x8
+; CHECK-NEXT: mov h2, v2.h[1]
; CHECK-NEXT: fcvtzs x13, h6
-; CHECK-NEXT: fcvtzs x15, h0
-; CHECK-NEXT: fcvtzs x8, h17
+; CHECK-NEXT: fmov d4, x8
+; CHECK-NEXT: fcvtzs x8, h0
; CHECK-NEXT: fmov d0, x9
-; CHECK-NEXT: fcvtzs x9, h5
-; CHECK-NEXT: fcvtzs x16, h7
-; CHECK-NEXT: fcvtzs x17, h16
+; CHECK-NEXT: fcvtzs x9, h17
+; CHECK-NEXT: fcvtzs x16, h5
+; CHECK-NEXT: fcvtzs x15, h16
+; CHECK-NEXT: fcvtzs x17, h7
; CHECK-NEXT: fmov d6, x11
; CHECK-NEXT: fcvtzs x11, h18
; CHECK-NEXT: fcvtzs x18, h3
-; CHECK-NEXT: fmov d2, x14
-; CHECK-NEXT: fcvtzs x14, h19
-; CHECK-NEXT: fcvtzs x0, h1
; CHECK-NEXT: fmov d5, x10
-; CHECK-NEXT: fmov d1, x12
-; CHECK-NEXT: fmov d7, x8
-; CHECK-NEXT: fmov d3, x9
-; CHECK-NEXT: mov v0.d[1], x13
-; CHECK-NEXT: mov v4.d[1], x16
-; CHECK-NEXT: mov v2.d[1], x18
+; CHECK-NEXT: fcvtzs x10, h2
+; CHECK-NEXT: fcvtzs x0, h1
+; CHECK-NEXT: fmov d2, x14
+; CHECK-NEXT: fmov d1, x13
+; CHECK-NEXT: fmov d7, x9
+; CHECK-NEXT: fmov d3, x16
+; CHECK-NEXT: mov v0.d[1], x15
+; CHECK-NEXT: mov v4.d[1], x12
; CHECK-NEXT: mov v1.d[1], x17
+; CHECK-NEXT: mov v2.d[1], x18
; CHECK-NEXT: mov v5.d[1], x0
-; CHECK-NEXT: mov v6.d[1], x14
; CHECK-NEXT: mov v3.d[1], x11
-; CHECK-NEXT: mov v7.d[1], x15
+; CHECK-NEXT: mov v6.d[1], x10
+; CHECK-NEXT: mov v7.d[1], x8
; CHECK-NEXT: ret
%a = call <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half> %x)
ret <16 x i64> %a
@@ -151,118 +151,118 @@ define <32 x i64> @llrint_v32i64_v32f16(<32 x half> %x) nounwind {
; CHECK-NEXT: sub x9, sp, #272
; CHECK-NEXT: mov x29, sp
; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
-; CHECK-NEXT: frintx v5.4h, v0.4h
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: ext v4.16b, v1.16b, v1.16b, #8
-; CHECK-NEXT: ext v17.16b, v2.16b, v2.16b, #8
-; CHECK-NEXT: frintx v1.4h, v1.4h
-; CHECK-NEXT: frintx v2.4h, v2.4h
-; CHECK-NEXT: ptrue p0.d, vl4
-; CHECK-NEXT: mov h6, v5.h[3]
+; CHECK-NEXT: mov d5, v0.d[1]
; CHECK-NEXT: frintx v0.4h, v0.4h
-; CHECK-NEXT: mov h7, v5.h[2]
-; CHECK-NEXT: mov h16, v5.h[1]
-; CHECK-NEXT: frintx v4.4h, v4.4h
-; CHECK-NEXT: fcvtzs x12, h5
-; CHECK-NEXT: ext v5.16b, v3.16b, v3.16b, #8
-; CHECK-NEXT: frintx v17.4h, v17.4h
-; CHECK-NEXT: frintx v3.4h, v3.4h
-; CHECK-NEXT: fcvtzs x9, h6
+; CHECK-NEXT: frintx v4.4h, v1.4h
+; CHECK-NEXT: mov d1, v1.d[1]
+; CHECK-NEXT: ptrue p0.d, vl4
+; CHECK-NEXT: frintx v5.4h, v5.4h
; CHECK-NEXT: mov h6, v0.h[3]
-; CHECK-NEXT: fcvtzs x10, h7
; CHECK-NEXT: mov h7, v0.h[2]
-; CHECK-NEXT: fcvtzs x11, h16
; CHECK-NEXT: mov h16, v0.h[1]
-; CHECK-NEXT: fcvtzs x13, h6
-; CHECK-NEXT: mov h6, v4.h[3]
+; CHECK-NEXT: fcvtzs x12, h0
+; CHECK-NEXT: frintx v1.4h, v1.4h
+; CHECK-NEXT: frintx v0.4h, v2.4h
+; CHECK-NEXT: mov d2, v2.d[1]
+; CHECK-NEXT: mov h17, v5.h[3]
+; CHECK-NEXT: fcvtzs x9, h6
+; CHECK-NEXT: mov h6, v5.h[2]
+; CHECK-NEXT: fcvtzs x10, h7
+; CHECK-NEXT: fcvtzs x11, h16
+; CHECK-NEXT: mov h7, v5.h[1]
+; CHECK-NEXT: mov h16, v4.h[3]
+; CHECK-NEXT: frintx v2.4h, v2.4h
+; CHECK-NEXT: fcvtzs x13, h17
; CHECK-NEXT: stp x10, x9, [sp, #48]
-; CHECK-NEXT: fcvtzs x9, h7
-; CHECK-NEXT: mov h7, v4.h[2]
-; CHECK-NEXT: fcvtzs x10, h16
-; CHECK-NEXT: mov h16, v4.h[1]
+; CHECK-NEXT: fcvtzs x9, h6
+; CHECK-NEXT: mov h6, v4.h[2]
+; CHECK-NEXT: fcvtzs x10, h7
+; CHECK-NEXT: mov h7, v4.h[1]
; CHECK-NEXT: stp x12, x11, [sp, #32]
-; CHECK-NEXT: fcvtzs x11, h0
-; CHECK-NEXT: frintx v0.4h, v5.4h
-; CHECK-NEXT: mov h5, v17.h[3]
-; CHECK-NEXT: fcvtzs x12, h6
-; CHECK-NEXT: mov h6, v17.h[2]
+; CHECK-NEXT: fcvtzs x11, h5
+; CHECK-NEXT: fcvtzs x12, h16
+; CHECK-NEXT: mov h5, v1.h[3]
; CHECK-NEXT: stp x9, x13, [sp, #16]
-; CHECK-NEXT: fcvtzs x13, h7
-; CHECK-NEXT: mov h7, v17.h[1]
-; CHECK-NEXT: fcvtzs x9, h16
+; CHECK-NEXT: fcvtzs x13, h6
+; CHECK-NEXT: mov h6, v1.h[2]
+; CHECK-NEXT: fcvtzs x9, h7
+; CHECK-NEXT: mov h7, v0.h[3]
; CHECK-NEXT: stp x11, x10, [sp]
; CHECK-NEXT: fcvtzs x10, h4
+; CHECK-NEXT: mov h4, v1.h[1]
; CHECK-NEXT: fcvtzs x11, h5
-; CHECK-NEXT: mov h4, v0.h[3]
; CHECK-NEXT: mov h5, v0.h[2]
-; CHECK-NEXT: stp x13, x12, [sp, #80]
+; CHECK-NEXT: stp x13, x12, [sp, #112]
; CHECK-NEXT: fcvtzs x12, h6
+; CHECK-NEXT: frintx v6.4h, v3.4h
; CHECK-NEXT: fcvtzs x13, h7
-; CHECK-NEXT: mov h6, v0.h[1]
-; CHECK-NEXT: stp x10, x9, [sp, #64]
-; CHECK-NEXT: fcvtzs x9, h17
-; CHECK-NEXT: mov h7, v1.h[3]
-; CHECK-NEXT: fcvtzs x10, h4
-; CHECK-NEXT: mov h4, v1.h[2]
-; CHECK-NEXT: stp x12, x11, [sp, #144]
+; CHECK-NEXT: mov d3, v3.d[1]
+; CHECK-NEXT: stp x10, x9, [sp, #96]
+; CHECK-NEXT: fcvtzs x9, h4
+; CHECK-NEXT: mov h4, v0.h[1]
+; CHECK-NEXT: fcvtzs x10, h1
+; CHECK-NEXT: mov h1, v2.h[3]
+; CHECK-NEXT: stp x12, x11, [sp, #80]
; CHECK-NEXT: fcvtzs x11, h5
-; CHECK-NEXT: mov h5, v1.h[1]
-; CHECK-NEXT: fcvtzs x12, h6
-; CHECK-NEXT: stp x9, x13, [sp, #128]
+; CHECK-NEXT: mov h5, v2.h[2]
+; CHECK-NEXT: fcvtzs x12, h4
+; CHECK-NEXT: mov h4, v2.h[1]
+; CHECK-NEXT: stp x10, x9, [sp, #64]
; CHECK-NEXT: fcvtzs x9, h0
-; CHECK-NEXT: fcvtzs x13, h7
-; CHECK-NEXT: mov h0, v2.h[3]
-; CHECK-NEXT: stp x11, x10, [sp, #208]
-; CHECK-NEXT: fcvtzs x10, h4
-; CHECK-NEXT: mov h4, v2.h[2]
+; CHECK-NEXT: fcvtzs x10, h1
+; CHECK-NEXT: mov h0, v6.h[3]
+; CHECK-NEXT: frintx v1.4h, v3.4h
+; CHECK-NEXT: stp x11, x13, [sp, #176]
; CHECK-NEXT: fcvtzs x11, h5
-; CHECK-NEXT: mov h5, v2.h[1]
-; CHECK-NEXT: stp x9, x12, [sp, #192]
-; CHECK-NEXT: fcvtzs x9, h1
-; CHECK-NEXT: fcvtzs x12, h0
-; CHECK-NEXT: mov h0, v3.h[3]
-; CHECK-NEXT: mov h1, v3.h[2]
-; CHECK-NEXT: stp x10, x13, [sp, #112]
-; CHECK-NEXT: fcvtzs x10, h4
-; CHECK-NEXT: mov h4, v3.h[1]
-; CHECK-NEXT: fcvtzs x13, h5
-; CHECK-NEXT: stp x9, x11, [sp, #96]
+; CHECK-NEXT: mov h3, v6.h[2]
+; CHECK-NEXT: fcvtzs x13, h4
+; CHECK-NEXT: mov h4, v6.h[1]
+; CHECK-NEXT: stp x9, x12, [sp, #160]
; CHECK-NEXT: fcvtzs x9, h2
-; CHECK-NEXT: fcvtzs x11, h0
-; CHECK-NEXT: stp x10, x12, [sp, #176]
-; CHECK-NEXT: fcvtzs x10, h1
-; CHECK-NEXT: fcvtzs x12, h4
-; CHECK-NEXT: stp x9, x13, [sp, #160]
-; CHECK-NEXT: fcvtzs x9, h3
-; CHECK-NEXT: stp x10, x11, [sp, #240]
-; CHECK-NEXT: add x10, sp, #64
-; CHECK-NEXT: stp x9, x12, [sp, #224]
+; CHECK-NEXT: fcvtzs x12, h0
+; CHECK-NEXT: mov h0, v1.h[3]
+; CHECK-NEXT: mov h2, v1.h[2]
+; CHECK-NEXT: stp x11, x10, [sp, #144]
+; CHECK-NEXT: fcvtzs x10, h3
+; CHECK-NEXT: mov h3, v1.h[1]
+; CHECK-NEXT: fcvtzs x11, h4
+; CHECK-NEXT: stp x9, x13, [sp, #128]
+; CHECK-NEXT: fcvtzs x9, h6
+; CHECK-NEXT: fcvtzs x13, h0
+; CHECK-NEXT: stp x10, x12, [sp, #240]
+; CHECK-NEXT: fcvtzs x10, h2
+; CHECK-NEXT: fcvtzs x12, h3
+; CHECK-NEXT: stp x9, x11, [sp, #224]
+; CHECK-NEXT: fcvtzs x9, h1
+; CHECK-NEXT: stp x10, x13, [sp, #208]
+; CHECK-NEXT: add x10, sp, #96
+; CHECK-NEXT: stp x9, x12, [sp, #192]
; CHECK-NEXT: add x9, sp, #32
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x9]
; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: ld1d { z2.d }, p0/z, [x10]
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x9]
-; CHECK-NEXT: add x9, sp, #224
-; CHECK-NEXT: add x10, sp, #128
+; CHECK-NEXT: add x9, sp, #192
+; CHECK-NEXT: add x10, sp, #64
; CHECK-NEXT: ld1d { z3.d }, p0/z, [x9]
-; CHECK-NEXT: add x9, sp, #160
+; CHECK-NEXT: add x9, sp, #224
; CHECK-NEXT: ld1d { z4.d }, p0/z, [x10]
-; CHECK-NEXT: add x10, sp, #96
+; CHECK-NEXT: add x10, sp, #128
; CHECK-NEXT: ld1d { z5.d }, p0/z, [x9]
-; CHECK-NEXT: add x9, sp, #192
+; CHECK-NEXT: add x9, sp, #160
; CHECK-NEXT: ld1d { z6.d }, p0/z, [x10]
-; CHECK-NEXT: mov x10, #24 // =0x18
+; CHECK-NEXT: mov x10, #28 // =0x1c
; CHECK-NEXT: ld1d { z7.d }, p0/z, [x9]
-; CHECK-NEXT: mov x9, #16 // =0x10
+; CHECK-NEXT: mov x9, #24 // =0x18
; CHECK-NEXT: st1d { z3.d }, p0, [x8, x10, lsl #3]
; CHECK-NEXT: st1d { z5.d }, p0, [x8, x9, lsl #3]
-; CHECK-NEXT: mov x9, #8 // =0x8
+; CHECK-NEXT: mov x9, #20 // =0x14
; CHECK-NEXT: st1d { z6.d }, p0, [x8, x9, lsl #3]
-; CHECK-NEXT: mov x9, #28 // =0x1c
+; CHECK-NEXT: mov x9, #16 // =0x10
; CHECK-NEXT: st1d { z7.d }, p0, [x8, x9, lsl #3]
-; CHECK-NEXT: mov x9, #20 // =0x14
-; CHECK-NEXT: st1d { z4.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #12 // =0xc
+; CHECK-NEXT: st1d { z4.d }, p0, [x8, x9, lsl #3]
+; CHECK-NEXT: mov x9, #8 // =0x8
; CHECK-NEXT: st1d { z2.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #4 // =0x4
; CHECK-NEXT: st1d { z1.d }, p0, [x8, x9, lsl #3]
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll b/llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll
index 2d7fe4a22ad0a..c9553388a5d4e 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll
@@ -112,7 +112,7 @@ define <8 x iXLen> @lrint_v8f16(<8 x half> %x) nounwind {
;
; CHECK-i64-LABEL: lrint_v8f16:
; CHECK-i64: // %bb.0:
-; CHECK-i64-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-i64-NEXT: mov d1, v0.d[1]
; CHECK-i64-NEXT: frintx v0.4h, v0.4h
; CHECK-i64-NEXT: frintx v1.4h, v1.4h
; CHECK-i64-NEXT: mov h3, v0.h[2]
@@ -198,56 +198,56 @@ define <16 x iXLen> @lrint_v16f16(<16 x half> %x) nounwind {
;
; CHECK-i64-LABEL: lrint_v16f16:
; CHECK-i64: // %bb.0:
-; CHECK-i64-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-i64-NEXT: ext v3.16b, v0.16b, v0.16b, #8
-; CHECK-i64-NEXT: frintx v0.4h, v0.4h
+; CHECK-i64-NEXT: mov d2, v1.d[1]
; CHECK-i64-NEXT: frintx v1.4h, v1.4h
+; CHECK-i64-NEXT: mov d3, v0.d[1]
+; CHECK-i64-NEXT: frintx v0.4h, v0.4h
; CHECK-i64-NEXT: frintx v2.4h, v2.4h
+; CHECK-i64-NEXT: mov h5, v1.h[1]
; CHECK-i64-NEXT: frintx v3.4h, v3.4h
-; CHECK-i64-NEXT: mov h5, v0.h[2]
; CHECK-i64-NEXT: mov h4, v1.h[2]
-; CHECK-i64-NEXT: mov h6, v0.h[1]
+; CHECK-i64-NEXT: mov h6, v0.h[2]
; CHECK-i64-NEXT: fcvtzs x8, h1
-; CHECK-i64-NEXT: mov h16, v0.h[3]
+; CHECK-i64-NEXT: mov h7, v0.h[3]
+; CHECK-i64-NEXT: mov h16, v0.h[1]
; CHECK-i64-NEXT: fcvtzs x9, h0
-; CHECK-i64-NEXT: mov h7, v1.h[1]
; CHECK-i64-NEXT: mov h1, v1.h[3]
; CHECK-i64-NEXT: mov h0, v2.h[3]
; CHECK-i64-NEXT: mov h17, v2.h[2]
; CHECK-i64-NEXT: fcvtzs x12, h5
; CHECK-i64-NEXT: mov h5, v3.h[2]
+; CHECK-i64-NEXT: fcvtzs x10, h4
; CHECK-i64-NEXT: fcvtzs x11, h2
; CHECK-i64-NEXT: mov h18, v3.h[3]
; CHECK-i64-NEXT: fcvtzs x14, h3
; CHECK-i64-NEXT: mov h3, v3.h[1]
-; CHECK-i64-NEXT: mov h19, v2.h[1]
-; CHECK-i64-NEXT: fcvtzs x10, h4
-; CHECK-i64-NEXT: fmov d4, x8
+; CHECK-i64-NEXT: mov h2, v2.h[1]
; CHECK-i64-NEXT: fcvtzs x13, h6
-; CHECK-i64-NEXT: fcvtzs x15, h0
-; CHECK-i64-NEXT: fcvtzs x8, h17
+; CHECK-i64-NEXT: fmov d4, x8
+; CHECK-i64-NEXT: fcvtzs x8, h0
; CHECK-i64-NEXT: fmov d0, x9
-; CHECK-i64-NEXT: fcvtzs x9, h5
-; CHECK-i64-NEXT: fcvtzs x16, h7
-; CHECK-i64-NEXT: fcvtzs x17, h16
+; CHECK-i64-NEXT: fcvtzs x9, h17
+; CHECK-i64-NEXT: fcvtzs x16, h5
+; CHECK-i64-NEXT: fcvtzs x15, h16
+; CHECK-i64-NEXT: fcvtzs x17, h7
; CHECK-i64-NEXT: fmov d6, x11
; CHECK-i64-NEXT: fcvtzs x11, h18
; CHECK-i64-NEXT: fcvtzs x18, h3
-; CHECK-i64-NEXT: fmov d2, x14
-; CHECK-i64-NEXT: fcvtzs x14, h19
-; CHECK-i64-NEXT: fcvtzs x0, h1
; CHECK-i64-NEXT: fmov d5, x10
-; CHECK-i64-NEXT: fmov d1, x12
-; CHECK-i64-NEXT: fmov d7, x8
-; CHECK-i64-NEXT: fmov d3, x9
-; CHECK-i64-NEXT: mov v0.d[1], x13
-; CHECK-i64-NEXT: mov v4.d[1], x16
-; CHECK-i64-NEXT: mov v2.d[1], x18
+; CHECK-i64-NEXT: fcvtzs x10, h2
+; CHECK-i64-NEXT: fcvtzs x0, h1
+; CHECK-i64-NEXT: fmov d2, x14
+; CHECK-i64-NEXT: fmov d1, x13
+; CHECK-i64-NEXT: fmov d7, x9
+; CHECK-i64-NEXT: fmov d3, x16
+; CHECK-i64-NEXT: mov v0.d[1], x15
+; CHECK-i64-NEXT: mov v4.d[1], x12
; CHECK-i64-NEXT: mov v1.d[1], x17
+; CHECK-i64-NEXT: mov v2.d[1], x18
; CHECK-i64-NEXT: mov v5.d[1], x0
-; CHECK-i64-NEXT: mov v6.d[1], x14
; CHECK-i64-NEXT: mov v3.d[1], x11
-; CHECK-i64-NEXT: mov v7.d[1], x15
+; CHECK-i64-NEXT: mov v6.d[1], x10
+; CHECK-i64-NEXT: mov v7.d[1], x8
; CHECK-i64-NEXT: ret
%a = call <16 x iXLen> @llvm.lrint.v16iXLen.v16f16(<16 x half> %x)
ret <16 x iXLen> %a
@@ -363,118 +363,118 @@ define <32 x iXLen> @lrint_v32f16(<32 x half> %x) nounwind {
; CHECK-i64-NEXT: sub x9, sp, #272
; CHECK-i64-NEXT: mov x29, sp
; CHECK-i64-NEXT: and sp, x9, #0xffffffffffffffe0
-; CHECK-i64-NEXT: frintx v5.4h, v0.4h
-; CHECK-i64-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-i64-NEXT: ext v4.16b, v1.16b, v1.16b, #8
-; CHECK-i64-NEXT: ext v17.16b, v2.16b, v2.16b, #8
-; CHECK-i64-NEXT: frintx v1.4h, v1.4h
-; CHECK-i64-NEXT: frintx v2.4h, v2.4h
-; CHECK-i64-NEXT: ptrue p0.d, vl4
-; CHECK-i64-NEXT: mov h6, v5.h[3]
+; CHECK-i64-NEXT: mov d5, v0.d[1]
; CHECK-i64-NEXT: frintx v0.4h, v0.4h
-; CHECK-i64-NEXT: mov h7, v5.h[2]
-; CHECK-i64-NEXT: mov h16, v5.h[1]
-; CHECK-i64-NEXT: frintx v4.4h, v4.4h
-; CHECK-i64-NEXT: fcvtzs x12, h5
-; CHECK-i64-NEXT: ext v5.16b, v3.16b, v3.16b, #8
-; CHECK-i64-NEXT: frintx v17.4h, v17.4h
-; CHECK-i64-NEXT: frintx v3.4h, v3.4h
-; CHECK-i64-NEXT: fcvtzs x9, h6
+; CHECK-i64-NEXT: frintx v4.4h, v1.4h
+; CHECK-i64-NEXT: mov d1, v1.d[1]
+; CHECK-i64-NEXT: ptrue p0.d, vl4
+; CHECK-i64-NEXT: frintx v5.4h, v5.4h
; CHECK-i64-NEXT: mov h6, v0.h[3]
-; CHECK-i64-NEXT: fcvtzs x10, h7
; CHECK-i64-NEXT: mov h7, v0.h[2]
-; CHECK-i64-NEXT: fcvtzs x11, h16
; CHECK-i64-NEXT: mov h16, v0.h[1]
-; CHECK-i64-NEXT: fcvtzs x13, h6
-; CHECK-i64-NEXT: mov h6, v4.h[3]
+; CHECK-i64-NEXT: fcvtzs x12, h0
+; CHECK-i64-NEXT: frintx v1.4h, v1.4h
+; CHECK-i64-NEXT: frintx v0.4h, v2.4h
+; CHECK-i64-NEXT: mov d2, v2.d[1]
+; CHECK-i64-NEXT: mov h17, v5.h[3]
+; CHECK-i64-NEXT: fcvtzs x9, h6
+; CHECK-i64-NEXT: mov h6, v5.h[2]
+; CHECK-i64-NEXT: fcvtzs x10, h7
+; CHECK-i64-NEXT: fcvtzs x11, h16
+; CHECK-i64-NEXT: mov h7, v5.h[1]
+; CHECK-i64-NEXT: mov h16, v4.h[3]
+; CHECK-i64-NEXT: frintx v2.4h, v2.4h
+; CHECK-i64-NEXT: fcvtzs x13, h17
; CHECK-i64-NEXT: stp x10, x9, [sp, #48]
-; CHECK-i64-NEXT: fcvtzs x9, h7
-; CHECK-i64-NEXT: mov h7, v4.h[2]
-; CHECK-i64-NEXT: fcvtzs x10, h16
-; CHECK-i64-NEXT: mov h16, v4.h[1]
+; CHECK-i64-NEXT: fcvtzs x9, h6
+; CHECK-i64-NEXT: mov h6, v4.h[2]
+; CHECK-i64-NEXT: fcvtzs x10, h7
+; CHECK-i64-NEXT: mov h7, v4.h[1]
; CHECK-i64-NEXT: stp x12, x11, [sp, #32]
-; CHECK-i64-NEXT: fcvtzs x11, h0
-; CHECK-i64-NEXT: frintx v0.4h, v5.4h
-; CHECK-i64-NEXT: mov h5, v17.h[3]
-; CHECK-i64-NEXT: fcvtzs x12, h6
-; CHECK-i64-NEXT: mov h6, v17.h[2]
+; CHECK-i64-NEXT: fcvtzs x11, h5
+; CHECK-i64-NEXT: fcvtzs x12, h16
+; CHECK-i64-NEXT: mov h5, v1.h[3]
; CHECK-i64-NEXT: stp x9, x13, [sp, #16]
-; CHECK-i64-NEXT: fcvtzs x13, h7
-; CHECK-i64-NEXT: mov h7, v17.h[1]
-; CHECK-i64-NEXT: fcvtzs x9, h16
+; CHECK-i64-NEXT: fcvtzs x13, h6
+; CHECK-i64-NEXT: mov h6, v1.h[2]
+; CHECK-i64-NEXT: fcvtzs x9, h7
+; CHECK-i64-NEXT: mov h7, v0.h[3]
; CHECK-i64-NEXT: stp x11, x10, [sp]
; CHECK-i64-NEXT: fcvtzs x10, h4
+; CHECK-i64-NEXT: mov h4, v1.h[1]
; CHECK-i64-NEXT: fcvtzs x11, h5
-; CHECK-i64-NEXT: mov h4, v0.h[3]
; CHECK-i64-NEXT: mov h5, v0.h[2]
-; CHECK-i64-NEXT: stp x13, x12, [sp, #80]
+; CHECK-i64-NEXT: stp x13, x12, [sp, #112]
; CHECK-i64-NEXT: fcvtzs x12, h6
+; CHECK-i64-NEXT: frintx v6.4h, v3.4h
; CHECK-i64-NEXT: fcvtzs x13, h7
-; CHECK-i64-NEXT: mov h6, v0.h[1]
-; CHECK-i64-NEXT: stp x10, x9, [sp, #64]
-; CHECK-i64-NEXT: fcvtzs x9, h17
-; CHECK-i64-NEXT: mov h7, v1.h[3]
-; CHECK-i64-NEXT: fcvtzs x10, h4
-; CHECK-i64-NEXT: mov h4, v1.h[2]
-; CHECK-i64-NEXT: stp x12, x11, [sp, #144]
+; CHECK-i64-NEXT: mov d3, v3.d[1]
+; CHECK-i64-NEXT: stp x10, x9, [sp, #96]
+; CHECK-i64-NEXT: fcvtzs x9, h4
+; CHECK-i64-NEXT: mov h4, v0.h[1]
+; CHECK-i64-NEXT: fcvtzs x10, h1
+; CHECK-i64-NEXT: mov h1, v2.h[3]
+; CHECK-i64-NEXT: stp x12, x11, [sp, #80]
; CHECK-i64-NEXT: fcvtzs x11, h5
-; CHECK-i64-NEXT: mov h5, v1.h[1]
-; CHECK-i64-NEXT: fcvtzs x12, h6
-; CHECK-i64-NEXT: stp x9, x13, [sp, #128]
+; CHECK-i64-NEXT: mov h5, v2.h[2]
+; CHECK-i64-NEXT: fcvtzs x12, h4
+; CHECK-i64-NEXT: mov h4, v2.h[1]
+; CHECK-i64-NEXT: stp x10, x9, [sp, #64]
; CHECK-i64-NEXT: fcvtzs x9, h0
-; CHECK-i64-NEXT: fcvtzs x13, h7
-; CHECK-i64-NEXT: mov h0, v2.h[3]
-; CHECK-i64-NEXT: stp x11, x10, [sp, #208]
-; CHECK-i64-NEXT: fcvtzs x10, h4
-; CHECK-i64-NEXT: mov h4, v2.h[2]
+; CHECK-i64-NEXT: fcvtzs x10, h1
+; CHECK-i64-NEXT: mov h0, v6.h[3]
+; CHECK-i64-NEXT: frintx v1.4h, v3.4h
+; CHECK-i64-NEXT: stp x11, x13, [sp, #176]
; CHECK-i64-NEXT: fcvtzs x11, h5
-; CHECK-i64-NEXT: mov h5, v2.h[1]
-; CHECK-i64-NEXT: stp x9, x12, [sp, #192]
-; CHECK-i64-NEXT: fcvtzs x9, h1
-; CHECK-i64-NEXT: fcvtzs x12, h0
-; CHECK-i64-NEXT: mov h0, v3.h[3]
-; CHECK-i64-NEXT: mov h1, v3.h[2]
-; CHECK-i64-NEXT: stp x10, x13, [sp, #112]
-; CHECK-i64-NEXT: fcvtzs x10, h4
-; CHECK-i64-NEXT: mov h4, v3.h[1]
-; CHECK-i64-NEXT: fcvtzs x13, h5
-; CHECK-i64-NEXT: stp x9, x11, [sp, #96]
+; CHECK-i64-NEXT: mov h3, v6.h[2]
+; CHECK-i64-NEXT: fcvtzs x13, h4
+; CHECK-i64-NEXT: mov h4, v6.h[1]
+; CHECK-i64-NEXT: stp x9, x12, [sp, #160]
; CHECK-i64-NEXT: fcvtzs x9, h2
-; CHECK-i64-NEXT: fcvtzs x11, h0
-; CHECK-i64-NEXT: stp x10, x12, [sp, #176]
-; CHECK-i64-NEXT: fcvtzs x10, h1
-; CHECK-i64-NEXT: fcvtzs x12, h4
-; CHECK-i64-NEXT: stp x9, x13, [sp, #160]
-; CHECK-i64-NEXT: fcvtzs x9, h3
-; CHECK-i64-NEXT: stp x10, x11, [sp, #240]
-; CHECK-i64-NEXT: add x10, sp, #64
-; CHECK-i64-NEXT: stp x9, x12, [sp, #224]
+; CHECK-i64-NEXT: fcvtzs x12, h0
+; CHECK-i64-NEXT: mov h0, v1.h[3]
+; CHECK-i64-NEXT: mov h2, v1.h[2]
+; CHECK-i64-NEXT: stp x11, x10, [sp, #144]
+; CHECK-i64-NEXT: fcvtzs x10, h3
+; CHECK-i64-NEXT: mov h3, v1.h[1]
+; CHECK-i64-NEXT: fcvtzs x11, h4
+; CHECK-i64-NEXT: stp x9, x13, [sp, #128]
+; CHECK-i64-NEXT: fcvtzs x9, h6
+; CHECK-i64-NEXT: fcvtzs x13, h0
+; CHECK-i64-NEXT: stp x10, x12, [sp, #240]
+; CHECK-i64-NEXT: fcvtzs x10, h2
+; CHECK-i64-NEXT: fcvtzs x12, h3
+; CHECK-i64-NEXT: stp x9, x11, [sp, #224]
+; CHECK-i64-NEXT: fcvtzs x9, h1
+; CHECK-i64-NEXT: stp x10, x13, [sp, #208]
+; CHECK-i64-NEXT: add x10, sp, #96
+; CHECK-i64-NEXT: stp x9, x12, [sp, #192]
; CHECK-i64-NEXT: add x9, sp, #32
; CHECK-i64-NEXT: ld1d { z0.d }, p0/z, [x9]
; CHECK-i64-NEXT: mov x9, sp
; CHECK-i64-NEXT: ld1d { z2.d }, p0/z, [x10]
; CHECK-i64-NEXT: ld1d { z1.d }, p0/z, [x9]
-; CHECK-i64-NEXT: add x9, sp, #224
-; CHECK-i64-NEXT: add x10, sp, #128
+; CHECK-i64-NEXT: add x9, sp, #192
+; CHECK-i64-NEXT: add x10, sp, #64
; CHECK-i64-NEXT: ld1d { z3.d }, p0/z, [x9]
-; CHECK-i64-NEXT: add x9, sp, #160
+; CHECK-i64-NEXT: add x9, sp, #224
; CHECK-i64-NEXT: ld1d { z4.d }, p0/z, [x10]
-; CHECK-i64-NEXT: add x10, sp, #96
+; CHECK-i64-NEXT: add x10, sp, #128
; CHECK-i64-NEXT: ld1d { z5.d }, p0/z, [x9]
-; CHECK-i64-NEXT: add x9, sp, #192
+; CHECK-i64-NEXT: add x9, sp, #160
; CHECK-i64-NEXT: ld1d { z6.d }, p0/z, [x10]
-; CHECK-i64-NEXT: mov x10, #24 // =0x18
+; CHECK-i64-NEXT: mov x10, #28 // =0x1c
; CHECK-i64-NEXT: ld1d { z7.d }, p0/z, [x9]
-; CHECK-i64-NEXT: mov x9, #16 // =0x10
+; CHECK-i64-NEXT: mov x9, #24 // =0x18
; CHECK-i64-NEXT: st1d { z3.d }, p0, [x8, x10, lsl #3]
; CHECK-i64-NEXT: st1d { z5.d }, p0, [x8, x9, lsl #3]
-; CHECK-i64-NEXT: mov x9, #8 // =0x8
+; CHECK-i64-NEXT: mov x9, #20 // =0x14
; CHECK-i64-NEXT: st1d { z6.d }, p0, [x8, x9, lsl #3]
-; CHECK-i64-NEXT: mov x9, #28 // =0x1c
+; CHECK-i64-NEXT: mov x9, #16 // =0x10
; CHECK-i64-NEXT: st1d { z7.d }, p0, [x8, x9, lsl #3]
-; CHECK-i64-NEXT: mov x9, #20 // =0x14
-; CHECK-i64-NEXT: st1d { z4.d }, p0, [x8, x9, lsl #3]
; CHECK-i64-NEXT: mov x9, #12 // =0xc
+; CHECK-i64-NEXT: st1d { z4.d }, p0, [x8, x9, lsl #3]
+; CHECK-i64-NEXT: mov x9, #8 // =0x8
; CHECK-i64-NEXT: st1d { z2.d }, p0, [x8, x9, lsl #3]
; CHECK-i64-NEXT: mov x9, #4 // =0x4
; CHECK-i64-NEXT: st1d { z1.d }, p0, [x8, x9, lsl #3]
diff --git a/llvm/test/CodeGen/AArch64/vec_uaddo.ll b/llvm/test/CodeGen/AArch64/vec_uaddo.ll
index 2f51208e49351..df78c2394a942 100644
--- a/llvm/test/CodeGen/AArch64/vec_uaddo.ll
+++ b/llvm/test/CodeGen/AArch64/vec_uaddo.ll
@@ -141,7 +141,7 @@ define <16 x i32> @uaddo_v16i8(<16 x i8> %a0, <16 x i8> %a1, ptr %p2) nounwind {
; CHECK-NEXT: add v4.16b, v0.16b, v1.16b
; CHECK-NEXT: cmhi v0.16b, v0.16b, v4.16b
; CHECK-NEXT: str q4, [x0]
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: zip1 v2.8b, v0.8b, v0.8b
; CHECK-NEXT: zip2 v0.8b, v0.8b, v0.8b
; CHECK-NEXT: zip1 v3.8b, v1.8b, v0.8b
diff --git a/llvm/test/CodeGen/AArch64/vec_umulo.ll b/llvm/test/CodeGen/AArch64/vec_umulo.ll
index 935f4272218af..0a3d94d8ba952 100644
--- a/llvm/test/CodeGen/AArch64/vec_umulo.ll
+++ b/llvm/test/CodeGen/AArch64/vec_umulo.ll
@@ -169,7 +169,7 @@ define <16 x i32> @umulo_v16i8(<16 x i8> %a0, <16 x i8> %a1, ptr %p2) nounwind {
; CHECK-NEXT: uzp2 v2.16b, v3.16b, v2.16b
; CHECK-NEXT: str q6, [x0]
; CHECK-NEXT: cmtst v2.16b, v2.16b, v2.16b
-; CHECK-NEXT: ext v3.16b, v2.16b, v2.16b, #8
+; CHECK-NEXT: mov d3, v2.d[1]
; CHECK-NEXT: zip1 v4.8b, v2.8b, v0.8b
; CHECK-NEXT: zip2 v2.8b, v2.8b, v0.8b
; CHECK-NEXT: zip1 v5.8b, v3.8b, v0.8b
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll b/llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
index ac54dd41b0962..7fbe6e55cc968 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
@@ -103,7 +103,7 @@ define i8 @test_v9i8(<9 x i8> %a) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0xffffffffffffff00
; CHECK-NEXT: orr v1.16b, v0.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT: mov d1, v1.d[1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: and x8, x8, x8, lsr #32
@@ -121,7 +121,7 @@ define i32 @test_v3i32(<3 x i32> %a) nounwind {
; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: mov w8, #-1 // =0xffffffff
; CHECK-NEXT: mov v1.s[3], w8
-; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT: mov d1, v1.d[1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: lsr x9, x8, #32
@@ -147,7 +147,7 @@ define i1 @test_v4i1(<4 x i1> %a) nounwind {
define i24 @test_v4i24(<4 x i24> %a) nounwind {
; CHECK-LABEL: test_v4i24:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: lsr x9, x8, #32
@@ -173,7 +173,7 @@ define i32 @test_v16i32(<16 x i32> %a) nounwind {
; CHECK-NEXT: and v1.16b, v1.16b, v3.16b
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: lsr x9, x8, #32
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-bitext.ll b/llvm/test/CodeGen/AArch64/vecreduce-bitext.ll
index cc65f17b71864..01606f7ea07b6 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-bitext.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-bitext.ll
@@ -37,7 +37,7 @@ entry:
define zeroext i16 @and_sext_v16i8_i16(<16 x i8> %x) {
; CHECK-LABEL: and_sext_v16i8_i16:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: and x8, x8, x8, lsr #32
@@ -56,7 +56,7 @@ entry:
define zeroext i16 @and_zext_v16i8_i16(<16 x i8> %x) {
; CHECK-LABEL: and_zext_v16i8_i16:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: and x8, x8, x8, lsr #32
@@ -106,7 +106,7 @@ entry:
define i32 @and_sext_v16i8_i32(<16 x i8> %x) {
; CHECK-LABEL: and_sext_v16i8_i32:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: and x8, x8, x8, lsr #32
@@ -124,7 +124,7 @@ entry:
define i32 @and_zext_v16i8_i32(<16 x i8> %x) {
; CHECK-LABEL: and_zext_v16i8_i32:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: and x8, x8, x8, lsr #32
@@ -174,7 +174,7 @@ entry:
define i64 @and_sext_v16i8_i64(<16 x i8> %x) {
; CHECK-LABEL: and_sext_v16i8_i64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: and x8, x8, x8, lsr #32
@@ -192,7 +192,7 @@ entry:
define i64 @and_zext_v16i8_i64(<16 x i8> %x) {
; CHECK-LABEL: and_zext_v16i8_i64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: and x8, x8, x8, lsr #32
@@ -239,7 +239,7 @@ entry:
define i32 @and_sext_v8i16_i32(<8 x i16> %x) {
; CHECK-LABEL: and_sext_v8i16_i32:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: lsr x9, x8, #32
@@ -256,7 +256,7 @@ entry:
define i32 @and_zext_v8i16_i32(<8 x i16> %x) {
; CHECK-LABEL: and_zext_v8i16_i32:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: and x8, x8, x8, lsr #32
@@ -301,7 +301,7 @@ entry:
define i64 @and_sext_v8i16_i64(<8 x i16> %x) {
; CHECK-LABEL: and_sext_v8i16_i64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: lsr x9, x8, #32
@@ -318,7 +318,7 @@ entry:
define i64 @and_zext_v8i16_i64(<8 x i16> %x) {
; CHECK-LABEL: and_zext_v8i16_i64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: and x8, x8, x8, lsr #32
@@ -361,7 +361,7 @@ entry:
define i64 @and_sext_v4i32_i64(<4 x i32> %x) {
; CHECK-LABEL: and_sext_v4i32_i64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: lsr x9, x8, #32
@@ -377,7 +377,7 @@ entry:
define i64 @and_zext_v4i32_i64(<4 x i32> %x) {
; CHECK-LABEL: and_zext_v4i32_i64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: lsr x9, x8, #32
@@ -425,7 +425,7 @@ entry:
define zeroext i16 @or_sext_v16i8_i16(<16 x i8> %x) {
; CHECK-LABEL: or_sext_v16i8_i16:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: orr x8, x8, x8, lsr #32
@@ -444,7 +444,7 @@ entry:
define zeroext i16 @or_zext_v16i8_i16(<16 x i8> %x) {
; CHECK-LABEL: or_zext_v16i8_i16:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: orr x8, x8, x8, lsr #32
@@ -494,7 +494,7 @@ entry:
define i32 @or_sext_v16i8_i32(<16 x i8> %x) {
; CHECK-LABEL: or_sext_v16i8_i32:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: orr x8, x8, x8, lsr #32
@@ -512,7 +512,7 @@ entry:
define i32 @or_zext_v16i8_i32(<16 x i8> %x) {
; CHECK-LABEL: or_zext_v16i8_i32:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: orr x8, x8, x8, lsr #32
@@ -562,7 +562,7 @@ entry:
define i64 @or_sext_v16i8_i64(<16 x i8> %x) {
; CHECK-LABEL: or_sext_v16i8_i64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: orr x8, x8, x8, lsr #32
@@ -580,7 +580,7 @@ entry:
define i64 @or_zext_v16i8_i64(<16 x i8> %x) {
; CHECK-LABEL: or_zext_v16i8_i64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: orr x8, x8, x8, lsr #32
@@ -628,7 +628,7 @@ entry:
define i32 @or_sext_v8i16_i32(<8 x i16> %x) {
; CHECK-LABEL: or_sext_v8i16_i32:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: lsr x9, x8, #32
@@ -645,7 +645,7 @@ entry:
define i32 @or_zext_v8i16_i32(<8 x i16> %x) {
; CHECK-LABEL: or_zext_v8i16_i32:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: lsr x9, x8, #32
@@ -692,7 +692,7 @@ entry:
define i64 @or_sext_v8i16_i64(<8 x i16> %x) {
; CHECK-LABEL: or_sext_v8i16_i64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: lsr x9, x8, #32
@@ -709,7 +709,7 @@ entry:
define i64 @or_zext_v8i16_i64(<8 x i16> %x) {
; CHECK-LABEL: or_zext_v8i16_i64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: lsr x9, x8, #32
@@ -753,7 +753,7 @@ entry:
define i64 @or_sext_v4i32_i64(<4 x i32> %x) {
; CHECK-LABEL: or_sext_v4i32_i64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: lsr x9, x8, #32
@@ -769,7 +769,7 @@ entry:
define i64 @or_zext_v4i32_i64(<4 x i32> %x) {
; CHECK-LABEL: or_zext_v4i32_i64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: lsr x9, x8, #32
@@ -817,7 +817,7 @@ entry:
define zeroext i16 @xor_sext_v16i8_i16(<16 x i8> %x) {
; CHECK-LABEL: xor_sext_v16i8_i16:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: eor x8, x8, x8, lsr #32
@@ -836,7 +836,7 @@ entry:
define zeroext i16 @xor_zext_v16i8_i16(<16 x i8> %x) {
; CHECK-LABEL: xor_zext_v16i8_i16:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: eor x8, x8, x8, lsr #32
@@ -886,7 +886,7 @@ entry:
define i32 @xor_sext_v16i8_i32(<16 x i8> %x) {
; CHECK-LABEL: xor_sext_v16i8_i32:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: eor x8, x8, x8, lsr #32
@@ -904,7 +904,7 @@ entry:
define i32 @xor_zext_v16i8_i32(<16 x i8> %x) {
; CHECK-LABEL: xor_zext_v16i8_i32:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: eor x8, x8, x8, lsr #32
@@ -954,7 +954,7 @@ entry:
define i64 @xor_sext_v16i8_i64(<16 x i8> %x) {
; CHECK-LABEL: xor_sext_v16i8_i64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: eor x8, x8, x8, lsr #32
@@ -972,7 +972,7 @@ entry:
define i64 @xor_zext_v16i8_i64(<16 x i8> %x) {
; CHECK-LABEL: xor_zext_v16i8_i64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: eor x8, x8, x8, lsr #32
@@ -1020,7 +1020,7 @@ entry:
define i32 @xor_sext_v8i16_i32(<8 x i16> %x) {
; CHECK-LABEL: xor_sext_v8i16_i32:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: lsr x9, x8, #32
@@ -1037,7 +1037,7 @@ entry:
define i32 @xor_zext_v8i16_i32(<8 x i16> %x) {
; CHECK-LABEL: xor_zext_v8i16_i32:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: lsr x9, x8, #32
@@ -1084,7 +1084,7 @@ entry:
define i64 @xor_sext_v8i16_i64(<8 x i16> %x) {
; CHECK-LABEL: xor_sext_v8i16_i64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: lsr x9, x8, #32
@@ -1101,7 +1101,7 @@ entry:
define i64 @xor_zext_v8i16_i64(<8 x i16> %x) {
; CHECK-LABEL: xor_zext_v8i16_i64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: lsr x9, x8, #32
@@ -1145,7 +1145,7 @@ entry:
define i64 @xor_sext_v4i32_i64(<4 x i32> %x) {
; CHECK-LABEL: xor_sext_v4i32_i64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: lsr x9, x8, #32
@@ -1161,7 +1161,7 @@ entry:
define i64 @xor_zext_v4i32_i64(<4 x i32> %x) {
; CHECK-LABEL: xor_zext_v4i32_i64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: lsr x9, x8, #32
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-fmul.ll b/llvm/test/CodeGen/AArch64/vecreduce-fmul.ll
index f4825f065d316..5b09714402a38 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-fmul.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-fmul.ll
@@ -77,7 +77,7 @@ define half @mul_H(<8 x half> %bin.rdx) {
; CHECK-SD-NOFP16-NEXT: fcvtl2 v1.4s, v0.8h
; CHECK-SD-NOFP16-NEXT: fcvtl v0.4s, v0.4h
; CHECK-SD-NOFP16-NEXT: fmul v0.4s, v0.4s, v1.4s
-; CHECK-SD-NOFP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NOFP16-NEXT: mov d1, v0.d[1]
; CHECK-SD-NOFP16-NEXT: fmul v0.2s, v0.2s, v1.2s
; CHECK-SD-NOFP16-NEXT: fmul s0, s0, v0.s[1]
; CHECK-SD-NOFP16-NEXT: fcvt h0, s0
@@ -85,7 +85,7 @@ define half @mul_H(<8 x half> %bin.rdx) {
;
; CHECK-SD-FP16-LABEL: mul_H:
; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-FP16-NEXT: mov d1, v0.d[1]
; CHECK-SD-FP16-NEXT: fmul v0.4h, v0.4h, v1.4h
; CHECK-SD-FP16-NEXT: fmul h1, h0, v0.h[1]
; CHECK-SD-FP16-NEXT: fmul h1, h1, v0.h[2]
@@ -122,7 +122,7 @@ define half @mul_H(<8 x half> %bin.rdx) {
define float @mul_S(<4 x float> %bin.rdx) {
; CHECK-SD-LABEL: mul_S:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: fmul v0.2s, v0.2s, v1.2s
; CHECK-SD-NEXT: fmul s0, s0, v0.s[1]
; CHECK-SD-NEXT: ret
@@ -161,7 +161,7 @@ define half @mul_2H(<16 x half> %bin.rdx) {
; CHECK-SD-NOFP16-NEXT: fcvtl v1.4s, v1.4h
; CHECK-SD-NOFP16-NEXT: fcvtl v0.4s, v0.4h
; CHECK-SD-NOFP16-NEXT: fmul v0.4s, v0.4s, v1.4s
-; CHECK-SD-NOFP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NOFP16-NEXT: mov d1, v0.d[1]
; CHECK-SD-NOFP16-NEXT: fmul v0.2s, v0.2s, v1.2s
; CHECK-SD-NOFP16-NEXT: fmul s0, s0, v0.s[1]
; CHECK-SD-NOFP16-NEXT: fcvt h0, s0
@@ -170,7 +170,7 @@ define half @mul_2H(<16 x half> %bin.rdx) {
; CHECK-SD-FP16-LABEL: mul_2H:
; CHECK-SD-FP16: // %bb.0:
; CHECK-SD-FP16-NEXT: fmul v0.8h, v0.8h, v1.8h
-; CHECK-SD-FP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-FP16-NEXT: mov d1, v0.d[1]
; CHECK-SD-FP16-NEXT: fmul v0.4h, v0.4h, v1.4h
; CHECK-SD-FP16-NEXT: fmul h1, h0, v0.h[1]
; CHECK-SD-FP16-NEXT: fmul h1, h1, v0.h[2]
@@ -213,7 +213,7 @@ define float @mul_2S(<8 x float> %bin.rdx) {
; CHECK-SD-LABEL: mul_2S:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: fmul v0.4s, v0.4s, v1.4s
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: fmul v0.2s, v0.2s, v1.2s
; CHECK-SD-NEXT: fmul s0, s0, v0.s[1]
; CHECK-SD-NEXT: ret
@@ -244,7 +244,7 @@ define double @mul_2D(<4 x double> %bin.rdx) {
define float @mul_S_init_42(<4 x float> %bin.rdx) {
; CHECK-SD-LABEL: mul_S_init_42:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: mov w8, #1109917696 // =0x42280000
; CHECK-SD-NEXT: fmul v0.2s, v0.2s, v1.2s
; CHECK-SD-NEXT: fmov s1, w8
@@ -276,8 +276,8 @@ define half @fmul_reduct_reassoc_v8f16(<8 x half> %a, <8 x half> %b) {
; CHECK-SD-NOFP16-NEXT: fcvtl v1.4s, v1.4h
; CHECK-SD-NOFP16-NEXT: fmul v0.4s, v0.4s, v2.4s
; CHECK-SD-NOFP16-NEXT: fmul v1.4s, v1.4s, v3.4s
-; CHECK-SD-NOFP16-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NOFP16-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-SD-NOFP16-NEXT: mov d2, v0.d[1]
+; CHECK-SD-NOFP16-NEXT: mov d3, v1.d[1]
; CHECK-SD-NOFP16-NEXT: fmul v0.2s, v0.2s, v2.2s
; CHECK-SD-NOFP16-NEXT: fmul v1.2s, v1.2s, v3.2s
; CHECK-SD-NOFP16-NEXT: fmul s0, s0, v0.s[1]
@@ -293,7 +293,7 @@ define half @fmul_reduct_reassoc_v8f16(<8 x half> %a, <8 x half> %b) {
; CHECK-SD-FP16-LABEL: fmul_reduct_reassoc_v8f16:
; CHECK-SD-FP16: // %bb.0:
; CHECK-SD-FP16-NEXT: fmul v0.8h, v0.8h, v1.8h
-; CHECK-SD-FP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-FP16-NEXT: mov d1, v0.d[1]
; CHECK-SD-FP16-NEXT: fmul v0.4h, v0.4h, v1.4h
; CHECK-SD-FP16-NEXT: fmul h1, h0, v0.h[1]
; CHECK-SD-FP16-NEXT: fmul h1, h1, v0.h[2]
@@ -356,7 +356,7 @@ define float @fmul_reduct_reassoc_v8f32(<8 x float> %a, <8 x float> %b) {
; CHECK-SD-NEXT: fmul v2.4s, v2.4s, v3.4s
; CHECK-SD-NEXT: fmul v0.4s, v0.4s, v1.4s
; CHECK-SD-NEXT: fmul v0.4s, v0.4s, v2.4s
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: fmul v0.2s, v0.2s, v1.2s
; CHECK-SD-NEXT: fmul s0, s0, v0.s[1]
; CHECK-SD-NEXT: ret
@@ -385,7 +385,7 @@ define float @fmul_reduct_reassoc_v4f32(<4 x float> %a, <4 x float> %b) {
; CHECK-SD-LABEL: fmul_reduct_reassoc_v4f32:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: fmul v0.4s, v0.4s, v1.4s
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: fmul v0.2s, v0.2s, v1.2s
; CHECK-SD-NEXT: fmul s0, s0, v0.s[1]
; CHECK-SD-NEXT: ret
@@ -411,9 +411,9 @@ define float @fmul_reduct_reassoc_v4f32(<4 x float> %a, <4 x float> %b) {
define float @fmul_reduct_reassoc_v4f32_init(float %i, <4 x float> %a, <4 x float> %b) {
; CHECK-SD-LABEL: fmul_reduct_reassoc_v4f32_init:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-SD-NEXT: mov d3, v1.d[1]
; CHECK-SD-NEXT: fmul v1.2s, v1.2s, v3.2s
-; CHECK-SD-NEXT: ext v3.16b, v2.16b, v2.16b, #8
+; CHECK-SD-NEXT: mov d3, v2.d[1]
; CHECK-SD-NEXT: fmul s1, s1, v1.s[1]
; CHECK-SD-NEXT: fmul v2.2s, v2.2s, v3.2s
; CHECK-SD-NEXT: fmul s0, s0, s1
@@ -445,7 +445,7 @@ define float @fmul_reduct_reassoc_v4v8f32(<4 x float> %a, <8 x float> %b) {
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: fmul v1.4s, v1.4s, v2.4s
; CHECK-SD-NEXT: fmul v0.4s, v0.4s, v1.4s
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: fmul v0.2s, v0.2s, v1.2s
; CHECK-SD-NEXT: fmul s0, s0, v0.s[1]
; CHECK-SD-NEXT: ret
@@ -495,8 +495,8 @@ define double @fmul_reduct_reassoc_v4f64(<4 x double> %a, <4 x double> %b) {
define float @fmul_reduct_reassoc_v4f32_extrause(<4 x float> %a, <4 x float> %b) {
; CHECK-SD-LABEL: fmul_reduct_reassoc_v4f32_extrause:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-SD-NEXT: mov d2, v0.d[1]
+; CHECK-SD-NEXT: mov d3, v1.d[1]
; CHECK-SD-NEXT: fmul v0.2s, v0.2s, v2.2s
; CHECK-SD-NEXT: fmul v1.2s, v1.2s, v3.2s
; CHECK-SD-NEXT: fmul s0, s0, v0.s[1]
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll b/llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
index 0806f7da5c89c..c6617dbd20c2e 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
@@ -98,7 +98,7 @@ define i128 @test_v1i128(<1 x i128> %a) nounwind {
define i64 @test_v2i64(<2 x i64> %a) nounwind {
; CHECK-SD-LABEL: test_v2i64:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: cmhi d2, d0, d1
; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b
; CHECK-SD-NEXT: fmov x0, d0
diff --git a/llvm/test/CodeGen/AArch64/vector-fcvt.ll b/llvm/test/CodeGen/AArch64/vector-fcvt.ll
index c3b7161feefb5..e8a9a830dced4 100644
--- a/llvm/test/CodeGen/AArch64/vector-fcvt.ll
+++ b/llvm/test/CodeGen/AArch64/vector-fcvt.ll
@@ -36,7 +36,7 @@ define <8 x float> @sitofp_v8i8_float(<8 x i8> %a) {
define <16 x float> @sitofp_v16i8_float(<16 x i8> %a) {
; CHECK-LABEL: sitofp_v16i8_float:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: zip1 v2.8b, v0.8b, v0.8b
; CHECK-NEXT: zip2 v0.8b, v0.8b, v0.8b
; CHECK-NEXT: zip1 v3.8b, v1.8b, v0.8b
@@ -145,7 +145,7 @@ define <8 x float> @uitofp_v8i8_float(<8 x i8> %a) {
define <16 x float> @uitofp_v16i8_float(<16 x i8> %a) {
; CHECK-LABEL: uitofp_v16i8_float:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: zip1 v2.8b, v0.8b, v0.8b
; CHECK-NEXT: zip2 v0.8b, v0.8b, v0.8b
; CHECK-NEXT: zip1 v3.8b, v1.8b, v0.8b
@@ -225,7 +225,7 @@ define <4 x double> @sitofp_v4i8_double(<4 x i8> %a) {
; CHECK-LABEL: sitofp_v4i8_double:
; CHECK: // %bb.0:
; CHECK-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: shl v0.2s, v0.2s, #24
; CHECK-NEXT: sshr v0.2s, v0.2s, #24
; CHECK-NEXT: shl v1.2s, v1.2s, #24
@@ -275,7 +275,7 @@ define <8 x double> @sitofp_v8i8_double(<8 x i8> %a) {
define <16 x double> @sitofp_v16i8_double(<16 x i8> %a) {
; CHECK-LABEL: sitofp_v16i8_double:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: mov b2, v0.b[0]
; CHECK-NEXT: mov b3, v0.b[2]
; CHECK-NEXT: mov b4, v0.b[4]
@@ -380,7 +380,7 @@ define <4 x double> @uitofp_v4i8_double(<4 x i8> %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-NEXT: movi d1, #0x0000ff000000ff
-; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d2, v0.d[1]
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: and v1.8b, v2.8b, v1.8b
; CHECK-NEXT: ushll v0.2d, v0.2s, #0
@@ -425,7 +425,7 @@ define <8 x double> @uitofp_v8i8_double(<8 x i8> %a) {
define <16 x double> @uitofp_v16i8_double(<16 x i8> %a) {
; CHECK-LABEL: uitofp_v16i8_double:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d2, v0.d[1]
; CHECK-NEXT: mov b3, v0.b[0]
; CHECK-NEXT: mov b4, v0.b[2]
; CHECK-NEXT: mov b5, v0.b[4]
diff --git a/llvm/test/CodeGen/AArch64/vector-llrint.ll b/llvm/test/CodeGen/AArch64/vector-llrint.ll
index d9a9e57fe0a63..d1fe25457de8e 100644
--- a/llvm/test/CodeGen/AArch64/vector-llrint.ll
+++ b/llvm/test/CodeGen/AArch64/vector-llrint.ll
@@ -88,7 +88,7 @@ declare <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half>)
define <8 x i64> @llrint_v8i64_v8f16(<8 x half> %x) nounwind {
; CHECK-SD-LABEL: llrint_v8i64_v8f16:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: mov h4, v0.h[2]
; CHECK-SD-NEXT: mov h3, v0.h[1]
; CHECK-SD-NEXT: mov h7, v0.h[3]
@@ -156,8 +156,8 @@ declare <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half>)
define <16 x i64> @llrint_v16i64_v16f16(<16 x half> %x) nounwind {
; CHECK-SD-LABEL: llrint_v16i64_v16f16:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-SD-NEXT: mov d2, v0.d[1]
+; CHECK-SD-NEXT: mov d3, v1.d[1]
; CHECK-SD-NEXT: mov h17, v0.h[1]
; CHECK-SD-NEXT: mov h19, v0.h[2]
; CHECK-SD-NEXT: fcvt s18, h0
@@ -279,10 +279,10 @@ declare <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half>)
define <32 x i64> @llrint_v32i64_v32f16(<32 x half> %x) nounwind {
; CHECK-SD-LABEL: llrint_v32i64_v32f16:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v4.16b, v1.16b, v1.16b, #8
-; CHECK-SD-NEXT: ext v5.16b, v2.16b, v2.16b, #8
-; CHECK-SD-NEXT: ext v6.16b, v3.16b, v3.16b, #8
-; CHECK-SD-NEXT: ext v7.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d4, v1.d[1]
+; CHECK-SD-NEXT: mov d5, v2.d[1]
+; CHECK-SD-NEXT: mov d6, v3.d[1]
+; CHECK-SD-NEXT: mov d7, v0.d[1]
; CHECK-SD-NEXT: mov h19, v0.h[1]
; CHECK-SD-NEXT: fcvt s21, h0
; CHECK-SD-NEXT: mov h23, v1.h[2]
@@ -560,7 +560,7 @@ declare <2 x i64> @llvm.llrint.v2i64.v2f32(<2 x float>)
define <4 x i64> @llrint_v4i64_v4f32(<4 x float> %x) nounwind {
; CHECK-SD-LABEL: llrint_v4i64_v4f32:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: frintx v0.2s, v0.2s
; CHECK-SD-NEXT: frintx v1.2s, v1.2s
; CHECK-SD-NEXT: fcvtl v0.2d, v0.2s
@@ -585,19 +585,19 @@ declare <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float>)
define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x) nounwind {
; CHECK-SD-LABEL: llrint_v8i64_v8f32:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-SD-NEXT: mov d2, v0.d[1]
+; CHECK-SD-NEXT: mov d3, v1.d[1]
; CHECK-SD-NEXT: frintx v0.2s, v0.2s
; CHECK-SD-NEXT: frintx v1.2s, v1.2s
; CHECK-SD-NEXT: frintx v2.2s, v2.2s
; CHECK-SD-NEXT: frintx v3.2s, v3.2s
; CHECK-SD-NEXT: fcvtl v0.2d, v0.2s
-; CHECK-SD-NEXT: fcvtl v1.2d, v1.2s
-; CHECK-SD-NEXT: fcvtl v4.2d, v2.2s
+; CHECK-SD-NEXT: fcvtl v4.2d, v1.2s
+; CHECK-SD-NEXT: fcvtl v2.2d, v2.2s
; CHECK-SD-NEXT: fcvtl v3.2d, v3.2s
; CHECK-SD-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-SD-NEXT: fcvtzs v2.2d, v1.2d
-; CHECK-SD-NEXT: fcvtzs v1.2d, v4.2d
+; CHECK-SD-NEXT: fcvtzs v1.2d, v2.2d
+; CHECK-SD-NEXT: fcvtzs v2.2d, v4.2d
; CHECK-SD-NEXT: fcvtzs v3.2d, v3.2d
; CHECK-SD-NEXT: ret
;
@@ -622,10 +622,10 @@ declare <8 x i64> @llvm.llrint.v8i64.v8f32(<8 x float>)
define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x) nounwind {
; CHECK-SD-LABEL: llrint_v16i64_v16f32:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v4.16b, v1.16b, v1.16b, #8
-; CHECK-SD-NEXT: ext v5.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: ext v6.16b, v2.16b, v2.16b, #8
-; CHECK-SD-NEXT: ext v7.16b, v3.16b, v3.16b, #8
+; CHECK-SD-NEXT: mov d4, v1.d[1]
+; CHECK-SD-NEXT: mov d5, v0.d[1]
+; CHECK-SD-NEXT: mov d6, v2.d[1]
+; CHECK-SD-NEXT: mov d7, v3.d[1]
; CHECK-SD-NEXT: frintx v0.2s, v0.2s
; CHECK-SD-NEXT: frintx v1.2s, v1.2s
; CHECK-SD-NEXT: frintx v2.2s, v2.2s
@@ -683,70 +683,70 @@ declare <16 x i64> @llvm.llrint.v16i64.v16f32(<16 x float>)
define <32 x i64> @llrint_v32i64_v32f32(<32 x float> %x) nounwind {
; CHECK-SD-LABEL: llrint_v32i64_v32f32:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v16.16b, v7.16b, v7.16b, #8
-; CHECK-SD-NEXT: ext v17.16b, v6.16b, v6.16b, #8
+; CHECK-SD-NEXT: mov d16, v7.d[1]
+; CHECK-SD-NEXT: mov d17, v6.d[1]
; CHECK-SD-NEXT: frintx v7.2s, v7.2s
+; CHECK-SD-NEXT: mov d18, v5.d[1]
; CHECK-SD-NEXT: frintx v6.2s, v6.2s
-; CHECK-SD-NEXT: ext v18.16b, v5.16b, v5.16b, #8
-; CHECK-SD-NEXT: ext v21.16b, v4.16b, v4.16b, #8
-; CHECK-SD-NEXT: ext v22.16b, v2.16b, v2.16b, #8
+; CHECK-SD-NEXT: mov d19, v4.d[1]
+; CHECK-SD-NEXT: mov d22, v3.d[1]
; CHECK-SD-NEXT: frintx v5.2s, v5.2s
-; CHECK-SD-NEXT: ext v23.16b, v3.16b, v3.16b, #8
-; CHECK-SD-NEXT: frintx v4.2s, v4.2s
-; CHECK-SD-NEXT: ext v19.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: ext v20.16b, v1.16b, v1.16b, #8
+; CHECK-SD-NEXT: mov d20, v0.d[1]
+; CHECK-SD-NEXT: frintx v21.2s, v1.2s
+; CHECK-SD-NEXT: mov d1, v1.d[1]
+; CHECK-SD-NEXT: mov d23, v2.d[1]
; CHECK-SD-NEXT: frintx v16.2s, v16.2s
; CHECK-SD-NEXT: frintx v17.2s, v17.2s
; CHECK-SD-NEXT: fcvtl v7.2d, v7.2s
-; CHECK-SD-NEXT: fcvtl v6.2d, v6.2s
; CHECK-SD-NEXT: frintx v18.2s, v18.2s
-; CHECK-SD-NEXT: frintx v21.2s, v21.2s
-; CHECK-SD-NEXT: frintx v2.2s, v2.2s
+; CHECK-SD-NEXT: fcvtl v6.2d, v6.2s
+; CHECK-SD-NEXT: frintx v19.2s, v19.2s
+; CHECK-SD-NEXT: frintx v4.2s, v4.2s
+; CHECK-SD-NEXT: frintx v22.2s, v22.2s
; CHECK-SD-NEXT: frintx v3.2s, v3.2s
; CHECK-SD-NEXT: fcvtl v5.2d, v5.2s
+; CHECK-SD-NEXT: frintx v2.2s, v2.2s
; CHECK-SD-NEXT: frintx v23.2s, v23.2s
-; CHECK-SD-NEXT: fcvtl v4.2d, v4.2s
-; CHECK-SD-NEXT: frintx v1.2s, v1.2s
; CHECK-SD-NEXT: fcvtl v16.2d, v16.2s
; CHECK-SD-NEXT: fcvtl v17.2d, v17.2s
; CHECK-SD-NEXT: fcvtzs v7.2d, v7.2d
-; CHECK-SD-NEXT: fcvtzs v6.2d, v6.2d
; CHECK-SD-NEXT: fcvtl v18.2d, v18.2s
-; CHECK-SD-NEXT: fcvtl v21.2d, v21.2s
-; CHECK-SD-NEXT: frintx v20.2s, v20.2s
+; CHECK-SD-NEXT: fcvtzs v6.2d, v6.2d
+; CHECK-SD-NEXT: fcvtl v19.2d, v19.2s
+; CHECK-SD-NEXT: frintx v1.2s, v1.2s
+; CHECK-SD-NEXT: fcvtl v4.2d, v4.2s
; CHECK-SD-NEXT: fcvtl v3.2d, v3.2s
; CHECK-SD-NEXT: fcvtzs v5.2d, v5.2d
; CHECK-SD-NEXT: frintx v0.2s, v0.2s
; CHECK-SD-NEXT: fcvtl v2.2d, v2.2s
-; CHECK-SD-NEXT: fcvtzs v4.2d, v4.2d
; CHECK-SD-NEXT: fcvtzs v16.2d, v16.2d
; CHECK-SD-NEXT: fcvtzs v17.2d, v17.2d
+; CHECK-SD-NEXT: fcvtzs v4.2d, v4.2d
; CHECK-SD-NEXT: fcvtl v1.2d, v1.2s
; CHECK-SD-NEXT: fcvtzs v3.2d, v3.2d
; CHECK-SD-NEXT: fcvtl v0.2d, v0.2s
; CHECK-SD-NEXT: fcvtzs v2.2d, v2.2d
; CHECK-SD-NEXT: stp q6, q17, [x8, #192]
-; CHECK-SD-NEXT: fcvtl v6.2d, v23.2s
-; CHECK-SD-NEXT: frintx v17.2s, v19.2s
+; CHECK-SD-NEXT: frintx v6.2s, v20.2s
+; CHECK-SD-NEXT: fcvtl v17.2d, v23.2s
; CHECK-SD-NEXT: stp q7, q16, [x8, #224]
-; CHECK-SD-NEXT: frintx v7.2s, v22.2s
+; CHECK-SD-NEXT: fcvtl v7.2d, v22.2s
; CHECK-SD-NEXT: fcvtzs v16.2d, v18.2d
-; CHECK-SD-NEXT: fcvtzs v18.2d, v21.2d
+; CHECK-SD-NEXT: fcvtzs v18.2d, v19.2d
; CHECK-SD-NEXT: fcvtzs v1.2d, v1.2d
; CHECK-SD-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-SD-NEXT: fcvtzs v6.2d, v6.2d
+; CHECK-SD-NEXT: fcvtl v6.2d, v6.2s
; CHECK-SD-NEXT: stp q5, q16, [x8, #160]
-; CHECK-SD-NEXT: fcvtl v7.2d, v7.2s
-; CHECK-SD-NEXT: fcvtl v5.2d, v20.2s
-; CHECK-SD-NEXT: stp q4, q18, [x8, #128]
-; CHECK-SD-NEXT: fcvtl v4.2d, v17.2s
-; CHECK-SD-NEXT: stp q3, q6, [x8, #96]
; CHECK-SD-NEXT: fcvtzs v7.2d, v7.2d
+; CHECK-SD-NEXT: fcvtl v5.2d, v21.2s
+; CHECK-SD-NEXT: stp q4, q18, [x8, #128]
+; CHECK-SD-NEXT: fcvtzs v16.2d, v17.2d
+; CHECK-SD-NEXT: fcvtzs v4.2d, v6.2d
+; CHECK-SD-NEXT: stp q3, q7, [x8, #96]
; CHECK-SD-NEXT: fcvtzs v3.2d, v5.2d
-; CHECK-SD-NEXT: stp q1, q3, [x8, #32]
-; CHECK-SD-NEXT: stp q2, q7, [x8, #64]
-; CHECK-SD-NEXT: fcvtzs v2.2d, v4.2d
-; CHECK-SD-NEXT: stp q0, q2, [x8]
+; CHECK-SD-NEXT: stp q2, q16, [x8, #64]
+; CHECK-SD-NEXT: stp q0, q4, [x8]
+; CHECK-SD-NEXT: stp q3, q1, [x8, #32]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: llrint_v32i64_v32f32:
diff --git a/llvm/test/CodeGen/AArch64/vector-lrint.ll b/llvm/test/CodeGen/AArch64/vector-lrint.ll
index 2abe0b7ae2106..67e1f6a77a2ff 100644
--- a/llvm/test/CodeGen/AArch64/vector-lrint.ll
+++ b/llvm/test/CodeGen/AArch64/vector-lrint.ll
@@ -158,7 +158,7 @@ declare <4 x iXLen> @llvm.lrint.v4iXLen.v4f16(<4 x half>)
define <8 x iXLen> @lrint_v8f16(<8 x half> %x) nounwind {
; CHECK-i32-SD-LABEL: lrint_v8f16:
; CHECK-i32-SD: // %bb.0:
-; CHECK-i32-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-i32-SD-NEXT: mov d1, v0.d[1]
; CHECK-i32-SD-NEXT: mov h2, v0.h[1]
; CHECK-i32-SD-NEXT: mov h4, v0.h[2]
; CHECK-i32-SD-NEXT: fcvt s7, h0
@@ -199,7 +199,7 @@ define <8 x iXLen> @lrint_v8f16(<8 x half> %x) nounwind {
;
; CHECK-i64-SD-LABEL: lrint_v8f16:
; CHECK-i64-SD: // %bb.0:
-; CHECK-i64-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-i64-SD-NEXT: mov d1, v0.d[1]
; CHECK-i64-SD-NEXT: mov h4, v0.h[2]
; CHECK-i64-SD-NEXT: mov h3, v0.h[1]
; CHECK-i64-SD-NEXT: mov h7, v0.h[3]
@@ -281,8 +281,8 @@ declare <8 x iXLen> @llvm.lrint.v8iXLen.v8f16(<8 x half>)
define <16 x iXLen> @lrint_v16f16(<16 x half> %x) nounwind {
; CHECK-i32-SD-LABEL: lrint_v16f16:
; CHECK-i32-SD: // %bb.0:
-; CHECK-i32-SD-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-i32-SD-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-i32-SD-NEXT: mov d2, v0.d[1]
+; CHECK-i32-SD-NEXT: mov d3, v1.d[1]
; CHECK-i32-SD-NEXT: mov h4, v0.h[1]
; CHECK-i32-SD-NEXT: mov h5, v1.h[1]
; CHECK-i32-SD-NEXT: mov h16, v0.h[2]
@@ -359,8 +359,8 @@ define <16 x iXLen> @lrint_v16f16(<16 x half> %x) nounwind {
;
; CHECK-i64-SD-LABEL: lrint_v16f16:
; CHECK-i64-SD: // %bb.0:
-; CHECK-i64-SD-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-i64-SD-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-i64-SD-NEXT: mov d2, v0.d[1]
+; CHECK-i64-SD-NEXT: mov d3, v1.d[1]
; CHECK-i64-SD-NEXT: mov h17, v0.h[1]
; CHECK-i64-SD-NEXT: mov h19, v0.h[2]
; CHECK-i64-SD-NEXT: fcvt s18, h0
@@ -507,9 +507,9 @@ define <32 x iXLen> @lrint_v32f16(<32 x half> %x) nounwind {
; CHECK-i32-SD-LABEL: lrint_v32f16:
; CHECK-i32-SD: // %bb.0:
; CHECK-i32-SD-NEXT: str x19, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-i32-SD-NEXT: ext v4.16b, v0.16b, v0.16b, #8
-; CHECK-i32-SD-NEXT: ext v5.16b, v1.16b, v1.16b, #8
-; CHECK-i32-SD-NEXT: ext v6.16b, v2.16b, v2.16b, #8
+; CHECK-i32-SD-NEXT: mov d4, v0.d[1]
+; CHECK-i32-SD-NEXT: mov d5, v1.d[1]
+; CHECK-i32-SD-NEXT: mov d6, v2.d[1]
; CHECK-i32-SD-NEXT: mov h27, v3.h[2]
; CHECK-i32-SD-NEXT: mov h16, v4.h[2]
; CHECK-i32-SD-NEXT: mov h17, v4.h[3]
@@ -526,7 +526,7 @@ define <32 x iXLen> @lrint_v32f16(<32 x half> %x) nounwind {
; CHECK-i32-SD-NEXT: fcvt s18, h18
; CHECK-i32-SD-NEXT: fcvt s23, h7
; CHECK-i32-SD-NEXT: fcvt s19, h19
-; CHECK-i32-SD-NEXT: ext v7.16b, v3.16b, v3.16b, #8
+; CHECK-i32-SD-NEXT: mov d7, v3.d[1]
; CHECK-i32-SD-NEXT: fcvt s20, h20
; CHECK-i32-SD-NEXT: fcvt s21, h21
; CHECK-i32-SD-NEXT: fcvt s22, h22
@@ -660,10 +660,10 @@ define <32 x iXLen> @lrint_v32f16(<32 x half> %x) nounwind {
;
; CHECK-i64-SD-LABEL: lrint_v32f16:
; CHECK-i64-SD: // %bb.0:
-; CHECK-i64-SD-NEXT: ext v4.16b, v1.16b, v1.16b, #8
-; CHECK-i64-SD-NEXT: ext v5.16b, v2.16b, v2.16b, #8
-; CHECK-i64-SD-NEXT: ext v6.16b, v3.16b, v3.16b, #8
-; CHECK-i64-SD-NEXT: ext v7.16b, v0.16b, v0.16b, #8
+; CHECK-i64-SD-NEXT: mov d4, v1.d[1]
+; CHECK-i64-SD-NEXT: mov d5, v2.d[1]
+; CHECK-i64-SD-NEXT: mov d6, v3.d[1]
+; CHECK-i64-SD-NEXT: mov d7, v0.d[1]
; CHECK-i64-SD-NEXT: mov h19, v0.h[1]
; CHECK-i64-SD-NEXT: fcvt s21, h0
; CHECK-i64-SD-NEXT: mov h23, v1.h[2]
@@ -1009,7 +1009,7 @@ define <4 x iXLen> @lrint_v4f32(<4 x float> %x) nounwind {
;
; CHECK-i64-SD-LABEL: lrint_v4f32:
; CHECK-i64-SD: // %bb.0:
-; CHECK-i64-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-i64-SD-NEXT: mov d1, v0.d[1]
; CHECK-i64-SD-NEXT: frintx v0.2s, v0.2s
; CHECK-i64-SD-NEXT: frintx v1.2s, v1.2s
; CHECK-i64-SD-NEXT: fcvtl v0.2d, v0.2s
@@ -1042,19 +1042,19 @@ define <8 x iXLen> @lrint_v8f32(<8 x float> %x) nounwind {
;
; CHECK-i64-SD-LABEL: lrint_v8f32:
; CHECK-i64-SD: // %bb.0:
-; CHECK-i64-SD-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-i64-SD-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-i64-SD-NEXT: mov d2, v0.d[1]
+; CHECK-i64-SD-NEXT: mov d3, v1.d[1]
; CHECK-i64-SD-NEXT: frintx v0.2s, v0.2s
; CHECK-i64-SD-NEXT: frintx v1.2s, v1.2s
; CHECK-i64-SD-NEXT: frintx v2.2s, v2.2s
; CHECK-i64-SD-NEXT: frintx v3.2s, v3.2s
; CHECK-i64-SD-NEXT: fcvtl v0.2d, v0.2s
-; CHECK-i64-SD-NEXT: fcvtl v1.2d, v1.2s
-; CHECK-i64-SD-NEXT: fcvtl v4.2d, v2.2s
+; CHECK-i64-SD-NEXT: fcvtl v4.2d, v1.2s
+; CHECK-i64-SD-NEXT: fcvtl v2.2d, v2.2s
; CHECK-i64-SD-NEXT: fcvtl v3.2d, v3.2s
; CHECK-i64-SD-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-i64-SD-NEXT: fcvtzs v2.2d, v1.2d
-; CHECK-i64-SD-NEXT: fcvtzs v1.2d, v4.2d
+; CHECK-i64-SD-NEXT: fcvtzs v1.2d, v2.2d
+; CHECK-i64-SD-NEXT: fcvtzs v2.2d, v4.2d
; CHECK-i64-SD-NEXT: fcvtzs v3.2d, v3.2d
; CHECK-i64-SD-NEXT: ret
;
@@ -1091,10 +1091,10 @@ define <16 x iXLen> @lrint_v16f32(<16 x float> %x) nounwind {
;
; CHECK-i64-SD-LABEL: lrint_v16f32:
; CHECK-i64-SD: // %bb.0:
-; CHECK-i64-SD-NEXT: ext v4.16b, v1.16b, v1.16b, #8
-; CHECK-i64-SD-NEXT: ext v5.16b, v0.16b, v0.16b, #8
-; CHECK-i64-SD-NEXT: ext v6.16b, v2.16b, v2.16b, #8
-; CHECK-i64-SD-NEXT: ext v7.16b, v3.16b, v3.16b, #8
+; CHECK-i64-SD-NEXT: mov d4, v1.d[1]
+; CHECK-i64-SD-NEXT: mov d5, v0.d[1]
+; CHECK-i64-SD-NEXT: mov d6, v2.d[1]
+; CHECK-i64-SD-NEXT: mov d7, v3.d[1]
; CHECK-i64-SD-NEXT: frintx v0.2s, v0.2s
; CHECK-i64-SD-NEXT: frintx v1.2s, v1.2s
; CHECK-i64-SD-NEXT: frintx v2.2s, v2.2s
@@ -1172,70 +1172,70 @@ define <32 x iXLen> @lrint_v32f32(<32 x float> %x) nounwind {
;
; CHECK-i64-SD-LABEL: lrint_v32f32:
; CHECK-i64-SD: // %bb.0:
-; CHECK-i64-SD-NEXT: ext v16.16b, v7.16b, v7.16b, #8
-; CHECK-i64-SD-NEXT: ext v17.16b, v6.16b, v6.16b, #8
+; CHECK-i64-SD-NEXT: mov d16, v7.d[1]
+; CHECK-i64-SD-NEXT: mov d17, v6.d[1]
; CHECK-i64-SD-NEXT: frintx v7.2s, v7.2s
+; CHECK-i64-SD-NEXT: mov d18, v5.d[1]
; CHECK-i64-SD-NEXT: frintx v6.2s, v6.2s
-; CHECK-i64-SD-NEXT: ext v18.16b, v5.16b, v5.16b, #8
-; CHECK-i64-SD-NEXT: ext v21.16b, v4.16b, v4.16b, #8
-; CHECK-i64-SD-NEXT: ext v22.16b, v2.16b, v2.16b, #8
+; CHECK-i64-SD-NEXT: mov d19, v4.d[1]
+; CHECK-i64-SD-NEXT: mov d22, v3.d[1]
; CHECK-i64-SD-NEXT: frintx v5.2s, v5.2s
-; CHECK-i64-SD-NEXT: ext v23.16b, v3.16b, v3.16b, #8
-; CHECK-i64-SD-NEXT: frintx v4.2s, v4.2s
-; CHECK-i64-SD-NEXT: ext v19.16b, v0.16b, v0.16b, #8
-; CHECK-i64-SD-NEXT: ext v20.16b, v1.16b, v1.16b, #8
+; CHECK-i64-SD-NEXT: mov d20, v0.d[1]
+; CHECK-i64-SD-NEXT: frintx v21.2s, v1.2s
+; CHECK-i64-SD-NEXT: mov d1, v1.d[1]
+; CHECK-i64-SD-NEXT: mov d23, v2.d[1]
; CHECK-i64-SD-NEXT: frintx v16.2s, v16.2s
; CHECK-i64-SD-NEXT: frintx v17.2s, v17.2s
; CHECK-i64-SD-NEXT: fcvtl v7.2d, v7.2s
-; CHECK-i64-SD-NEXT: fcvtl v6.2d, v6.2s
; CHECK-i64-SD-NEXT: frintx v18.2s, v18.2s
-; CHECK-i64-SD-NEXT: frintx v21.2s, v21.2s
-; CHECK-i64-SD-NEXT: frintx v2.2s, v2.2s
+; CHECK-i64-SD-NEXT: fcvtl v6.2d, v6.2s
+; CHECK-i64-SD-NEXT: frintx v19.2s, v19.2s
+; CHECK-i64-SD-NEXT: frintx v4.2s, v4.2s
+; CHECK-i64-SD-NEXT: frintx v22.2s, v22.2s
; CHECK-i64-SD-NEXT: frintx v3.2s, v3.2s
; CHECK-i64-SD-NEXT: fcvtl v5.2d, v5.2s
+; CHECK-i64-SD-NEXT: frintx v2.2s, v2.2s
; CHECK-i64-SD-NEXT: frintx v23.2s, v23.2s
-; CHECK-i64-SD-NEXT: fcvtl v4.2d, v4.2s
-; CHECK-i64-SD-NEXT: frintx v1.2s, v1.2s
; CHECK-i64-SD-NEXT: fcvtl v16.2d, v16.2s
; CHECK-i64-SD-NEXT: fcvtl v17.2d, v17.2s
; CHECK-i64-SD-NEXT: fcvtzs v7.2d, v7.2d
-; CHECK-i64-SD-NEXT: fcvtzs v6.2d, v6.2d
; CHECK-i64-SD-NEXT: fcvtl v18.2d, v18.2s
-; CHECK-i64-SD-NEXT: fcvtl v21.2d, v21.2s
-; CHECK-i64-SD-NEXT: frintx v20.2s, v20.2s
+; CHECK-i64-SD-NEXT: fcvtzs v6.2d, v6.2d
+; CHECK-i64-SD-NEXT: fcvtl v19.2d, v19.2s
+; CHECK-i64-SD-NEXT: frintx v1.2s, v1.2s
+; CHECK-i64-SD-NEXT: fcvtl v4.2d, v4.2s
; CHECK-i64-SD-NEXT: fcvtl v3.2d, v3.2s
; CHECK-i64-SD-NEXT: fcvtzs v5.2d, v5.2d
; CHECK-i64-SD-NEXT: frintx v0.2s, v0.2s
; CHECK-i64-SD-NEXT: fcvtl v2.2d, v2.2s
-; CHECK-i64-SD-NEXT: fcvtzs v4.2d, v4.2d
; CHECK-i64-SD-NEXT: fcvtzs v16.2d, v16.2d
; CHECK-i64-SD-NEXT: fcvtzs v17.2d, v17.2d
+; CHECK-i64-SD-NEXT: fcvtzs v4.2d, v4.2d
; CHECK-i64-SD-NEXT: fcvtl v1.2d, v1.2s
; CHECK-i64-SD-NEXT: fcvtzs v3.2d, v3.2d
; CHECK-i64-SD-NEXT: fcvtl v0.2d, v0.2s
; CHECK-i64-SD-NEXT: fcvtzs v2.2d, v2.2d
; CHECK-i64-SD-NEXT: stp q6, q17, [x8, #192]
-; CHECK-i64-SD-NEXT: fcvtl v6.2d, v23.2s
-; CHECK-i64-SD-NEXT: frintx v17.2s, v19.2s
+; CHECK-i64-SD-NEXT: frintx v6.2s, v20.2s
+; CHECK-i64-SD-NEXT: fcvtl v17.2d, v23.2s
; CHECK-i64-SD-NEXT: stp q7, q16, [x8, #224]
-; CHECK-i64-SD-NEXT: frintx v7.2s, v22.2s
+; CHECK-i64-SD-NEXT: fcvtl v7.2d, v22.2s
; CHECK-i64-SD-NEXT: fcvtzs v16.2d, v18.2d
-; CHECK-i64-SD-NEXT: fcvtzs v18.2d, v21.2d
+; CHECK-i64-SD-NEXT: fcvtzs v18.2d, v19.2d
; CHECK-i64-SD-NEXT: fcvtzs v1.2d, v1.2d
; CHECK-i64-SD-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-i64-SD-NEXT: fcvtzs v6.2d, v6.2d
+; CHECK-i64-SD-NEXT: fcvtl v6.2d, v6.2s
; CHECK-i64-SD-NEXT: stp q5, q16, [x8, #160]
-; CHECK-i64-SD-NEXT: fcvtl v7.2d, v7.2s
-; CHECK-i64-SD-NEXT: fcvtl v5.2d, v20.2s
-; CHECK-i64-SD-NEXT: stp q4, q18, [x8, #128]
-; CHECK-i64-SD-NEXT: fcvtl v4.2d, v17.2s
-; CHECK-i64-SD-NEXT: stp q3, q6, [x8, #96]
; CHECK-i64-SD-NEXT: fcvtzs v7.2d, v7.2d
+; CHECK-i64-SD-NEXT: fcvtl v5.2d, v21.2s
+; CHECK-i64-SD-NEXT: stp q4, q18, [x8, #128]
+; CHECK-i64-SD-NEXT: fcvtzs v16.2d, v17.2d
+; CHECK-i64-SD-NEXT: fcvtzs v4.2d, v6.2d
+; CHECK-i64-SD-NEXT: stp q3, q7, [x8, #96]
; CHECK-i64-SD-NEXT: fcvtzs v3.2d, v5.2d
-; CHECK-i64-SD-NEXT: stp q1, q3, [x8, #32]
-; CHECK-i64-SD-NEXT: stp q2, q7, [x8, #64]
-; CHECK-i64-SD-NEXT: fcvtzs v2.2d, v4.2d
-; CHECK-i64-SD-NEXT: stp q0, q2, [x8]
+; CHECK-i64-SD-NEXT: stp q2, q16, [x8, #64]
+; CHECK-i64-SD-NEXT: stp q0, q4, [x8]
+; CHECK-i64-SD-NEXT: stp q3, q1, [x8, #32]
; CHECK-i64-SD-NEXT: ret
;
; CHECK-i64-GI-LABEL: lrint_v32f32:
diff --git a/llvm/test/CodeGen/AArch64/vselect-ext.ll b/llvm/test/CodeGen/AArch64/vselect-ext.ll
index 4f2b9c5a62669..5ed427110ea2f 100644
--- a/llvm/test/CodeGen/AArch64/vselect-ext.ll
+++ b/llvm/test/CodeGen/AArch64/vselect-ext.ll
@@ -516,14 +516,14 @@ define <16 x i32> @same_sext_used_in_cmp_unsigned_pred_and_select(<16 x i8> %a)
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: movi.16b v1, #10
; CHECK-NEXT: sshll.8h v2, v0, #0
-; CHECK-NEXT: ext.16b v4, v2, v2, #8
+; CHECK-NEXT: mov d4, v2[1]
; CHECK-NEXT: cmhi.16b v1, v0, v1
; CHECK-NEXT: sshll2.8h v0, v0, #0
; CHECK-NEXT: sshll.8h v3, v1, #0
; CHECK-NEXT: sshll2.8h v1, v1, #0
-; CHECK-NEXT: ext.16b v5, v0, v0, #8
-; CHECK-NEXT: ext.16b v6, v3, v3, #8
-; CHECK-NEXT: ext.16b v7, v1, v1, #8
+; CHECK-NEXT: mov d5, v0[1]
+; CHECK-NEXT: mov d6, v3[1]
+; CHECK-NEXT: mov d7, v1[1]
; CHECK-NEXT: and.8b v2, v3, v2
; CHECK-NEXT: and.8b v1, v1, v0
; CHECK-NEXT: sshll.4s v0, v2, #0
diff --git a/llvm/test/CodeGen/AArch64/zext-shuffle.ll b/llvm/test/CodeGen/AArch64/zext-shuffle.ll
index f3db88af0787c..cf917341f18b0 100644
--- a/llvm/test/CodeGen/AArch64/zext-shuffle.ll
+++ b/llvm/test/CodeGen/AArch64/zext-shuffle.ll
@@ -4,7 +4,7 @@
define <2 x i64> @v2i64_02(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: v2i64_02:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: zip1 v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ushll v0.2d, v0.2s, #0
; CHECK-NEXT: ret
@@ -16,7 +16,7 @@ define <2 x i64> @v2i64_02(<4 x i32> %a, <4 x i32> %b) {
define <2 x i64> @v2i64_13(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: v2i64_13:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: zip2 v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ushll v0.2d, v0.2s, #0
; CHECK-NEXT: ret
@@ -50,8 +50,8 @@ define <2 x i64> @v2i64_15913(<4 x i32> %a, <4 x i32> %b) {
define <2 x i64> @v2i64_261014(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: v2i64_261014:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v1.d[1]
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: zip1 v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ushll v0.2d, v0.2s, #0
; CHECK-NEXT: ret
@@ -63,8 +63,8 @@ define <2 x i64> @v2i64_261014(<4 x i32> %a, <4 x i32> %b) {
define <2 x i64> @v2i64_37(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: v2i64_37:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: mov d1, v1.d[1]
+; CHECK-NEXT: mov d0, v0.d[1]
; CHECK-NEXT: zip2 v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ushll v0.2d, v0.2s, #0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/zext-to-tbl.ll b/llvm/test/CodeGen/AArch64/zext-to-tbl.ll
index a4caf0e8068d4..26c814ba4f621 100644
--- a/llvm/test/CodeGen/AArch64/zext-to-tbl.ll
+++ b/llvm/test/CodeGen/AArch64/zext-to-tbl.ll
@@ -1717,7 +1717,7 @@ define void @zext_v8i8_to_v8i64_with_add_in_sequence_in_loop(ptr %src, ptr %dst)
; CHECK-BE-NEXT: sub x11, x9, #64
; CHECK-BE-NEXT: sub x12, x9, #32
; CHECK-BE-NEXT: ld1 { v6.2d }, [x9]
-; CHECK-BE-NEXT: ld1 { v21.2d }, [x11]
+; CHECK-BE-NEXT: ld1 { v22.2d }, [x11]
; CHECK-BE-NEXT: tbl v4.16b, { v2.16b }, v1.16b
; CHECK-BE-NEXT: tbl v2.16b, { v2.16b }, v0.16b
; CHECK-BE-NEXT: ld1 { v19.2d }, [x12]
@@ -1727,15 +1727,15 @@ define void @zext_v8i8_to_v8i64_with_add_in_sequence_in_loop(ptr %src, ptr %dst)
; CHECK-BE-NEXT: sub x14, x9, #48
; CHECK-BE-NEXT: add x16, x9, #48
; CHECK-BE-NEXT: add x17, x9, #16
-; CHECK-BE-NEXT: ld1 { v22.2d }, [x13]
+; CHECK-BE-NEXT: ld1 { v21.2d }, [x13]
; CHECK-BE-NEXT: subs x8, x8, #16
; CHECK-BE-NEXT: add x10, x10, #16
; CHECK-BE-NEXT: rev32 v7.8b, v4.8b
-; CHECK-BE-NEXT: ext v4.16b, v4.16b, v4.16b, #8
+; CHECK-BE-NEXT: mov d4, v4.d[1]
; CHECK-BE-NEXT: rev32 v17.8b, v2.8b
-; CHECK-BE-NEXT: ext v18.16b, v5.16b, v5.16b, #8
-; CHECK-BE-NEXT: ext v20.16b, v3.16b, v3.16b, #8
-; CHECK-BE-NEXT: ext v2.16b, v2.16b, v2.16b, #8
+; CHECK-BE-NEXT: mov d18, v5.d[1]
+; CHECK-BE-NEXT: mov d20, v3.d[1]
+; CHECK-BE-NEXT: mov d2, v2.d[1]
; CHECK-BE-NEXT: rev32 v5.8b, v5.8b
; CHECK-BE-NEXT: rev32 v3.8b, v3.8b
; CHECK-BE-NEXT: uaddw v7.2d, v16.2d, v7.2s
@@ -1747,14 +1747,14 @@ define void @zext_v8i8_to_v8i64_with_add_in_sequence_in_loop(ptr %src, ptr %dst)
; CHECK-BE-NEXT: ld1 { v16.2d }, [x16]
; CHECK-BE-NEXT: ld1 { v18.2d }, [x14]
; CHECK-BE-NEXT: uaddw v5.2d, v19.2d, v5.2s
-; CHECK-BE-NEXT: uaddw v3.2d, v21.2d, v3.2s
+; CHECK-BE-NEXT: uaddw v3.2d, v22.2d, v3.2s
; CHECK-BE-NEXT: st1 { v7.2d }, [x15]
; CHECK-BE-NEXT: ld1 { v7.2d }, [x17]
; CHECK-BE-NEXT: st1 { v6.2d }, [x9]
; CHECK-BE-NEXT: add x9, x9, #128
; CHECK-BE-NEXT: uaddw v4.2d, v16.2d, v4.2s
; CHECK-BE-NEXT: st1 { v5.2d }, [x12]
-; CHECK-BE-NEXT: uaddw v5.2d, v22.2d, v17.2s
+; CHECK-BE-NEXT: uaddw v5.2d, v21.2d, v17.2s
; CHECK-BE-NEXT: st1 { v3.2d }, [x11]
; CHECK-BE-NEXT: uaddw v3.2d, v18.2d, v20.2s
; CHECK-BE-NEXT: uaddw v2.2d, v7.2d, v2.2s
@@ -2960,27 +2960,27 @@ define i32 @test_widening_instr_mull_64(ptr %p1, ptr %p2, i32 %h) {
; CHECK-BE-NEXT: tbl v6.16b, { v4.16b }, v2.16b
; CHECK-BE-NEXT: tbl v7.16b, { v4.16b }, v1.16b
; CHECK-BE-NEXT: tbl v4.16b, { v4.16b }, v0.16b
-; CHECK-BE-NEXT: ext v24.16b, v18.16b, v18.16b, #8
+; CHECK-BE-NEXT: mov d24, v18.d[1]
; CHECK-BE-NEXT: add x9, x0, #32
-; CHECK-BE-NEXT: ext v25.16b, v20.16b, v20.16b, #8
+; CHECK-BE-NEXT: mov d25, v20.d[1]
; CHECK-BE-NEXT: add x10, x0, #16
; CHECK-BE-NEXT: subs w2, w2, #1
-; CHECK-BE-NEXT: ext v17.16b, v5.16b, v5.16b, #8
-; CHECK-BE-NEXT: ext v19.16b, v6.16b, v6.16b, #8
+; CHECK-BE-NEXT: mov d17, v5.d[1]
+; CHECK-BE-NEXT: mov d19, v6.d[1]
; CHECK-BE-NEXT: rev32 v5.8b, v5.8b
; CHECK-BE-NEXT: rev32 v21.8b, v7.8b
+; CHECK-BE-NEXT: mov d7, v7.d[1]
; CHECK-BE-NEXT: rev32 v23.8b, v4.8b
-; CHECK-BE-NEXT: ext v7.16b, v7.16b, v7.16b, #8
-; CHECK-BE-NEXT: ext v4.16b, v4.16b, v4.16b, #8
+; CHECK-BE-NEXT: mov d4, v4.d[1]
; CHECK-BE-NEXT: rev32 v6.8b, v6.8b
; CHECK-BE-NEXT: rev32 v17.8b, v17.8b
; CHECK-BE-NEXT: rev32 v19.8b, v19.8b
; CHECK-BE-NEXT: umull v5.2d, v5.2s, v18.2s
; CHECK-BE-NEXT: umull v18.2d, v21.2s, v22.2s
-; CHECK-BE-NEXT: ext v21.16b, v22.16b, v22.16b, #8
+; CHECK-BE-NEXT: mov d21, v22.d[1]
; CHECK-BE-NEXT: rev32 v7.8b, v7.8b
; CHECK-BE-NEXT: umull v22.2d, v23.2s, v16.2s
-; CHECK-BE-NEXT: ext v16.16b, v16.16b, v16.16b, #8
+; CHECK-BE-NEXT: mov d16, v16.d[1]
; CHECK-BE-NEXT: rev32 v4.8b, v4.8b
; CHECK-BE-NEXT: umull v17.2d, v17.2s, v24.2s
; CHECK-BE-NEXT: umull v19.2d, v19.2s, v25.2s
diff --git a/llvm/test/CodeGen/AArch64/zext.ll b/llvm/test/CodeGen/AArch64/zext.ll
index 292b7b28903ee..9ec760aa57e27 100644
--- a/llvm/test/CodeGen/AArch64/zext.ll
+++ b/llvm/test/CodeGen/AArch64/zext.ll
@@ -292,9 +292,8 @@ define <3 x i64> @zext_v3i8_v3i64(<3 x i8> %a) {
; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-SD-NEXT: ushll v1.2d, v3.2s, #0
; CHECK-SD-NEXT: mov v2.b[0], v1.b[0]
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-SD-NEXT: ret
;
@@ -344,9 +343,8 @@ define <3 x i64> @zext_v3i16_v3i64(<3 x i16> %a) {
; CHECK-SD-NEXT: ushll v0.2d, v2.2s, #0
; CHECK-SD-NEXT: ushll2 v2.2d, v2.4s, #0
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: zext_v3i16_v3i64:
@@ -370,9 +368,8 @@ define <3 x i64> @zext_v3i32_v3i64(<3 x i32> %a) {
; CHECK-SD-NEXT: ushll v3.2d, v0.2s, #0
; CHECK-SD-NEXT: ushll2 v2.2d, v0.4s, #0
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-SD-NEXT: mov d1, v3.d[1]
; CHECK-SD-NEXT: fmov d0, d3
-; CHECK-SD-NEXT: ext v1.16b, v3.16b, v3.16b, #8
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: zext_v3i32_v3i64:
@@ -443,17 +440,16 @@ define <3 x i64> @zext_v3i10_v3i64(<3 x i10> %a) {
; CHECK-SD-LABEL: zext_v3i10_v3i64:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: fmov s0, w0
-; CHECK-SD-NEXT: fmov s1, w2
; CHECK-SD-NEXT: mov w8, #1023 // =0x3ff
+; CHECK-SD-NEXT: fmov s1, w2
; CHECK-SD-NEXT: dup v2.2d, x8
; CHECK-SD-NEXT: mov v0.s[1], w1
; CHECK-SD-NEXT: zip1 v3.2s, v1.2s, v1.2s
; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #0
; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b
; CHECK-SD-NEXT: and v2.8b, v3.8b, v2.8b
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: zext_v3i10_v3i64:
More information about the llvm-commits
mailing list