[llvm] [DAG] Support soft half promotion of insert_vector_elt (PR #194994)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index 9467f6406..10150e72f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -3199,7 +3199,8 @@ bool DAGTypeLegalizer::SoftPromoteHalfOperand(SDNode *N, unsigned OpNo) {
   case ISD::SELECT_CC:  Res = SoftPromoteHalfOp_SELECT_CC(N, OpNo); break;
   case ISD::SETCC:      Res = SoftPromoteHalfOp_SETCC(N); break;
   case ISD::INSERT_VECTOR_ELT:
-    Res = SoftPromoteHalfOp_INSERT_VECTOR_ELT(N); break;
+    Res = SoftPromoteHalfOp_INSERT_VECTOR_ELT(N);
+    break;
   case ISD::STORE:      Res = SoftPromoteHalfOp_STORE(N, OpNo); break;
   case ISD::ATOMIC_STORE:
     Res = SoftPromoteHalfOp_ATOMIC_STORE(N, OpNo);
@@ -3356,9 +3357,9 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfOp_SETCC(SDNode *N) {
 SDValue DAGTypeLegalizer::SoftPromoteHalfOp_INSERT_VECTOR_ELT(SDNode *N) {
   SDValue NewVec = BitConvertVectorToIntegerVector(N->getOperand(0));
   SDValue NewElt = GetSoftPromotedHalf(N->getOperand(1));
-  SDValue NewIns = DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
-                               NewVec.getValueType(), NewVec, NewElt,
-                               N->getOperand(2));
+  SDValue NewIns =
+      DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), NewVec.getValueType(),
+                  NewVec, NewElt, N->getOperand(2));
   return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0), NewIns);
 }
 

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https://github.com/llvm/llvm-project/pull/194994