[llvm] [X86][AVX10.2] Skip select-minmax fusion for BF16 (PR #194987)
Akhil Goel via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 29 17:33:56 PDT 2026
https://github.com/akhilgoe created https://github.com/llvm/llvm-project/pull/194987
This PR disables the select-compare fusion for BF16. This is necessary because the combine pass generates `X86ISD::FMIN/FMAX` nodes which lack the necessary selection support for `bf16` types, resulting in selection failure.
>From 0ab07a3fb81ed9af9287f9d37497519520dfef78 Mon Sep 17 00:00:00 2001
From: Akhil Goel <akhil.goel at intel.com>
Date: Thu, 30 Apr 2026 00:13:54 +0000
Subject: [PATCH] Return early for avx10.2 bf16 select minmax
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 3 +-
.../X86/avx10_2bf16-fp16-select-minmax.ll | 135 ++++++++++++++++++
2 files changed, 137 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/X86/avx10_2bf16-fp16-select-minmax.ll
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index c2d99a3d2b226..53903bf14f307 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -48455,7 +48455,8 @@ static SDValue combineSelectToMinMax(SelectionDAG &DAG,
if ((Cond.getOpcode() != ISD::SETCC &&
Cond.getOpcode() != ISD::STRICT_FSETCCS) ||
!VT.isFloatingPoint() || VT == MVT::f80 || VT == MVT::f128 ||
- isSoftF16(VT, Subtarget) || (!TLI.isTypeLegal(VT) && VT != MVT::v2f32) ||
+ isBF16orSoftF16(VT, Subtarget) ||
+ (!TLI.isTypeLegal(VT) && VT != MVT::v2f32) ||
((VT == MVT::v8f16 || VT == MVT::v16f16) && !Subtarget.hasVLX()) ||
(!Subtarget.hasSSE2() &&
(!Subtarget.hasSSE1() || VT.getScalarType() != MVT::f32)))
diff --git a/llvm/test/CodeGen/X86/avx10_2bf16-fp16-select-minmax.ll b/llvm/test/CodeGen/X86/avx10_2bf16-fp16-select-minmax.ll
new file mode 100644
index 0000000000000..3d476fd46e156
--- /dev/null
+++ b/llvm/test/CodeGen/X86/avx10_2bf16-fp16-select-minmax.ll
@@ -0,0 +1,135 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.1 | FileCheck %s --check-prefixes=CHECK,AVX10_1
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,AVX10_2
+
+define bfloat @select_ogt_bf16(bfloat %a, bfloat %b) {
+; CHECK-LABEL: select_ogt_bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmovw %xmm0, %eax
+; CHECK-NEXT: vmovw %xmm1, %ecx
+; CHECK-NEXT: movl %ecx, %edx
+; CHECK-NEXT: shll $16, %edx
+; CHECK-NEXT: vmovd %edx, %xmm0
+; CHECK-NEXT: movl %eax, %edx
+; CHECK-NEXT: shll $16, %edx
+; CHECK-NEXT: vmovd %edx, %xmm1
+; CHECK-NEXT: vucomiss %xmm0, %xmm1
+; CHECK-NEXT: cmoval %eax, %ecx
+; CHECK-NEXT: vmovw %ecx, %xmm0
+; CHECK-NEXT: retq
+ %cmp = fcmp ogt bfloat %a, %b
+ %sel = select i1 %cmp, bfloat %a, bfloat %b
+ ret bfloat %sel
+}
+
+define <8 x bfloat> @select_olt_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) {
+; AVX10_1-LABEL: select_olt_v8bf16:
+; AVX10_1: # %bb.0:
+; AVX10_1-NEXT: vpmovzxwd {{.*#+}} ymm2 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
+; AVX10_1-NEXT: vpslld $16, %ymm2, %ymm2
+; AVX10_1-NEXT: vpmovzxwd {{.*#+}} ymm3 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; AVX10_1-NEXT: vpslld $16, %ymm3, %ymm3
+; AVX10_1-NEXT: vcmpltps %ymm2, %ymm3, %k1
+; AVX10_1-NEXT: vpblendmw %xmm0, %xmm1, %xmm0 {%k1}
+; AVX10_1-NEXT: vzeroupper
+; AVX10_1-NEXT: retq
+;
+; AVX10_2-LABEL: select_olt_v8bf16:
+; AVX10_2: # %bb.0:
+; AVX10_2-NEXT: vcmpltbf16 %xmm1, %xmm0, %k1
+; AVX10_2-NEXT: vpblendmw %xmm0, %xmm1, %xmm0 {%k1}
+; AVX10_2-NEXT: retq
+ %cmp = fcmp olt <8 x bfloat> %a, %b
+ %sel = select <8 x i1> %cmp, <8 x bfloat> %a, <8 x bfloat> %b
+ ret <8 x bfloat> %sel
+}
+
+define <16 x bfloat> @select_ogt_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) {
+; AVX10_1-LABEL: select_ogt_v16bf16:
+; AVX10_1: # %bb.0:
+; AVX10_1-NEXT: vpmovzxwd {{.*#+}} zmm2 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
+; AVX10_1-NEXT: vpslld $16, %zmm2, %zmm2
+; AVX10_1-NEXT: vpmovzxwd {{.*#+}} zmm3 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero
+; AVX10_1-NEXT: vpslld $16, %zmm3, %zmm3
+; AVX10_1-NEXT: vcmpltps %zmm2, %zmm3, %k1
+; AVX10_1-NEXT: vpblendmw %ymm0, %ymm1, %ymm0 {%k1}
+; AVX10_1-NEXT: retq
+;
+; AVX10_2-LABEL: select_ogt_v16bf16:
+; AVX10_2: # %bb.0:
+; AVX10_2-NEXT: vcmpltbf16 %ymm0, %ymm1, %k1
+; AVX10_2-NEXT: vpblendmw %ymm0, %ymm1, %ymm0 {%k1}
+; AVX10_2-NEXT: retq
+ %cmp = fcmp ogt <16 x bfloat> %a, %b
+ %sel = select <16 x i1> %cmp, <16 x bfloat> %a, <16 x bfloat> %b
+ ret <16 x bfloat> %sel
+}
+
+define <32 x bfloat> @select_olt_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) {
+; AVX10_1-LABEL: select_olt_v32bf16:
+; AVX10_1: # %bb.0:
+; AVX10_1-NEXT: vpmovzxwd {{.*#+}} zmm2 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero
+; AVX10_1-NEXT: vpslld $16, %zmm2, %zmm2
+; AVX10_1-NEXT: vpmovzxwd {{.*#+}} zmm3 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
+; AVX10_1-NEXT: vpslld $16, %zmm3, %zmm3
+; AVX10_1-NEXT: vcmpltps %zmm2, %zmm3, %k0
+; AVX10_1-NEXT: vextracti64x4 $1, %zmm1, %ymm2
+; AVX10_1-NEXT: vpmovzxwd {{.*#+}} zmm2 = ymm2[0],zero,ymm2[1],zero,ymm2[2],zero,ymm2[3],zero,ymm2[4],zero,ymm2[5],zero,ymm2[6],zero,ymm2[7],zero,ymm2[8],zero,ymm2[9],zero,ymm2[10],zero,ymm2[11],zero,ymm2[12],zero,ymm2[13],zero,ymm2[14],zero,ymm2[15],zero
+; AVX10_1-NEXT: vpslld $16, %zmm2, %zmm2
+; AVX10_1-NEXT: vextracti64x4 $1, %zmm0, %ymm3
+; AVX10_1-NEXT: vpmovzxwd {{.*#+}} zmm3 = ymm3[0],zero,ymm3[1],zero,ymm3[2],zero,ymm3[3],zero,ymm3[4],zero,ymm3[5],zero,ymm3[6],zero,ymm3[7],zero,ymm3[8],zero,ymm3[9],zero,ymm3[10],zero,ymm3[11],zero,ymm3[12],zero,ymm3[13],zero,ymm3[14],zero,ymm3[15],zero
+; AVX10_1-NEXT: vpslld $16, %zmm3, %zmm3
+; AVX10_1-NEXT: vcmpltps %zmm2, %zmm3, %k1
+; AVX10_1-NEXT: kunpckwd %k0, %k1, %k1
+; AVX10_1-NEXT: vpblendmw %zmm0, %zmm1, %zmm0 {%k1}
+; AVX10_1-NEXT: retq
+;
+; AVX10_2-LABEL: select_olt_v32bf16:
+; AVX10_2: # %bb.0:
+; AVX10_2-NEXT: vcmpltbf16 %zmm1, %zmm0, %k1
+; AVX10_2-NEXT: vpblendmw %zmm0, %zmm1, %zmm0 {%k1}
+; AVX10_2-NEXT: retq
+ %cmp = fcmp olt <32 x bfloat> %a, %b
+ %sel = select <32 x i1> %cmp, <32 x bfloat> %a, <32 x bfloat> %b
+ ret <32 x bfloat> %sel
+}
+
+define half @select_ogt_f16(half %a, half %b) {
+; CHECK-LABEL: select_ogt_f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmaxsh %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: retq
+ %cmp = fcmp ogt half %a, %b
+ %sel = select i1 %cmp, half %a, half %b
+ ret half %sel
+}
+
+define <8 x half> @select_olt_v8f16(<8 x half> %a, <8 x half> %b) {
+; CHECK-LABEL: select_olt_v8f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vminph %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: retq
+ %cmp = fcmp olt <8 x half> %a, %b
+ %sel = select <8 x i1> %cmp, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %sel
+}
+
+define <16 x half> @select_ogt_v16f16(<16 x half> %a, <16 x half> %b) {
+; CHECK-LABEL: select_ogt_v16f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmaxph %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: retq
+ %cmp = fcmp ogt <16 x half> %a, %b
+ %sel = select <16 x i1> %cmp, <16 x half> %a, <16 x half> %b
+ ret <16 x half> %sel
+}
+
+define <32 x half> @select_olt_v32f16(<32 x half> %a, <32 x half> %b) {
+; CHECK-LABEL: select_olt_v32f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vminph %zmm1, %zmm0, %zmm0
+; CHECK-NEXT: retq
+ %cmp = fcmp olt <32 x half> %a, %b
+ %sel = select <32 x i1> %cmp, <32 x half> %a, <32 x half> %b
+ ret <32 x half> %sel
+}
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