[llvm] [ARM] Port CSINC patterns from AArch64 to ARM (PR #194956)

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<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-arm

Author: LumioseSil (LumioseSil)

<details>
<summary>Changes</summary>

This folds (or x, (csinc 0, 0, cc)) -> (csinc x, 0, cc) in TableGen.

And add val, csel(0,1,cc) -> CSINC val,val,cc)

Use add_like for csinc.

---
Full diff: https://github.com/llvm/llvm-project/pull/194956.diff


1 Files Affected:

- (modified) llvm/lib/Target/ARM/ARMInstrThumb2.td (+7-1) 


``````````diff
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td
index e79adb370798e..e05d96e8c3183 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -5819,12 +5819,18 @@ let Predicates = [HasV8_1MMainline] in {
                 (Insn GPRwithZR:$tval, GPRwithZR:$fval,
                          (i32 (inv_cond_XFORM imm:$cc)))>;
   }
-  defm : ModifiedV8_1CSEL<t2CSINC, (add rGPR:$fval, 1)>;
+  defm : ModifiedV8_1CSEL<t2CSINC, (add_like rGPR:$fval, 1)>;
   defm : ModifiedV8_1CSEL<t2CSINV, (xor rGPR:$fval, -1)>;
   defm : ModifiedV8_1CSEL<t2CSNEG, (sub 0, rGPR:$fval)>;
 
   def : T2Pat<(ARMcmov (topbitsallzero32:$Rn), (i32 1), imm:$cc, CPSR),
               (t2CSINC $Rn, ZR, (inv_cond_XFORM imm:$cc))>;
+  def : T2Pat<(add_like rGPR:$Rn,
+                   (ARMcsinc_su (i32 0), (i32 0), imm:$cc, CPSR)),
+              (t2CSINC $Rn, $Rn, imm:$cc)>;
+  def : T2Pat<(or (topbitsallzero32:$Rn),
+                  (ARMcsinc_su (i32 0), (i32 0), imm:$cc, CPSR)),
+              (t2CSINC $Rn, ZR, imm:$cc)>;
   def : T2Pat<(and (topbitsallzero32:$Rn),
                    (ARMcsinc_su (i32 0), (i32 0), imm:$cc, CPSR)),
               (t2CSEL ZR, $Rn, imm:$cc)>;

``````````

</details>


https://github.com/llvm/llvm-project/pull/194956