[llvm] [AMDGPU] Support Wave Reduction for i16 types - 1 (PR #194808)

[Matt Arsenault via llvm-commits]

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@@ -6114,12 +6153,35 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
           IsWave32 ? AMDGPU::S_FF1_I32_B32 : AMDGPU::S_FF1_I32_B64;
       BuildMI(*ComputeLoop, I, DL, TII->get(SFFOpc), FF1Reg)
           .addReg(ActiveBitsReg);
-      if (is32BitOpc) {
+      if (is32BitOpc || is16BitOpc) {
         BuildMI(*ComputeLoop, I, DL, TII->get(AMDGPU::V_READLANE_B32),
                 LaneValueReg)
             .addReg(SrcReg)
             .addReg(FF1Reg);
-        if (isFPOp) {
+        if (is16BitOpc) {
+          Register LaneValVgpr = MRI.createVirtualRegister(SrcRegClass);
+          Register VgprResultReg = MRI.createVirtualRegister(SrcRegClass);
+          bool isGFX10 = ST.getGeneration() == AMDGPUSubtarget::GFX10;
+          // Get the Lane Value in VGPR to avoid the Constant Bus Restriction
+          BuildMI(*ComputeLoop, I, DL, TII->get(AMDGPU::COPY), LaneValVgpr)
+              .addReg(LaneValueReg);
+          auto OpInstr =
+              BuildMI(*ComputeLoop, I, DL, TII->get(Opc), VgprResultReg);
+          if (isGFX10)
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arsenm wrote:

Should not be a generation check

https://github.com/llvm/llvm-project/pull/194808