[llvm] [RISCV] Remove codegen for vp_trunc (PR #194886)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 29 08:37:59 PDT 2026
https://github.com/lukel97 updated https://github.com/llvm/llvm-project/pull/194886
>From d0ec742a77ae78bc20ffa2ba0616699363dfbf3d Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Sun, 26 Apr 2026 22:47:08 -0700
Subject: [PATCH 1/2] [RISCV] Remove codegen for vp_trunc
Part of the work to remove trivial VP intrinsics from the RISC-V backend, see https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999
This splits off vp_truncate from #179622.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 132 +--
llvm/lib/Target/RISCV/RISCVISelLowering.h | 4 +-
.../Target/RISCV/RISCVTargetTransformInfo.h | 1 -
.../RISCV/rvv/fixed-vectors-trunc-vp-mask.ll | 24 +-
.../RISCV/rvv/fixed-vectors-trunc-vp.ll | 835 ++++--------------
llvm/test/CodeGen/RISCV/rvv/pr141907.ll | 5 +-
.../RISCV/rvv/rvv-peephole-vmerge-vops.ll | 2 +-
llvm/test/CodeGen/RISCV/rvv/vnsra-vp.ll | 18 +-
llvm/test/CodeGen/RISCV/rvv/vnsrl-vp.ll | 18 +-
llvm/test/CodeGen/RISCV/rvv/vp-vaaddu.ll | 49 +-
llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll | 14 +-
llvm/test/CodeGen/RISCV/rvv/vtrunc-vp-mask.ll | 25 +-
llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll | 215 ++---
13 files changed, 281 insertions(+), 1061 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index a896ba637059c..eb0bc24a48af8 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -873,7 +873,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::VP_REDUCE_OR, ISD::VP_REDUCE_XOR, ISD::VP_REDUCE_SMAX,
ISD::VP_REDUCE_SMIN, ISD::VP_REDUCE_UMAX, ISD::VP_REDUCE_UMIN,
ISD::VP_MERGE,
- ISD::VP_TRUNCATE,
ISD::EXPERIMENTAL_VP_REVERSE, ISD::EXPERIMENTAL_VP_SPLICE,
ISD::VP_CTTZ_ELTS, ISD::VP_CTTZ_ELTS_ZERO_UNDEF};
@@ -964,8 +963,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
OtherVT, Expand);
}
- setOperationAction(ISD::VP_TRUNCATE, VT, Custom);
-
setOperationAction(ISD::VECTOR_DEINTERLEAVE, VT, Custom);
setOperationAction(ISD::VECTOR_INTERLEAVE, VT, Custom);
@@ -1523,8 +1520,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::OR, ISD::XOR},
VT, Custom);
- setOperationAction(ISD::VP_TRUNCATE, VT, Custom);
-
setOperationAction(ISD::VP_MERGE, VT, Custom);
setOperationAction(ISD::EXPERIMENTAL_VP_SPLICE, VT, Custom);
@@ -1886,7 +1881,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::BUILD_VECTOR,
ISD::CONCAT_VECTORS,
ISD::VP_STORE,
- ISD::VP_TRUNCATE,
ISD::EXPERIMENTAL_VP_REVERSE,
ISD::SDIV,
ISD::UDIV,
@@ -7890,7 +7884,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
// Only custom-lower vector truncates
if (!Op.getSimpleValueType().isVector())
return Op;
- return lowerVectorTruncLike(Op, DAG);
+ return lowerVectorTrunc(Op, DAG);
case ISD::ANY_EXTEND:
case ISD::ZERO_EXTEND:
if (Op.getOperand(0).getValueType().isVector() &&
@@ -8957,8 +8951,6 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
case ISD::VP_SRL:
case ISD::VP_SHL:
return lowerVPOp(Op, DAG);
- case ISD::VP_TRUNCATE:
- return lowerVectorTruncLike(Op, DAG);
case ISD::EXPERIMENTAL_VP_STRIDED_LOAD:
return lowerVPStridedLoad(Op, DAG);
case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
@@ -10413,9 +10405,8 @@ SDValue RISCVTargetLowering::lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
// Custom-lower truncations from vectors to mask vectors by using a mask and a
// setcc operation:
// (vXi1 = trunc vXiN vec) -> (vXi1 = setcc (and vec, 1), 0, ne)
-SDValue RISCVTargetLowering::lowerVectorMaskTruncLike(SDValue Op,
+SDValue RISCVTargetLowering::lowerVectorMaskTrunc(SDValue Op,
SelectionDAG &DAG) const {
- bool IsVPTrunc = Op.getOpcode() == ISD::VP_TRUNCATE;
SDLoc DL(Op);
EVT MaskVT = Op.getValueType();
// Only expect to custom-lower truncations to mask types
@@ -10423,28 +10414,15 @@ SDValue RISCVTargetLowering::lowerVectorMaskTruncLike(SDValue Op,
"Unexpected type for vector mask lowering");
SDValue Src = Op.getOperand(0);
MVT VecVT = Src.getSimpleValueType();
- SDValue Mask, VL;
- if (IsVPTrunc) {
- Mask = Op.getOperand(1);
- VL = Op.getOperand(2);
- }
// If this is a fixed vector, we need to convert it to a scalable vector.
MVT ContainerVT = VecVT;
if (VecVT.isFixedLengthVector()) {
ContainerVT = getContainerForFixedLengthVector(VecVT);
Src = convertToScalableVector(ContainerVT, Src, DAG, Subtarget);
- if (IsVPTrunc) {
- MVT MaskContainerVT =
- getContainerForFixedLengthVector(Mask.getSimpleValueType());
- Mask = convertToScalableVector(MaskContainerVT, Mask, DAG, Subtarget);
- }
}
- if (!IsVPTrunc) {
- std::tie(Mask, VL) =
- getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget);
- }
+ auto [Mask, VL] = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget);
SDValue SplatOne = DAG.getConstant(1, DL, Subtarget.getXLenVT());
SDValue SplatZero = DAG.getConstant(0, DL, Subtarget.getXLenVT());
@@ -10465,10 +10443,9 @@ SDValue RISCVTargetLowering::lowerVectorMaskTruncLike(SDValue Op,
return Trunc;
}
-SDValue RISCVTargetLowering::lowerVectorTruncLike(SDValue Op,
+SDValue RISCVTargetLowering::lowerVectorTrunc(SDValue Op,
SelectionDAG &DAG) const {
unsigned Opc = Op.getOpcode();
- bool IsVPTrunc = Opc == ISD::VP_TRUNCATE;
SDLoc DL(Op);
MVT VT = Op.getSimpleValueType();
@@ -10477,7 +10454,7 @@ SDValue RISCVTargetLowering::lowerVectorTruncLike(SDValue Op,
// Truncates to mask types are handled differently
if (VT.getVectorElementType() == MVT::i1)
- return lowerVectorMaskTruncLike(Op, DAG);
+ return lowerVectorMaskTrunc(Op, DAG);
// RVV only has truncates which operate from SEW*2->SEW, so lower arbitrary
// truncates as a series of "RISCVISD::TRUNCATE_VECTOR_VL" nodes which
@@ -10493,25 +10470,13 @@ SDValue RISCVTargetLowering::lowerVectorTruncLike(SDValue Op,
"Unexpected vector truncate lowering");
MVT ContainerVT = SrcVT;
- SDValue Mask, VL;
- if (IsVPTrunc) {
- Mask = Op.getOperand(1);
- VL = Op.getOperand(2);
- }
if (SrcVT.isFixedLengthVector()) {
ContainerVT = getContainerForFixedLengthVector(SrcVT);
Src = convertToScalableVector(ContainerVT, Src, DAG, Subtarget);
- if (IsVPTrunc) {
- MVT MaskVT = getMaskTypeFor(ContainerVT);
- Mask = convertToScalableVector(MaskVT, Mask, DAG, Subtarget);
- }
}
SDValue Result = Src;
- if (!IsVPTrunc) {
- std::tie(Mask, VL) =
- getDefaultVLOps(SrcVT, ContainerVT, DL, DAG, Subtarget);
- }
+ auto [Mask, VL] = getDefaultVLOps(SrcVT, ContainerVT, DL, DAG, Subtarget);
unsigned NewOpc;
if (Opc == ISD::TRUNCATE_SSAT_S)
@@ -19216,89 +19181,6 @@ static SDValue performVP_STORECombine(SDNode *N, SelectionDAG &DAG,
VPStore->isTruncatingStore(), VPStore->isCompressingStore());
}
-// Peephole avgceil pattern.
-// %1 = zext <N x i8> %a to <N x i32>
-// %2 = zext <N x i8> %b to <N x i32>
-// %3 = add nuw nsw <N x i32> %1, splat (i32 1)
-// %4 = add nuw nsw <N x i32> %3, %2
-// %5 = lshr <N x i32> %4, splat (i32 1)
-// %6 = trunc <N x i32> %5 to <N x i8>
-static SDValue performVP_TRUNCATECombine(SDNode *N, SelectionDAG &DAG,
- const RISCVSubtarget &Subtarget) {
- EVT VT = N->getValueType(0);
-
- // Ignore fixed vectors.
- const TargetLowering &TLI = DAG.getTargetLoweringInfo();
- if (!VT.isScalableVector() || !TLI.isTypeLegal(VT))
- return SDValue();
-
- SDValue In = N->getOperand(0);
- SDValue Mask = N->getOperand(1);
- SDValue VL = N->getOperand(2);
-
- // Input should be a srl.
- if (In.getOpcode() != ISD::SRL)
- return SDValue();
-
- // Shift amount should be 1.
- if (!isOneOrOneSplat(In.getOperand(1)))
- return SDValue();
-
- // Shifted value should be an add.
- SDValue LHS = In.getOperand(0);
- if (LHS.getOpcode() != ISD::ADD)
- return SDValue();
-
- SDValue Operands[3];
-
- // Matches another add.
- auto FindAdd = [&](SDValue V, SDValue Other) {
- if (V.getOpcode() != ISD::ADD)
- return false;
-
- Operands[0] = Other;
- Operands[1] = V.getOperand(1);
- Operands[2] = V.getOperand(0);
- return true;
- };
-
- // We need to find another add in one of the operands.
- SDValue LHS0 = LHS.getOperand(0);
- SDValue LHS1 = LHS.getOperand(1);
- if (!FindAdd(LHS0, LHS1) && !FindAdd(LHS1, LHS0))
- return SDValue();
-
- // Now we have three operands of two additions. Check that one of them is a
- // constant vector with ones.
- auto I = llvm::find_if(Operands,
- [](const SDValue &Op) { return isOneOrOneSplat(Op); });
- if (I == std::end(Operands))
- return SDValue();
- // We found a vector with ones, move if it to the end of the Operands array.
- std::swap(*I, Operands[2]);
-
- // Make sure the other 2 operands can be promoted from the result type.
- for (SDValue Op : drop_end(Operands)) {
- if (Op.getOpcode() != ISD::ZERO_EXTEND)
- return SDValue();
- // Input must be the same size or smaller than our result.
- if (Op.getOperand(0).getScalarValueSizeInBits() > VT.getScalarSizeInBits())
- return SDValue();
- }
-
- // Pattern is detected.
- // Rebuild the zero extends in case the inputs are smaller than our result.
- SDValue NewOp0 = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(Operands[0]), VT,
- Operands[0].getOperand(0));
- SDValue NewOp1 = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(Operands[1]), VT,
- Operands[1].getOperand(0));
- // Build a AVGCEILU_VL which will be selected as a VAADDU with RNU rounding
- // mode.
- SDLoc DL(N);
- return DAG.getNode(RISCVISD::AVGCEILU_VL, DL, VT,
- {NewOp0, NewOp1, DAG.getUNDEF(VT), Mask, VL});
-}
-
// Convert from one FMA opcode to another based on whether we are negating the
// multiply result and/or the accumulator.
// NOTE: Only supports RVV operations with VL.
@@ -21498,8 +21380,6 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
if (SDValue V = combineTruncOfSraSext(N, DAG))
return V;
return combineTruncToVnclip(N, DAG, Subtarget);
- case ISD::VP_TRUNCATE:
- return performVP_TRUNCATECombine(N, DAG, Subtarget);
case ISD::TRUNCATE:
return performTRUNCATECombine(N, DAG, Subtarget);
case ISD::SELECT:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index b9229782e120f..a39c0f76c3b79 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -504,8 +504,8 @@ class RISCVTargetLowering : public TargetLowering {
SDValue lowerVectorMaskSplat(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
int64_t ExtTrueVal) const;
- SDValue lowerVectorMaskTruncLike(SDValue Op, SelectionDAG &DAG) const;
- SDValue lowerVectorTruncLike(SDValue Op, SelectionDAG &DAG) const;
+ SDValue lowerVectorMaskTrunc(SDValue Op, SelectionDAG &DAG) const;
+ SDValue lowerVectorTrunc(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerVectorFPExtendOrRound(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index 8b76ca6829949..477c419228a6b 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -398,7 +398,6 @@ class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
Intrinsic::vp_sdiv,
Intrinsic::vp_srem,
Intrinsic::vp_store,
- Intrinsic::vp_trunc,
Intrinsic::vp_udiv,
Intrinsic::vp_urem};
if (!ST->hasVInstructions() ||
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp-mask.ll
index 05ac11d1ca9d7..92b6614bed438 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp-mask.ll
@@ -5,9 +5,9 @@
define <2 x i1> @vtrunc_v2i1_v2i16(<2 x i16> %a, <2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i1_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vand.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%v = call <2 x i1> @llvm.vp.trunc.v2i1.v2i16(<2 x i16> %a, <2 x i1> %m, i32 %vl)
ret <2 x i1> %v
@@ -16,7 +16,7 @@ define <2 x i1> @vtrunc_v2i1_v2i16(<2 x i16> %a, <2 x i1> %m, i32 zeroext %vl) {
define <2 x i1> @vtrunc_v2i1_v2i16_unmasked(<2 x i16> %a, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i1_v2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
@@ -27,9 +27,9 @@ define <2 x i1> @vtrunc_v2i1_v2i16_unmasked(<2 x i16> %a, i32 zeroext %vl) {
define <2 x i1> @vtrunc_v2i1_v2i32(<2 x i32> %a, <2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i1_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vand.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%v = call <2 x i1> @llvm.vp.trunc.v2i1.v2i32(<2 x i32> %a, <2 x i1> %m, i32 %vl)
ret <2 x i1> %v
@@ -38,7 +38,7 @@ define <2 x i1> @vtrunc_v2i1_v2i32(<2 x i32> %a, <2 x i1> %m, i32 zeroext %vl) {
define <2 x i1> @vtrunc_v2i1_v2i32_unmasked(<2 x i32> %a, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i1_v2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
@@ -49,9 +49,9 @@ define <2 x i1> @vtrunc_v2i1_v2i32_unmasked(<2 x i32> %a, i32 zeroext %vl) {
define <2 x i1> @vtrunc_v2i1_v2i64(<2 x i64> %a, <2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i1_v2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vand.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%v = call <2 x i1> @llvm.vp.trunc.v2i1.v2i64(<2 x i64> %a, <2 x i1> %m, i32 %vl)
ret <2 x i1> %v
@@ -60,7 +60,7 @@ define <2 x i1> @vtrunc_v2i1_v2i64(<2 x i64> %a, <2 x i1> %m, i32 zeroext %vl) {
define <2 x i1> @vtrunc_v2i1_v2i64_unmasked(<2 x i64> %a, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i1_v2i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
index f992d1f8f7eee..d726fd0061f07 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
@@ -5,8 +5,8 @@
define <2 x i7> @vtrunc_v2i7_v2i16(<2 x i16> %a, <2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i7_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = call <2 x i7> @llvm.vp.trunc.v2i7.v2i16(<2 x i16> %a, <2 x i1> %m, i32 %vl)
ret <2 x i7> %v
@@ -15,8 +15,8 @@ define <2 x i7> @vtrunc_v2i7_v2i16(<2 x i16> %a, <2 x i1> %m, i32 zeroext %vl) {
define <2 x i8> @vtrunc_v2i8_v2i15(<2 x i15> %a, <2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i8_v2i15:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i15(<2 x i15> %a, <2 x i1> %m, i32 %vl)
ret <2 x i8> %v
@@ -25,8 +25,8 @@ define <2 x i8> @vtrunc_v2i8_v2i15(<2 x i15> %a, <2 x i1> %m, i32 zeroext %vl) {
define <2 x i8> @vtrunc_v2i8_v2i16(<2 x i16> %a, <2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i8_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i16(<2 x i16> %a, <2 x i1> %m, i32 %vl)
ret <2 x i8> %v
@@ -35,7 +35,7 @@ define <2 x i8> @vtrunc_v2i8_v2i16(<2 x i16> %a, <2 x i1> %m, i32 zeroext %vl) {
define <2 x i8> @vtrunc_v2i8_v2i16_unmasked(<2 x i16> %a, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i8_v2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i16(<2 x i16> %a, <2 x i1> <i1 true, i1 true>, i32 %vl)
@@ -45,27 +45,14 @@ define <2 x i8> @vtrunc_v2i8_v2i16_unmasked(<2 x i16> %a, i32 zeroext %vl) {
define <128 x i7> @vtrunc_v128i7_v128i16(<128 x i16> %a, <128 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v128i7_v128i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; CHECK-NEXT: vmv8r.v v24, v8
-; CHECK-NEXT: li a1, 64
-; CHECK-NEXT: vslidedown.vi v12, v0, 8
-; CHECK-NEXT: mv a2, a0
-; CHECK-NEXT: bltu a0, a1, .LBB4_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a2, 64
-; CHECK-NEXT: .LBB4_2:
-; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v24, 0, v0.t
-; CHECK-NEXT: addi a2, a0, -64
-; CHECK-NEXT: sltu a0, a0, a2
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a0, a0, a2
-; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: li a0, 64
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t
-; CHECK-NEXT: li a0, 128
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v24, a1
+; CHECK-NEXT: vnsrl.wi v24, v16, 0
+; CHECK-NEXT: vnsrl.wi v16, v8, 0
+; CHECK-NEXT: li a1, 128
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT: vslideup.vx v16, v24, a0
+; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
%v = call <128 x i7> @llvm.vp.trunc.v128i7.v128i16(<128 x i16> %a, <128 x i1> %m, i32 %vl)
ret <128 x i7> %v
@@ -74,10 +61,10 @@ define <128 x i7> @vtrunc_v128i7_v128i16(<128 x i16> %a, <128 x i1> %m, i32 zero
define <2 x i8> @vtrunc_v2i8_v2i32(<2 x i32> %a, <2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i8_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i32(<2 x i32> %a, <2 x i1> %m, i32 %vl)
ret <2 x i8> %v
@@ -86,7 +73,7 @@ define <2 x i8> @vtrunc_v2i8_v2i32(<2 x i32> %a, <2 x i1> %m, i32 zeroext %vl) {
define <2 x i8> @vtrunc_v2i8_v2i32_unmasked(<2 x i32> %a, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i8_v2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
@@ -98,12 +85,12 @@ define <2 x i8> @vtrunc_v2i8_v2i32_unmasked(<2 x i32> %a, i32 zeroext %vl) {
define <2 x i8> @vtrunc_v2i8_v2i64(<2 x i64> %a, <2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i8_v2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i64(<2 x i64> %a, <2 x i1> %m, i32 %vl)
ret <2 x i8> %v
@@ -112,7 +99,7 @@ define <2 x i8> @vtrunc_v2i8_v2i64(<2 x i64> %a, <2 x i1> %m, i32 zeroext %vl) {
define <2 x i8> @vtrunc_v2i8_v2i64_unmasked(<2 x i64> %a, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i8_v2i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
@@ -126,8 +113,8 @@ define <2 x i8> @vtrunc_v2i8_v2i64_unmasked(<2 x i64> %a, i32 zeroext %vl) {
define <2 x i16> @vtrunc_v2i16_v2i32(<2 x i32> %a, <2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i16_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = call <2 x i16> @llvm.vp.trunc.v2i16.v2i32(<2 x i32> %a, <2 x i1> %m, i32 %vl)
ret <2 x i16> %v
@@ -136,7 +123,7 @@ define <2 x i16> @vtrunc_v2i16_v2i32(<2 x i32> %a, <2 x i1> %m, i32 zeroext %vl)
define <2 x i16> @vtrunc_v2i16_v2i32_unmasked(<2 x i32> %a, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i16_v2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = call <2 x i16> @llvm.vp.trunc.v2i16.v2i32(<2 x i32> %a, <2 x i1> <i1 true, i1 true>, i32 %vl)
@@ -146,10 +133,10 @@ define <2 x i16> @vtrunc_v2i16_v2i32_unmasked(<2 x i32> %a, i32 zeroext %vl) {
define <2 x i16> @vtrunc_v2i16_v2i64(<2 x i64> %a, <2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i16_v2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = call <2 x i16> @llvm.vp.trunc.v2i16.v2i64(<2 x i64> %a, <2 x i1> %m, i32 %vl)
ret <2 x i16> %v
@@ -158,7 +145,7 @@ define <2 x i16> @vtrunc_v2i16_v2i64(<2 x i64> %a, <2 x i1> %m, i32 zeroext %vl)
define <2 x i16> @vtrunc_v2i16_v2i64_unmasked(<2 x i64> %a, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i16_v2i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
@@ -170,10 +157,10 @@ define <2 x i16> @vtrunc_v2i16_v2i64_unmasked(<2 x i64> %a, i32 zeroext %vl) {
define <15 x i16> @vtrunc_v15i16_v15i64(<15 x i64> %a, <15 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v15i16_v15i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vnsrl.wi v16, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v16, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v8, v16, 0
; CHECK-NEXT: ret
%v = call <15 x i16> @llvm.vp.trunc.v15i16.v15i64(<15 x i64> %a, <15 x i1> %m, i32 %vl)
ret <15 x i16> %v
@@ -182,8 +169,8 @@ define <15 x i16> @vtrunc_v15i16_v15i64(<15 x i64> %a, <15 x i1> %m, i32 zeroext
define <2 x i32> @vtrunc_v2i32_v2i64(<2 x i64> %a, <2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i32_v2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = call <2 x i32> @llvm.vp.trunc.v2i32.v2i64(<2 x i64> %a, <2 x i1> %m, i32 %vl)
ret <2 x i32> %v
@@ -192,7 +179,7 @@ define <2 x i32> @vtrunc_v2i32_v2i64(<2 x i64> %a, <2 x i1> %m, i32 zeroext %vl)
define <2 x i32> @vtrunc_v2i32_v2i64_unmasked(<2 x i64> %a, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i32_v2i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = call <2 x i32> @llvm.vp.trunc.v2i32.v2i64(<2 x i64> %a, <2 x i1> <i1 true, i1 true>, i32 %vl)
@@ -200,625 +187,110 @@ define <2 x i32> @vtrunc_v2i32_v2i64_unmasked(<2 x i64> %a, i32 zeroext %vl) {
}
define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 zeroext %vl) {
-; RV32-LABEL: vtrunc_v128i32_v128i64:
-; RV32: # %bb.0:
-; RV32-NEXT: addi sp, sp, -32
-; RV32-NEXT: .cfi_def_cfa_offset 32
-; RV32-NEXT: sw s0, 28(sp) # 4-byte Folded Spill
-; RV32-NEXT: .cfi_offset s0, -4
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 72
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: sub sp, sp, a2
-; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0xc8, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 72 * vlenb
-; RV32-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; RV32-NEXT: vmv1r.v v7, v0
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 5
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 40
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vslidedown.vi v5, v0, 8
-; RV32-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV32-NEXT: vslidedown.vi v4, v0, 4
-; RV32-NEXT: addi a2, a7, -64
-; RV32-NEXT: vslidedown.vi v3, v5, 4
-; RV32-NEXT: sltu a3, a7, a2
-; RV32-NEXT: addi a3, a3, -1
-; RV32-NEXT: and a4, a3, a2
-; RV32-NEXT: addi a2, a4, -32
-; RV32-NEXT: sltu a3, a4, a2
-; RV32-NEXT: addi a3, a3, -1
-; RV32-NEXT: and a3, a3, a2
-; RV32-NEXT: li a2, 16
-; RV32-NEXT: addi t0, a3, -16
-; RV32-NEXT: mv a5, a3
-; RV32-NEXT: bltu a3, a2, .LBB16_2
-; RV32-NEXT: # %bb.1:
-; RV32-NEXT: li a5, 16
-; RV32-NEXT: .LBB16_2:
-; RV32-NEXT: li t2, 64
-; RV32-NEXT: sltu t1, a3, t0
-; RV32-NEXT: mv a6, a7
-; RV32-NEXT: bltu a7, t2, .LBB16_4
-; RV32-NEXT: # %bb.3:
-; RV32-NEXT: li a6, 64
-; RV32-NEXT: .LBB16_4:
-; RV32-NEXT: addi t2, a1, 128
-; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v6, v4, 2
-; RV32-NEXT: addi t6, a1, 512
-; RV32-NEXT: addi t5, a1, 640
-; RV32-NEXT: vslidedown.vi v0, v3, 2
-; RV32-NEXT: addi t1, t1, -1
-; RV32-NEXT: addi t3, a1, 384
-; RV32-NEXT: vslidedown.vi v2, v5, 2
-; RV32-NEXT: li a3, 32
-; RV32-NEXT: addi t4, a6, -32
-; RV32-NEXT: sltu a6, a6, t4
-; RV32-NEXT: addi a6, a6, -1
-; RV32-NEXT: and a6, a6, t4
-; RV32-NEXT: addi t4, a6, -16
-; RV32-NEXT: sltu s0, a6, t4
-; RV32-NEXT: addi s0, s0, -1
-; RV32-NEXT: bltu a6, a2, .LBB16_6
-; RV32-NEXT: # %bb.5:
-; RV32-NEXT: li a6, 16
-; RV32-NEXT: .LBB16_6:
-; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vle64.v v8, (t6)
-; RV32-NEXT: csrr t6, vlenb
-; RV32-NEXT: sw a0, 4(sp) # 4-byte Folded Spill
-; RV32-NEXT: li a0, 56
-; RV32-NEXT: mul t6, t6, a0
-; RV32-NEXT: lw a0, 4(sp) # 4-byte Folded Reload
-; RV32-NEXT: add t6, sp, t6
-; RV32-NEXT: addi t6, t6, 16
-; RV32-NEXT: vs8r.v v8, (t6) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vle64.v v8, (t5)
-; RV32-NEXT: vle64.v v16, (t2)
-; RV32-NEXT: vle64.v v24, (a1)
-; RV32-NEXT: csrr t2, vlenb
-; RV32-NEXT: li t5, 48
-; RV32-NEXT: mul t2, t2, t5
-; RV32-NEXT: add t2, sp, t2
-; RV32-NEXT: addi t2, t2, 16
-; RV32-NEXT: vs8r.v v24, (t2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vle64.v v24, (t3)
-; RV32-NEXT: csrr t2, vlenb
-; RV32-NEXT: slli t2, t2, 3
-; RV32-NEXT: add t2, sp, t2
-; RV32-NEXT: addi t2, t2, 16
-; RV32-NEXT: vs8r.v v24, (t2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: and t2, t1, t0
-; RV32-NEXT: and t1, s0, t4
-; RV32-NEXT: addi a1, a1, 256
-; RV32-NEXT: mv t0, a4
-; RV32-NEXT: bltu a4, a3, .LBB16_8
-; RV32-NEXT: # %bb.7:
-; RV32-NEXT: li t0, 32
-; RV32-NEXT: .LBB16_8:
-; RV32-NEXT: vsetvli zero, t2, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v24, v8, 0, v0.t
-; RV32-NEXT: csrr t2, vlenb
-; RV32-NEXT: li t3, 24
-; RV32-NEXT: mul t2, t2, t3
-; RV32-NEXT: add t2, sp, t2
-; RV32-NEXT: addi t2, t2, 16
-; RV32-NEXT: vs8r.v v24, (t2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v3
-; RV32-NEXT: csrr t2, vlenb
-; RV32-NEXT: li t3, 56
-; RV32-NEXT: mul t2, t2, t3
-; RV32-NEXT: add t2, sp, t2
-; RV32-NEXT: addi t2, t2, 16
-; RV32-NEXT: vl8r.v v24, (t2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a5, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v8, v24, 0, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 6
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, t1, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 4
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
-; RV32-NEXT: addi a5, t0, -16
-; RV32-NEXT: sltu t0, t0, a5
-; RV32-NEXT: addi t0, t0, -1
-; RV32-NEXT: and a5, t0, a5
-; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vle64.v v8, (a1)
-; RV32-NEXT: addi a1, sp, 16
-; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v30, v7, 2
-; RV32-NEXT: vmv1r.v v0, v4
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li t0, 48
-; RV32-NEXT: mul a1, a1, t0
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a6, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a6, 56
-; RV32-NEXT: mul a1, a1, a6
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v2
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a5, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v16, v8, 0, v0.t
-; RV32-NEXT: bltu a4, a2, .LBB16_10
-; RV32-NEXT: # %bb.9:
-; RV32-NEXT: li a4, 16
-; RV32-NEXT: .LBB16_10:
-; RV32-NEXT: vmv1r.v v0, v5
-; RV32-NEXT: addi a1, sp, 16
-; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a4, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v24, v8, 0, v0.t
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a4, 48
-; RV32-NEXT: mul a1, a1, a4
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: mv a1, a7
-; RV32-NEXT: bltu a7, a3, .LBB16_12
-; RV32-NEXT: # %bb.11:
-; RV32-NEXT: li a1, 32
-; RV32-NEXT: .LBB16_12:
-; RV32-NEXT: vmv1r.v v0, v30
-; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: li a5, 24
-; RV32-NEXT: mul a4, a4, a5
-; RV32-NEXT: add a4, sp, a4
-; RV32-NEXT: addi a4, a4, 16
-; RV32-NEXT: vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: slli a4, a4, 4
-; RV32-NEXT: add a4, sp, a4
-; RV32-NEXT: addi a4, a4, 16
-; RV32-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: li a5, 24
-; RV32-NEXT: mul a4, a4, a5
-; RV32-NEXT: add a4, sp, a4
-; RV32-NEXT: addi a4, a4, 16
-; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: slli a4, a4, 6
-; RV32-NEXT: add a4, sp, a4
-; RV32-NEXT: addi a4, a4, 16
-; RV32-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; RV32-NEXT: vslideup.vi v16, v8, 16
-; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: slli a4, a4, 6
-; RV32-NEXT: add a4, sp, a4
-; RV32-NEXT: addi a4, a4, 16
-; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV32-NEXT: addi a4, a1, -16
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a6, 56
-; RV32-NEXT: mul a5, a5, a6
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vslideup.vi v16, v24, 16
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a6, 56
-; RV32-NEXT: mul a5, a5, a6
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a6, 48
-; RV32-NEXT: mul a5, a5, a6
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a6, 24
-; RV32-NEXT: mul a5, a5, a6
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vslideup.vi v16, v8, 16
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a6, 48
-; RV32-NEXT: mul a5, a5, a6
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
-; RV32-NEXT: sltu a1, a1, a4
-; RV32-NEXT: addi a1, a1, -1
-; RV32-NEXT: and a1, a1, a4
-; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: slli a4, a4, 5
-; RV32-NEXT: add a4, sp, a4
-; RV32-NEXT: addi a4, a4, 16
-; RV32-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t
-; RV32-NEXT: bltu a7, a2, .LBB16_14
-; RV32-NEXT: # %bb.13:
-; RV32-NEXT: li a7, 16
-; RV32-NEXT: .LBB16_14:
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 40
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a7, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v24, v16, 0, v0.t
-; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; RV32-NEXT: vslideup.vi v24, v8, 16
-; RV32-NEXT: vse32.v v24, (a0)
-; RV32-NEXT: addi a1, a0, 256
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 48
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vse32.v v8, (a1)
-; RV32-NEXT: addi a1, a0, 128
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 56
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vse32.v v8, (a1)
-; RV32-NEXT: addi a0, a0, 384
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 6
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vse32.v v8, (a0)
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 72
-; RV32-NEXT: mul a0, a0, a1
-; RV32-NEXT: add sp, sp, a0
-; RV32-NEXT: .cfi_def_cfa sp, 32
-; RV32-NEXT: lw s0, 28(sp) # 4-byte Folded Reload
-; RV32-NEXT: .cfi_restore s0
-; RV32-NEXT: addi sp, sp, 32
-; RV32-NEXT: .cfi_def_cfa_offset 0
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vtrunc_v128i32_v128i64:
-; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -48
-; RV64-NEXT: .cfi_def_cfa_offset 48
-; RV64-NEXT: sd s0, 40(sp) # 8-byte Folded Spill
-; RV64-NEXT: .cfi_offset s0, -8
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 72
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: sub sp, sp, a2
-; RV64-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0xc8, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 72 * vlenb
-; RV64-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; RV64-NEXT: vmv1r.v v7, v0
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: slli a2, a2, 5
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 32
-; RV64-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 40
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 32
-; RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vslidedown.vi v5, v0, 8
-; RV64-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64-NEXT: vslidedown.vi v4, v0, 4
-; RV64-NEXT: addi a2, a7, -64
-; RV64-NEXT: vslidedown.vi v3, v5, 4
-; RV64-NEXT: sltu a3, a7, a2
-; RV64-NEXT: addi a3, a3, -1
-; RV64-NEXT: and a4, a3, a2
-; RV64-NEXT: addi a2, a4, -32
-; RV64-NEXT: sltu a3, a4, a2
-; RV64-NEXT: addi a3, a3, -1
-; RV64-NEXT: and a3, a3, a2
-; RV64-NEXT: li a2, 16
-; RV64-NEXT: addi t0, a3, -16
-; RV64-NEXT: mv a5, a3
-; RV64-NEXT: bltu a3, a2, .LBB16_2
-; RV64-NEXT: # %bb.1:
-; RV64-NEXT: li a5, 16
-; RV64-NEXT: .LBB16_2:
-; RV64-NEXT: li t2, 64
-; RV64-NEXT: sltu t1, a3, t0
-; RV64-NEXT: mv a6, a7
-; RV64-NEXT: bltu a7, t2, .LBB16_4
-; RV64-NEXT: # %bb.3:
-; RV64-NEXT: li a6, 64
-; RV64-NEXT: .LBB16_4:
-; RV64-NEXT: addi t2, a1, 128
-; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vi v6, v4, 2
-; RV64-NEXT: addi t6, a1, 512
-; RV64-NEXT: addi t5, a1, 640
-; RV64-NEXT: vslidedown.vi v0, v3, 2
-; RV64-NEXT: addi t1, t1, -1
-; RV64-NEXT: addi t3, a1, 384
-; RV64-NEXT: vslidedown.vi v2, v5, 2
-; RV64-NEXT: li a3, 32
-; RV64-NEXT: addi t4, a6, -32
-; RV64-NEXT: sltu a6, a6, t4
-; RV64-NEXT: addi a6, a6, -1
-; RV64-NEXT: and a6, a6, t4
-; RV64-NEXT: addi t4, a6, -16
-; RV64-NEXT: sltu s0, a6, t4
-; RV64-NEXT: addi s0, s0, -1
-; RV64-NEXT: bltu a6, a2, .LBB16_6
-; RV64-NEXT: # %bb.5:
-; RV64-NEXT: li a6, 16
-; RV64-NEXT: .LBB16_6:
-; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vle64.v v8, (t6)
-; RV64-NEXT: csrr t6, vlenb
-; RV64-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64-NEXT: li a0, 56
-; RV64-NEXT: mul t6, t6, a0
-; RV64-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
-; RV64-NEXT: add t6, sp, t6
-; RV64-NEXT: addi t6, t6, 32
-; RV64-NEXT: vs8r.v v8, (t6) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vle64.v v8, (t5)
-; RV64-NEXT: vle64.v v16, (t2)
-; RV64-NEXT: vle64.v v24, (a1)
-; RV64-NEXT: csrr t2, vlenb
-; RV64-NEXT: li t5, 48
-; RV64-NEXT: mul t2, t2, t5
-; RV64-NEXT: add t2, sp, t2
-; RV64-NEXT: addi t2, t2, 32
-; RV64-NEXT: vs8r.v v24, (t2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vle64.v v24, (t3)
-; RV64-NEXT: csrr t2, vlenb
-; RV64-NEXT: slli t2, t2, 3
-; RV64-NEXT: add t2, sp, t2
-; RV64-NEXT: addi t2, t2, 32
-; RV64-NEXT: vs8r.v v24, (t2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: and t2, t1, t0
-; RV64-NEXT: and t1, s0, t4
-; RV64-NEXT: addi a1, a1, 256
-; RV64-NEXT: mv t0, a4
-; RV64-NEXT: bltu a4, a3, .LBB16_8
-; RV64-NEXT: # %bb.7:
-; RV64-NEXT: li t0, 32
-; RV64-NEXT: .LBB16_8:
-; RV64-NEXT: vsetvli zero, t2, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v24, v8, 0, v0.t
-; RV64-NEXT: csrr t2, vlenb
-; RV64-NEXT: li t3, 24
-; RV64-NEXT: mul t2, t2, t3
-; RV64-NEXT: add t2, sp, t2
-; RV64-NEXT: addi t2, t2, 32
-; RV64-NEXT: vs8r.v v24, (t2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv1r.v v0, v3
-; RV64-NEXT: csrr t2, vlenb
-; RV64-NEXT: li t3, 56
-; RV64-NEXT: mul t2, t2, t3
-; RV64-NEXT: add t2, sp, t2
-; RV64-NEXT: addi t2, t2, 32
-; RV64-NEXT: vl8r.v v24, (t2) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vsetvli zero, a5, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v8, v24, 0, v0.t
-; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: slli a5, a5, 6
-; RV64-NEXT: add a5, sp, a5
-; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, t1, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t
-; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: slli a5, a5, 4
-; RV64-NEXT: add a5, sp, a5
-; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
-; RV64-NEXT: addi a5, t0, -16
-; RV64-NEXT: sltu t0, t0, a5
-; RV64-NEXT: addi t0, t0, -1
-; RV64-NEXT: and a5, t0, a5
-; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vle64.v v8, (a1)
-; RV64-NEXT: addi a1, sp, 32
-; RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vi v30, v7, 2
-; RV64-NEXT: vmv1r.v v0, v4
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li t0, 48
-; RV64-NEXT: mul a1, a1, t0
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 32
-; RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vsetvli zero, a6, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a6, 56
-; RV64-NEXT: mul a1, a1, a6
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 32
-; RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv1r.v v0, v2
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 32
-; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vsetvli zero, a5, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v16, v8, 0, v0.t
-; RV64-NEXT: bltu a4, a2, .LBB16_10
-; RV64-NEXT: # %bb.9:
-; RV64-NEXT: li a4, 16
-; RV64-NEXT: .LBB16_10:
-; RV64-NEXT: vmv1r.v v0, v5
-; RV64-NEXT: addi a1, sp, 32
-; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vsetvli zero, a4, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v24, v8, 0, v0.t
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a4, 48
-; RV64-NEXT: mul a1, a1, a4
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 32
-; RV64-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
-; RV64-NEXT: mv a1, a7
-; RV64-NEXT: bltu a7, a3, .LBB16_12
-; RV64-NEXT: # %bb.11:
-; RV64-NEXT: li a1, 32
-; RV64-NEXT: .LBB16_12:
-; RV64-NEXT: vmv1r.v v0, v30
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: li a5, 24
-; RV64-NEXT: mul a4, a4, a5
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 32
-; RV64-NEXT: vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 4
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 32
-; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: li a5, 24
-; RV64-NEXT: mul a4, a4, a5
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 32
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 6
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 32
-; RV64-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; RV64-NEXT: vslideup.vi v16, v8, 16
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 6
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 32
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: addi a4, a1, -16
-; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li a6, 56
-; RV64-NEXT: mul a5, a5, a6
-; RV64-NEXT: add a5, sp, a5
-; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vslideup.vi v16, v24, 16
-; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li a6, 56
-; RV64-NEXT: mul a5, a5, a6
-; RV64-NEXT: add a5, sp, a5
-; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
-; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li a6, 48
-; RV64-NEXT: mul a5, a5, a6
-; RV64-NEXT: add a5, sp, a5
-; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
-; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li a6, 24
-; RV64-NEXT: mul a5, a5, a6
-; RV64-NEXT: add a5, sp, a5
-; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vslideup.vi v16, v8, 16
-; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li a6, 48
-; RV64-NEXT: mul a5, a5, a6
-; RV64-NEXT: add a5, sp, a5
-; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
-; RV64-NEXT: sltu a1, a1, a4
-; RV64-NEXT: addi a1, a1, -1
-; RV64-NEXT: and a1, a1, a4
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 5
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 32
-; RV64-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vsetvli zero, a1, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t
-; RV64-NEXT: bltu a7, a2, .LBB16_14
-; RV64-NEXT: # %bb.13:
-; RV64-NEXT: li a7, 16
-; RV64-NEXT: .LBB16_14:
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 40
-; RV64-NEXT: mul a1, a1, a2
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 32
-; RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vsetvli zero, a7, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v24, v16, 0, v0.t
-; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; RV64-NEXT: vslideup.vi v24, v8, 16
-; RV64-NEXT: vse32.v v24, (a0)
-; RV64-NEXT: addi a1, a0, 256
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 48
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 32
-; RV64-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vse32.v v8, (a1)
-; RV64-NEXT: addi a1, a0, 128
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 32
-; RV64-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vse32.v v8, (a1)
-; RV64-NEXT: addi a0, a0, 384
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 6
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 32
-; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vse32.v v8, (a0)
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 72
-; RV64-NEXT: mul a0, a0, a1
-; RV64-NEXT: add sp, sp, a0
-; RV64-NEXT: .cfi_def_cfa sp, 48
-; RV64-NEXT: ld s0, 40(sp) # 8-byte Folded Reload
-; RV64-NEXT: .cfi_restore s0
-; RV64-NEXT: addi sp, sp, 48
-; RV64-NEXT: .cfi_def_cfa_offset 0
-; RV64-NEXT: ret
+; CHECK-LABEL: vtrunc_v128i32_v128i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: li a3, 40
+; CHECK-NEXT: mul a2, a2, a3
+; CHECK-NEXT: sub sp, sp, a2
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
+; CHECK-NEXT: addi a2, a1, 512
+; CHECK-NEXT: addi a3, a1, 640
+; CHECK-NEXT: addi a4, a1, 256
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vle64.v v24, (a2)
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 5
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: addi a5, a1, 384
+; CHECK-NEXT: vle64.v v24, (a3)
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: li a3, 24
+; CHECK-NEXT: mul a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: li a2, 32
+; CHECK-NEXT: vnsrl.wi v24, v16, 0
+; CHECK-NEXT: vnsrl.wi v16, v8, 0
+; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vslideup.vi v16, v24, 16
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vle64.v v0, (a1)
+; CHECK-NEXT: addi a1, a1, 128
+; CHECK-NEXT: vle64.v v8, (a4)
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vle64.v v24, (a1)
+; CHECK-NEXT: vle64.v v8, (a5)
+; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vse32.v v16, (a0)
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v0, 0
+; CHECK-NEXT: vnsrl.wi v16, v24, 0
+; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v16, 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vnsrl.wi v24, v8, 0
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vnsrl.wi v16, v8, 0
+; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vslideup.vi v16, v24, 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: li a3, 24
+; CHECK-NEXT: mul a1, a1, a3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vnsrl.wi v24, v8, 0
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 5
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vnsrl.wi v0, v8, 0
+; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vslideup.vi v0, v24, 16
+; CHECK-NEXT: addi a1, a0, 384
+; CHECK-NEXT: vse32.v v0, (a1)
+; CHECK-NEXT: addi a1, a0, 256
+; CHECK-NEXT: vse32.v v16, (a1)
+; CHECK-NEXT: addi a0, a0, 128
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vse32.v v8, (a0)
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a1, 40
+; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: add sp, sp, a0
+; CHECK-NEXT: .cfi_def_cfa sp, 16
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: ret
%v = call <128 x i32> @llvm.vp.trunc.v128i32.v128i64(<128 x i64> %a, <128 x i1> %m, i32 %vl)
ret <128 x i32> %v
}
@@ -826,27 +298,13 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
define <32 x i32> @vtrunc_v32i32_v32i64(<32 x i64> %a, <32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v32i32_v32i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vmv8r.v v24, v8
-; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: vslidedown.vi v12, v0, 2
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: bltu a0, a2, .LBB17_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a1, 16
-; CHECK-NEXT: .LBB17_2:
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v24, 0, v0.t
-; CHECK-NEXT: addi a1, a0, -16
-; CHECK-NEXT: sltu a0, a0, a1
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a0, a0, a1
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vnsrl.wi v24, v16, 0
+; CHECK-NEXT: vnsrl.wi v16, v8, 0
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v24, 16
+; CHECK-NEXT: vslideup.vi v16, v24, 16
+; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
%v = call <32 x i32> @llvm.vp.trunc.v32i32.v32i64(<32 x i64> %a, <32 x i1> %m, i32 %vl)
ret <32 x i32> %v
@@ -859,3 +317,6 @@ define <2 x i7> @vtrunc_v2i7_v2i8(<2 x i8> %a, <2 x i1> %m, i32 zeroext %vl) {
%v = call <2 x i7> @llvm.vp.trunc.v2i7.v2i8(<2 x i8> %a, <2 x i1> %m, i32 %vl)
ret <2 x i7> %v
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; RV32: {{.*}}
+; RV64: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/rvv/pr141907.ll b/llvm/test/CodeGen/RISCV/rvv/pr141907.ll
index 1f485ea348396..aa8d3c2bb61fb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/pr141907.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/pr141907.ll
@@ -10,11 +10,10 @@ define void @pr141907(ptr %0) nounwind {
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: li a1, 0
+; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: addi a3, sp, 20
; CHECK-NEXT: li a4, 12
; CHECK-NEXT: .LBB0_1: # %vector.body
@@ -22,7 +21,7 @@ define void @pr141907(ptr %0) nounwind {
; CHECK-NEXT: vs4r.v v8, (a2)
; CHECK-NEXT: vsetvli a1, a1, e8, mf8, ta, ma
; CHECK-NEXT: vsetivli zero, 0, e16, mf2, ta, ma
-; CHECK-NEXT: vnsrl.wi v9, v8, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v9, v8, 0
; CHECK-NEXT: vsetvli a5, zero, e32, m1, ta, ma
; CHECK-NEXT: vlse32.v v8, (a3), a4
; CHECK-NEXT: vsetivli zero, 0, e16, mf2, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
index 54e02a5f4d1f4..44900ac653ca4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
@@ -528,7 +528,7 @@ define <vscale x 2 x i32> @vpselect_vpzext(<vscale x 2 x i32> %passthru, <vscale
define <vscale x 2 x i32> @vpselect_vptrunc(<vscale x 2 x i32> %passthru, <vscale x 2 x i64> %x, <vscale x 2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vpselect_vptrunc:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v10, 0, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 2 x i32> @llvm.vp.trunc.nxv2i32.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i1> splat (i1 -1), i32 %vl)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsra-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vnsra-vp.ll
index ec87c3d70a8bd..e4311985b11e6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vnsra-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vnsra-vp.ll
@@ -5,11 +5,8 @@
define <vscale x 1 x i16> @vsra_vv_nxv1i16(<vscale x 1 x i32> %a, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsra_vv_nxv1i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vsext.vf2 v10, v9
-; CHECK-NEXT: vsra.vv v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vnsra.wv v8, v8, v9
; CHECK-NEXT: ret
%bext = call <vscale x 1 x i32> @llvm.vp.sext.nxv1i32.nxv1i16(<vscale x 1 x i16> %b, <vscale x 1 x i1> splat (i1 -1), i32 %evl)
%v = call <vscale x 1 x i32> @llvm.vp.ashr.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %bext, <vscale x 1 x i1> splat (i1 -1), i32 %evl)
@@ -20,7 +17,7 @@ define <vscale x 1 x i16> @vsra_vv_nxv1i16(<vscale x 1 x i32> %a, <vscale x 1 x
define <vscale x 1 x i16> @vsra_vv_nxv1i16_unmasked(<vscale x 1 x i32> %a, <vscale x 1 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsra_vv_nxv1i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vnsra.wv v8, v8, v9
; CHECK-NEXT: ret
%bext = call <vscale x 1 x i32> @llvm.vp.sext.nxv1i32.nxv1i16(<vscale x 1 x i16> %b, <vscale x 1 x i1> splat (i1 -1), i32 %evl)
@@ -32,11 +29,8 @@ define <vscale x 1 x i16> @vsra_vv_nxv1i16_unmasked(<vscale x 1 x i32> %a, <vsca
define <vscale x 1 x i32> @vsra_vv_nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsra_vv_nxv1i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vsext.vf2 v10, v9
-; CHECK-NEXT: vsra.vv v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vnsra.wv v8, v8, v9
; CHECK-NEXT: ret
%bext = call <vscale x 1 x i64> @llvm.vp.sext.nxv1i64.nxv1i32(<vscale x 1 x i32> %b, <vscale x 1 x i1> splat (i1 -1), i32 %evl)
%v = call <vscale x 1 x i64> @llvm.vp.ashr.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %bext, <vscale x 1 x i1> splat (i1 -1), i32 %evl)
@@ -47,7 +41,7 @@ define <vscale x 1 x i32> @vsra_vv_nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x
define <vscale x 1 x i32> @vsra_vv_nxv1i64_unmasked(<vscale x 1 x i64> %a, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsra_vv_nxv1i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vnsra.wv v8, v8, v9
; CHECK-NEXT: ret
%bext = call <vscale x 1 x i64> @llvm.vp.sext.nxv1i64.nxv1i32(<vscale x 1 x i32> %b, <vscale x 1 x i1> splat (i1 -1), i32 %evl)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsrl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vnsrl-vp.ll
index 2451d7a5c0893..5562c36ba9f73 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vnsrl-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vnsrl-vp.ll
@@ -5,11 +5,8 @@
define <vscale x 1 x i16> @vsra_vv_nxv1i16(<vscale x 1 x i32> %a, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsra_vv_nxv1i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vsext.vf2 v10, v9
-; CHECK-NEXT: vsrl.vv v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vnsrl.wv v8, v8, v9
; CHECK-NEXT: ret
%bext = call <vscale x 1 x i32> @llvm.vp.sext.nxv1i32.nxv1i16(<vscale x 1 x i16> %b, <vscale x 1 x i1> splat (i1 -1), i32 %evl)
%v = call <vscale x 1 x i32> @llvm.vp.lshr.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %bext, <vscale x 1 x i1> splat (i1 -1), i32 %evl)
@@ -20,7 +17,7 @@ define <vscale x 1 x i16> @vsra_vv_nxv1i16(<vscale x 1 x i32> %a, <vscale x 1 x
define <vscale x 1 x i16> @vsra_vv_nxv1i16_unmasked(<vscale x 1 x i32> %a, <vscale x 1 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vsra_vv_nxv1i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wv v8, v8, v9
; CHECK-NEXT: ret
%bext = call <vscale x 1 x i32> @llvm.vp.sext.nxv1i32.nxv1i16(<vscale x 1 x i16> %b, <vscale x 1 x i1> splat (i1 -1), i32 %evl)
@@ -32,11 +29,8 @@ define <vscale x 1 x i16> @vsra_vv_nxv1i16_unmasked(<vscale x 1 x i32> %a, <vsca
define <vscale x 1 x i32> @vsra_vv_nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsra_vv_nxv1i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vsext.vf2 v10, v9
-; CHECK-NEXT: vsrl.vv v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vnsrl.wv v8, v8, v9
; CHECK-NEXT: ret
%bext = call <vscale x 1 x i64> @llvm.vp.sext.nxv1i64.nxv1i32(<vscale x 1 x i32> %b, <vscale x 1 x i1> splat (i1 -1), i32 %evl)
%v = call <vscale x 1 x i64> @llvm.vp.lshr.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %bext, <vscale x 1 x i1> splat (i1 -1), i32 %evl)
@@ -47,7 +41,7 @@ define <vscale x 1 x i32> @vsra_vv_nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x
define <vscale x 1 x i32> @vsra_vv_nxv1i64_unmasked(<vscale x 1 x i64> %a, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsra_vv_nxv1i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wv v8, v8, v9
; CHECK-NEXT: ret
%bext = call <vscale x 1 x i64> @llvm.vp.sext.nxv1i64.nxv1i32(<vscale x 1 x i32> %b, <vscale x 1 x i1> splat (i1 -1), i32 %evl)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-vaaddu.ll b/llvm/test/CodeGen/RISCV/rvv/vp-vaaddu.ll
index 89ea4d725660d..b575f97889f1b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-vaaddu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-vaaddu.ll
@@ -5,8 +5,8 @@ define <vscale x 2 x i8> @vaaddu_1(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y, <
; CHECK-LABEL: vaaddu_1:
; CHECK: # %bb.0:
; CHECK-NEXT: csrwi vxrm, 0
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vaaddu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vaaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%xz = call <vscale x 2 x i16> @llvm.vp.zext.nxv2i16.nxv2i8(<vscale x 2 x i8> %x, <vscale x 2 x i1> %m, i32 %vl)
%yz = call <vscale x 2 x i16> @llvm.vp.zext.nxv2i16.nxv2i8(<vscale x 2 x i8> %y, <vscale x 2 x i1> %m, i32 %vl)
@@ -21,8 +21,8 @@ define <vscale x 2 x i8> @vaaddu_2(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y, <
; CHECK-LABEL: vaaddu_2:
; CHECK: # %bb.0:
; CHECK-NEXT: csrwi vxrm, 0
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vaaddu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vaaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%xz = call <vscale x 2 x i16> @llvm.vp.zext.nxv2i16.nxv2i8(<vscale x 2 x i8> %x, <vscale x 2 x i1> %m, i32 %vl)
%yz = call <vscale x 2 x i16> @llvm.vp.zext.nxv2i16.nxv2i8(<vscale x 2 x i8> %y, <vscale x 2 x i1> %m, i32 %vl)
@@ -37,8 +37,8 @@ define <vscale x 2 x i8> @vaaddu_3(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y, <
; CHECK-LABEL: vaaddu_3:
; CHECK: # %bb.0:
; CHECK-NEXT: csrwi vxrm, 0
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vaaddu.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vaaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%xz = call <vscale x 2 x i16> @llvm.vp.zext.nxv2i16.nxv2i8(<vscale x 2 x i8> %x, <vscale x 2 x i1> %m, i32 %vl)
%yz = call <vscale x 2 x i16> @llvm.vp.zext.nxv2i16.nxv2i8(<vscale x 2 x i8> %y, <vscale x 2 x i1> %m, i32 %vl)
@@ -53,8 +53,8 @@ define <vscale x 2 x i8> @vaaddu_4(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y, <
; CHECK-LABEL: vaaddu_4:
; CHECK: # %bb.0:
; CHECK-NEXT: csrwi vxrm, 0
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vaaddu.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vaaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%xz = call <vscale x 2 x i16> @llvm.vp.zext.nxv2i16.nxv2i8(<vscale x 2 x i8> %x, <vscale x 2 x i1> %m, i32 %vl)
%yz = call <vscale x 2 x i16> @llvm.vp.zext.nxv2i16.nxv2i8(<vscale x 2 x i8> %y, <vscale x 2 x i1> %m, i32 %vl)
@@ -69,8 +69,8 @@ define <vscale x 2 x i8> @vaaddu_5(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y, <
; CHECK-LABEL: vaaddu_5:
; CHECK: # %bb.0:
; CHECK-NEXT: csrwi vxrm, 0
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vaaddu.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vaaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%xz = call <vscale x 2 x i16> @llvm.vp.zext.nxv2i16.nxv2i8(<vscale x 2 x i8> %x, <vscale x 2 x i1> %m, i32 %vl)
%yz = call <vscale x 2 x i16> @llvm.vp.zext.nxv2i16.nxv2i8(<vscale x 2 x i8> %y, <vscale x 2 x i1> %m, i32 %vl)
@@ -85,8 +85,8 @@ define <vscale x 2 x i8> @vaaddu_6(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y, <
; CHECK-LABEL: vaaddu_6:
; CHECK: # %bb.0:
; CHECK-NEXT: csrwi vxrm, 0
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vaaddu.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vaaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%xz = call <vscale x 2 x i16> @llvm.vp.zext.nxv2i16.nxv2i8(<vscale x 2 x i8> %x, <vscale x 2 x i1> %m, i32 %vl)
%yz = call <vscale x 2 x i16> @llvm.vp.zext.nxv2i16.nxv2i8(<vscale x 2 x i8> %y, <vscale x 2 x i1> %m, i32 %vl)
@@ -102,8 +102,8 @@ define <vscale x 2 x i8> @vaaddu_7(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y, <
; CHECK-LABEL: vaaddu_7:
; CHECK: # %bb.0:
; CHECK-NEXT: csrwi vxrm, 0
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vaaddu.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vaaddu.vv v8, v8, v9
; CHECK-NEXT: ret
%xz = call <vscale x 2 x i32> @llvm.vp.zext.nxv2i32.nxv2i8(<vscale x 2 x i8> %x, <vscale x 2 x i1> %m, i32 %vl)
%yz = call <vscale x 2 x i32> @llvm.vp.zext.nxv2i32.nxv2i8(<vscale x 2 x i8> %y, <vscale x 2 x i1> %m, i32 %vl)
@@ -118,11 +118,11 @@ define <vscale x 2 x i8> @vaaddu_7(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y, <
define <vscale x 2 x i16> @vaaddu_8(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y, <vscale x 2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vaaddu_8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vzext.vf2 v10, v8
-; CHECK-NEXT: vzext.vf2 v8, v9
; CHECK-NEXT: csrwi vxrm, 0
-; CHECK-NEXT: vaaddu.vv v8, v10, v8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vaaddu.vv v9, v8, v9
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vzext.vf2 v8, v9
; CHECK-NEXT: ret
%xz = call <vscale x 2 x i32> @llvm.vp.zext.nxv2i32.nxv2i8(<vscale x 2 x i8> %x, <vscale x 2 x i1> %m, i32 %vl)
%yz = call <vscale x 2 x i32> @llvm.vp.zext.nxv2i32.nxv2i8(<vscale x 2 x i8> %y, <vscale x 2 x i1> %m, i32 %vl)
@@ -133,20 +133,17 @@ define <vscale x 2 x i16> @vaaddu_8(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y,
ret <vscale x 2 x i16> %d
}
-; Negative test. The truncate has a smaller type than the zero extend.
-; TODO: Could still handle this by truncating after an i16 vaaddu.
define <vscale x 2 x i8> @vaaddu_9(<vscale x 2 x i16> %x, <vscale x 2 x i16> %y, <vscale x 2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vaaddu_9:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrwi vxrm, 0
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vaaddu.vv v8, v8, v9
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vadd.vi v8, v10, 1
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v9, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v8, v8, 1
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%xz = call <vscale x 2 x i32> @llvm.vp.zext.nxv2i32.nxv2i16(<vscale x 2 x i16> %x, <vscale x 2 x i1> %m, i32 %vl)
%yz = call <vscale x 2 x i32> @llvm.vp.zext.nxv2i32.nxv2i16(<vscale x 2 x i16> %y, <vscale x 2 x i1> %m, i32 %vl)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
index c4b4d4f6b328d..82110b2052ee5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
@@ -935,19 +935,13 @@ define <vscale x 8 x i32> @vsra_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale
ret <vscale x 8 x i32> %vc
}
-; Negative test. We shouldn't look through the vp.trunc as it isn't vlmax like
-; the rest of the code.
define <vscale x 1 x i8> @vsra_vv_nxv1i8_sext_zext_mixed_trunc(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsra_vv_nxv1i8_sext_zext_mixed_trunc:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vsext.vf4 v9, v8
-; CHECK-NEXT: vzext.vf4 v10, v8
-; CHECK-NEXT: vsra.vv v8, v9, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: li a0, 7
+; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vmin.vx v9, v8, a0
+; CHECK-NEXT: vsra.vv v8, v8, v9
; CHECK-NEXT: ret
%sexted_va = sext <vscale x 1 x i8> %va to <vscale x 1 x i32>
%zexted_vb = zext <vscale x 1 x i8> %va to <vscale x 1 x i32>
diff --git a/llvm/test/CodeGen/RISCV/rvv/vtrunc-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vtrunc-vp-mask.ll
index c1adb7d70e434..b521887de3e58 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vtrunc-vp-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vtrunc-vp-mask.ll
@@ -5,9 +5,9 @@
define <vscale x 2 x i1> @vtrunc_nxv2i1_nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv2i1_nxv2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vand.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i1> @llvm.vp.trunc.nxv2i1.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> %m, i32 %vl)
ret <vscale x 2 x i1> %v
@@ -16,7 +16,7 @@ define <vscale x 2 x i1> @vtrunc_nxv2i1_nxv2i16(<vscale x 2 x i16> %a, <vscale x
define <vscale x 2 x i1> @vtrunc_nxv2i1_nxv2i16_unmasked(<vscale x 2 x i16> %a, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv2i1_nxv2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
@@ -27,9 +27,9 @@ define <vscale x 2 x i1> @vtrunc_nxv2i1_nxv2i16_unmasked(<vscale x 2 x i16> %a,
define <vscale x 2 x i1> @vtrunc_nxv2i1_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv2i1_nxv2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vand.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i1> @llvm.vp.trunc.nxv2i1.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i32 %vl)
ret <vscale x 2 x i1> %v
@@ -38,7 +38,7 @@ define <vscale x 2 x i1> @vtrunc_nxv2i1_nxv2i32(<vscale x 2 x i32> %a, <vscale x
define <vscale x 2 x i1> @vtrunc_nxv2i1_nxv2i32_unmasked(<vscale x 2 x i32> %a, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv2i1_nxv2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
@@ -49,10 +49,9 @@ define <vscale x 2 x i1> @vtrunc_nxv2i1_nxv2i32_unmasked(<vscale x 2 x i32> %a,
define <vscale x 2 x i1> @vtrunc_nxv2i1_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv2i1_nxv2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vand.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vmsne.vi v10, v8, 0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i1> @llvm.vp.trunc.nxv2i1.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %m, i32 %vl)
ret <vscale x 2 x i1> %v
@@ -61,7 +60,7 @@ define <vscale x 2 x i1> @vtrunc_nxv2i1_nxv2i64(<vscale x 2 x i64> %a, <vscale x
define <vscale x 2 x i1> @vtrunc_nxv2i1_nxv2i64_unmasked(<vscale x 2 x i64> %a, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv2i1_nxv2i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
index 6414717ff74a5..5ae7929c6ebfc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
@@ -5,8 +5,8 @@
define <vscale x 2 x i7> @vtrunc_nxv2i7_nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv2i7_nxv2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i7> @llvm.vp.trunc.nxv2i7.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> %m, i32 %vl)
ret <vscale x 2 x i7> %v
@@ -15,8 +15,8 @@ define <vscale x 2 x i7> @vtrunc_nxv2i7_nxv2i16(<vscale x 2 x i16> %a, <vscale x
define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i15(<vscale x 2 x i15> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv2i8_nxv2i15:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.trunc.nxv2i8.nxv2i15(<vscale x 2 x i15> %a, <vscale x 2 x i1> %m, i32 %vl)
ret <vscale x 2 x i8> %v
@@ -25,8 +25,8 @@ define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i15(<vscale x 2 x i15> %a, <vscale x
define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv2i8_nxv2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.trunc.nxv2i8.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> %m, i32 %vl)
ret <vscale x 2 x i8> %v
@@ -35,7 +35,7 @@ define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i16(<vscale x 2 x i16> %a, <vscale x
define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i16_unmasked(<vscale x 2 x i16> %a, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv2i8_nxv2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.trunc.nxv2i8.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)
@@ -45,10 +45,10 @@ define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i16_unmasked(<vscale x 2 x i16> %a,
define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv2i8_nxv2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.trunc.nxv2i8.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i32 %vl)
ret <vscale x 2 x i8> %v
@@ -57,7 +57,7 @@ define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i32(<vscale x 2 x i32> %a, <vscale x
define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i32_unmasked(<vscale x 2 x i32> %a, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv2i8_nxv2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
@@ -69,12 +69,12 @@ define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i32_unmasked(<vscale x 2 x i32> %a,
define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv2i8_nxv2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v10, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.trunc.nxv2i8.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %m, i32 %vl)
ret <vscale x 2 x i8> %v
@@ -83,7 +83,7 @@ define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i64(<vscale x 2 x i64> %a, <vscale x
define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i64_unmasked(<vscale x 2 x i64> %a, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv2i8_nxv2i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0
@@ -97,8 +97,8 @@ define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i64_unmasked(<vscale x 2 x i64> %a,
define <vscale x 2 x i16> @vtrunc_nxv2i16_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv2i16_nxv2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.trunc.nxv2i16.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i32 %vl)
ret <vscale x 2 x i16> %v
@@ -107,7 +107,7 @@ define <vscale x 2 x i16> @vtrunc_nxv2i16_nxv2i32(<vscale x 2 x i32> %a, <vscale
define <vscale x 2 x i16> @vtrunc_nxv2i16_nxv2i32_unmasked(<vscale x 2 x i32> %a, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv2i16_nxv2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.trunc.nxv2i16.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)
@@ -117,10 +117,10 @@ define <vscale x 2 x i16> @vtrunc_nxv2i16_nxv2i32_unmasked(<vscale x 2 x i32> %a
define <vscale x 2 x i16> @vtrunc_nxv2i16_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv2i16_nxv2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v10, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.trunc.nxv2i16.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %m, i32 %vl)
ret <vscale x 2 x i16> %v
@@ -129,7 +129,7 @@ define <vscale x 2 x i16> @vtrunc_nxv2i16_nxv2i64(<vscale x 2 x i64> %a, <vscale
define <vscale x 2 x i16> @vtrunc_nxv2i16_nxv2i64_unmasked(<vscale x 2 x i64> %a, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv2i16_nxv2i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0
@@ -141,29 +141,14 @@ define <vscale x 2 x i16> @vtrunc_nxv2i16_nxv2i64_unmasked(<vscale x 2 x i64> %a
define <vscale x 15 x i16> @vtrunc_nxv15i16_nxv15i64(<vscale x 15 x i64> %a, <vscale x 15 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv15i16_nxv15i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 3
-; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma
-; CHECK-NEXT: vnsrl.wi v28, v16, 0, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vnsrl.wi v24, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vnsrl.wi v18, v28, 0, v0.t
-; CHECK-NEXT: bltu a0, a1, .LBB12_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: .LBB12_2:
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vnsrl.wi v20, v8, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v8, v24, 0
+; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vnsrl.wi v12, v16, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vnsrl.wi v16, v20, 0, v0.t
-; CHECK-NEXT: vmv4r.v v8, v16
+; CHECK-NEXT: vnsrl.wi v10, v12, 0
; CHECK-NEXT: ret
%v = call <vscale x 15 x i16> @llvm.vp.trunc.nxv15i16.nxv15i64(<vscale x 15 x i64> %a, <vscale x 15 x i1> %m, i32 %vl)
ret <vscale x 15 x i16> %v
@@ -172,8 +157,8 @@ define <vscale x 15 x i16> @vtrunc_nxv15i16_nxv15i64(<vscale x 15 x i64> %a, <vs
define <vscale x 2 x i32> @vtrunc_nxv2i32_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv2i32_nxv2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.trunc.nxv2i32.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %m, i32 %vl)
@@ -183,7 +168,7 @@ define <vscale x 2 x i32> @vtrunc_nxv2i32_nxv2i64(<vscale x 2 x i64> %a, <vscale
define <vscale x 2 x i32> @vtrunc_nxv2i32_nxv2i64_unmasked(<vscale x 2 x i64> %a, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv2i32_nxv2i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
@@ -194,30 +179,14 @@ define <vscale x 2 x i32> @vtrunc_nxv2i32_nxv2i64_unmasked(<vscale x 2 x i64> %a
define <vscale x 32 x i7> @vtrunc_nxv32i7_nxv32i32(<vscale x 32 x i32> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv32i7_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vnsrl.wi v28, v16, 0, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-NEXT: vnsrl.wi v24, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
-; CHECK-NEXT: vnsrl.wi v18, v28, 0, v0.t
-; CHECK-NEXT: bltu a0, a1, .LBB15_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: .LBB15_2:
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vnsrl.wi v20, v8, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v8, v24, 0
+; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; CHECK-NEXT: vnsrl.wi v12, v16, 0
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
-; CHECK-NEXT: vnsrl.wi v16, v20, 0, v0.t
-; CHECK-NEXT: vmv4r.v v8, v16
+; CHECK-NEXT: vnsrl.wi v10, v12, 0
; CHECK-NEXT: ret
%v = call <vscale x 32 x i7> @llvm.vp.trunc.nxv32i7.nxv32i32(<vscale x 32 x i32> %a, <vscale x 32 x i1> %m, i32 %vl)
ret <vscale x 32 x i7> %v
@@ -226,30 +195,14 @@ define <vscale x 32 x i7> @vtrunc_nxv32i7_nxv32i32(<vscale x 32 x i32> %a, <vsca
define <vscale x 32 x i8> @vtrunc_nxv32i8_nxv32i32(<vscale x 32 x i32> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv32i8_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vnsrl.wi v28, v16, 0, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-NEXT: vnsrl.wi v24, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
-; CHECK-NEXT: vnsrl.wi v18, v28, 0, v0.t
-; CHECK-NEXT: bltu a0, a1, .LBB16_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: .LBB16_2:
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vnsrl.wi v20, v8, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v8, v24, 0
+; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; CHECK-NEXT: vnsrl.wi v12, v16, 0
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
-; CHECK-NEXT: vnsrl.wi v16, v20, 0, v0.t
-; CHECK-NEXT: vmv4r.v v8, v16
+; CHECK-NEXT: vnsrl.wi v10, v12, 0
; CHECK-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.trunc.nxv32i8.nxv32i32(<vscale x 32 x i32> %a, <vscale x 32 x i1> %m, i32 %vl)
ret <vscale x 32 x i8> %v
@@ -261,78 +214,28 @@ define <vscale x 32 x i32> @vtrunc_nxv32i64_nxv32i32(<vscale x 32 x i64> %a, <vs
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
-; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv8r.v v0, v8
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: vl8re64.v v16, (a0)
-; CHECK-NEXT: srli a5, a1, 3
-; CHECK-NEXT: slli a4, a1, 3
-; CHECK-NEXT: slli a3, a1, 1
-; CHECK-NEXT: add a6, a0, a4
-; CHECK-NEXT: sub a0, a2, a3
-; CHECK-NEXT: sltu a4, a2, a0
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a0, a4, a0
-; CHECK-NEXT: sub a4, a0, a1
-; CHECK-NEXT: sltu a7, a0, a4
-; CHECK-NEXT: addi a7, a7, -1
-; CHECK-NEXT: and a4, a7, a4
-; CHECK-NEXT: srli a7, a1, 2
-; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; CHECK-NEXT: vle64.v v8, (a6)
-; CHECK-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vx v6, v0, a5
-; CHECK-NEXT: vsetvli a6, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v24, v0, a7
-; CHECK-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v24, a5
-; CHECK-NEXT: bltu a0, a1, .LBB17_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: .LBB17_2:
-; CHECK-NEXT: vsetvli zero, a4, e32, m4, ta, ma
-; CHECK-NEXT: vnsrl.wi v28, v8, 0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t
-; CHECK-NEXT: bltu a2, a3, .LBB17_4
-; CHECK-NEXT: # %bb.3:
-; CHECK-NEXT: mv a2, a3
-; CHECK-NEXT: .LBB17_4:
-; CHECK-NEXT: sub a0, a2, a1
-; CHECK-NEXT: sltu a3, a2, a0
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a0, a3, a0
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: addi a3, sp, 16
-; CHECK-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vnsrl.wi v12, v16, 0, v0.t
-; CHECK-NEXT: bltu a2, a1, .LBB17_6
-; CHECK-NEXT: # %bb.5:
-; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: .LBB17_6:
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl8re64.v v8, (a0)
+; CHECK-NEXT: vnsrl.wi v24, v0, 0
+; CHECK-NEXT: vnsrl.wi v0, v16, 0
+; CHECK-NEXT: vnsrl.wi v4, v8, 0
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vnsrl.wi v28, v8, 0
+; CHECK-NEXT: vmv8r.v v8, v24
+; CHECK-NEXT: vmv8r.v v16, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v16, 0, v0.t
-; CHECK-NEXT: vmv8r.v v16, v24
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
>From 197dfcbd6f3111670091768d6e50be3c5d10e6b0 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Wed, 29 Apr 2026 08:37:32 -0700
Subject: [PATCH 2/2] clang-format
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index eb0bc24a48af8..47fd94c3f12e2 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -10406,7 +10406,7 @@ SDValue RISCVTargetLowering::lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
// setcc operation:
// (vXi1 = trunc vXiN vec) -> (vXi1 = setcc (and vec, 1), 0, ne)
SDValue RISCVTargetLowering::lowerVectorMaskTrunc(SDValue Op,
- SelectionDAG &DAG) const {
+ SelectionDAG &DAG) const {
SDLoc DL(Op);
EVT MaskVT = Op.getValueType();
// Only expect to custom-lower truncations to mask types
@@ -10444,7 +10444,7 @@ SDValue RISCVTargetLowering::lowerVectorMaskTrunc(SDValue Op,
}
SDValue RISCVTargetLowering::lowerVectorTrunc(SDValue Op,
- SelectionDAG &DAG) const {
+ SelectionDAG &DAG) const {
unsigned Opc = Op.getOpcode();
SDLoc DL(Op);
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