[llvm] [llvm][RISCV] Optimize fneg for fixed vectors (PR #194555)
Brandon Wu via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 29 08:36:33 PDT 2026
https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/194555
>From 6460a1e710f52c7f954423e603849271a361426f Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Tue, 28 Apr 2026 14:35:35 +0800
Subject: [PATCH 1/3] pre commit test
---
.../RISCV/rvv/fixed-vectors-vfneg-sdnode.ll | 1131 ++++++++++++++++-
1 file changed, 1097 insertions(+), 34 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-sdnode.ll
index b3b9a62600f46..49195a9bde914 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-sdnode.ll
@@ -1,66 +1,1129 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfa,+v \
-; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfa,+v \
-; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+experimental-zvfbfa \
+; RUN: -target-abi=ilp32d -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFA,ZVFHMIN32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+experimental-zvfbfa \
+; RUN: -target-abi=lp64d -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFA,ZVFHMIN64
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin -target-abi=ilp32d \
+; RUN: -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFHMIN32,ZVFBFMIN32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin -target-abi=lp64d \
+; RUN: -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFHMIN64,ZVFBFMIN64
define <1 x bfloat> @v1bf16(<1 x bfloat> %va) {
-; CHECK-LABEL: v1bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 1, e16alt, mf4, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
-; CHECK-NEXT: ret
+; ZVFBFA-LABEL: v1bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 1, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfneg.v v8, v8
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN-LABEL: v1bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 8
+; ZVFBFMIN-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vxor.vx v8, v8, a0
+; ZVFBFMIN-NEXT: ret
%vb = fneg <1 x bfloat> %va
ret <1 x bfloat> %vb
}
define <2 x bfloat> @v2bf16(<2 x bfloat> %va) {
-; CHECK-LABEL: v2bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
-; CHECK-NEXT: ret
+; ZVFBFA-LABEL: v2bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfneg.v v8, v8
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN-LABEL: v2bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 8
+; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vxor.vx v8, v8, a0
+; ZVFBFMIN-NEXT: ret
%vb = fneg <2 x bfloat> %va
ret <2 x bfloat> %vb
}
define <4 x bfloat> @v4bf16(<4 x bfloat> %va) {
-; CHECK-LABEL: v4bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
-; CHECK-NEXT: ret
+; ZVFBFA-LABEL: v4bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma
+; ZVFBFA-NEXT: vfneg.v v8, v8
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN-LABEL: v4bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 8
+; ZVFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vxor.vx v8, v8, a0
+; ZVFBFMIN-NEXT: ret
%vb = fneg <4 x bfloat> %va
ret <4 x bfloat> %vb
}
define <8 x bfloat> @v8bf16(<8 x bfloat> %va) {
-; CHECK-LABEL: v8bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16alt, m1, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
-; CHECK-NEXT: ret
+; ZVFBFA-LABEL: v8bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 8, e16alt, m1, ta, ma
+; ZVFBFA-NEXT: vfneg.v v8, v8
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN-LABEL: v8bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 8
+; ZVFBFMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vxor.vx v8, v8, a0
+; ZVFBFMIN-NEXT: ret
%vb = fneg <8 x bfloat> %va
ret <8 x bfloat> %vb
}
define <16 x bfloat> @v16bf16(<16 x bfloat> %va) {
-; CHECK-LABEL: v16bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e16alt, m2, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
-; CHECK-NEXT: ret
+; ZVFBFA-LABEL: v16bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 16, e16alt, m2, ta, ma
+; ZVFBFA-NEXT: vfneg.v v8, v8
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN-LABEL: v16bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 8
+; ZVFBFMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFBFMIN-NEXT: vxor.vx v8, v8, a0
+; ZVFBFMIN-NEXT: ret
%vb = fneg <16 x bfloat> %va
ret <16 x bfloat> %vb
}
define <32 x bfloat> @v32bf16(<32 x bfloat> %va) {
-; CHECK-LABEL: v32bf16:
+; ZVFBFA-LABEL: v32bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: li a0, 32
+; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfneg.v v8, v8
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN-LABEL: v32bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: li a0, 32
+; ZVFBFMIN-NEXT: lui a1, 8
+; ZVFBFMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vxor.vx v8, v8, a1
+; ZVFBFMIN-NEXT: ret
+ %vb = fneg <32 x bfloat> %va
+ ret <32 x bfloat> %vb
+}
+
+define <64 x bfloat> @v64bf16(<64 x bfloat> %va) {
+; ZVFBFA-LABEL: v64bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: li a0, 64
+; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma
+; ZVFBFA-NEXT: vfneg.v v8, v8
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN32-LABEL: v64bf16:
+; ZVFBFMIN32: # %bb.0:
+; ZVFBFMIN32-NEXT: addi sp, sp, -384
+; ZVFBFMIN32-NEXT: .cfi_def_cfa_offset 384
+; ZVFBFMIN32-NEXT: sw ra, 380(sp) # 4-byte Folded Spill
+; ZVFBFMIN32-NEXT: sw s0, 376(sp) # 4-byte Folded Spill
+; ZVFBFMIN32-NEXT: .cfi_offset ra, -4
+; ZVFBFMIN32-NEXT: .cfi_offset s0, -8
+; ZVFBFMIN32-NEXT: addi s0, sp, 384
+; ZVFBFMIN32-NEXT: .cfi_def_cfa s0, 0
+; ZVFBFMIN32-NEXT: andi sp, sp, -128
+; ZVFBFMIN32-NEXT: li a0, 64
+; ZVFBFMIN32-NEXT: mv a1, sp
+; ZVFBFMIN32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFBFMIN32-NEXT: vse16.v v8, (a1)
+; ZVFBFMIN32-NEXT: lh a2, 126(sp)
+; ZVFBFMIN32-NEXT: lui a1, 8
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 254(sp)
+; ZVFBFMIN32-NEXT: lh a2, 124(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 252(sp)
+; ZVFBFMIN32-NEXT: lh a2, 122(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 250(sp)
+; ZVFBFMIN32-NEXT: lh a2, 120(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 248(sp)
+; ZVFBFMIN32-NEXT: lh a2, 118(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 246(sp)
+; ZVFBFMIN32-NEXT: lh a2, 116(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 244(sp)
+; ZVFBFMIN32-NEXT: lh a2, 114(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 242(sp)
+; ZVFBFMIN32-NEXT: lh a2, 112(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 240(sp)
+; ZVFBFMIN32-NEXT: lh a2, 110(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 238(sp)
+; ZVFBFMIN32-NEXT: lh a2, 108(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 236(sp)
+; ZVFBFMIN32-NEXT: lh a2, 106(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 234(sp)
+; ZVFBFMIN32-NEXT: lh a2, 104(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 232(sp)
+; ZVFBFMIN32-NEXT: lh a2, 102(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 230(sp)
+; ZVFBFMIN32-NEXT: lh a2, 100(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 228(sp)
+; ZVFBFMIN32-NEXT: lh a2, 98(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 226(sp)
+; ZVFBFMIN32-NEXT: lh a2, 96(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 224(sp)
+; ZVFBFMIN32-NEXT: lh a2, 94(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s a3, v8
+; ZVFBFMIN32-NEXT: xor a3, a3, a1
+; ZVFBFMIN32-NEXT: sh a3, 128(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 222(sp)
+; ZVFBFMIN32-NEXT: lh a2, 92(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 220(sp)
+; ZVFBFMIN32-NEXT: lh a2, 90(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 218(sp)
+; ZVFBFMIN32-NEXT: lh a2, 88(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 216(sp)
+; ZVFBFMIN32-NEXT: lh a2, 86(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 214(sp)
+; ZVFBFMIN32-NEXT: lh a2, 84(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 212(sp)
+; ZVFBFMIN32-NEXT: lh a2, 82(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 210(sp)
+; ZVFBFMIN32-NEXT: lh a2, 80(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 208(sp)
+; ZVFBFMIN32-NEXT: lh a2, 78(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 206(sp)
+; ZVFBFMIN32-NEXT: lh a2, 76(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 204(sp)
+; ZVFBFMIN32-NEXT: lh a2, 74(sp)
+; ZVFBFMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFBFMIN32-NEXT: vslidedown.vi v10, v8, 7
+; ZVFBFMIN32-NEXT: vslidedown.vi v11, v8, 6
+; ZVFBFMIN32-NEXT: vslidedown.vi v12, v8, 5
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 202(sp)
+; ZVFBFMIN32-NEXT: lh a2, 72(sp)
+; ZVFBFMIN32-NEXT: vslidedown.vi v13, v8, 4
+; ZVFBFMIN32-NEXT: vslidedown.vi v14, v8, 3
+; ZVFBFMIN32-NEXT: vslidedown.vi v15, v8, 2
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 200(sp)
+; ZVFBFMIN32-NEXT: lh a2, 70(sp)
+; ZVFBFMIN32-NEXT: vslidedown.vi v16, v8, 1
+; ZVFBFMIN32-NEXT: vmv.x.s a3, v10
+; ZVFBFMIN32-NEXT: vmv.x.s a4, v11
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 198(sp)
+; ZVFBFMIN32-NEXT: lh a2, 68(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s a5, v12
+; ZVFBFMIN32-NEXT: vmv.x.s a6, v13
+; ZVFBFMIN32-NEXT: vmv.x.s a7, v14
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 196(sp)
+; ZVFBFMIN32-NEXT: lh a2, 66(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s t0, v15
+; ZVFBFMIN32-NEXT: vmv.x.s t1, v16
+; ZVFBFMIN32-NEXT: xor a3, a3, a1
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 194(sp)
+; ZVFBFMIN32-NEXT: lh a2, 64(sp)
+; ZVFBFMIN32-NEXT: xor a4, a4, a1
+; ZVFBFMIN32-NEXT: xor a5, a5, a1
+; ZVFBFMIN32-NEXT: xor a6, a6, a1
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 192(sp)
+; ZVFBFMIN32-NEXT: lh a2, 62(sp)
+; ZVFBFMIN32-NEXT: xor a7, a7, a1
+; ZVFBFMIN32-NEXT: xor t0, t0, a1
+; ZVFBFMIN32-NEXT: xor t1, t1, a1
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 190(sp)
+; ZVFBFMIN32-NEXT: lh a2, 60(sp)
+; ZVFBFMIN32-NEXT: sh t1, 130(sp)
+; ZVFBFMIN32-NEXT: sh t0, 132(sp)
+; ZVFBFMIN32-NEXT: sh a7, 134(sp)
+; ZVFBFMIN32-NEXT: sh a6, 136(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a5, 138(sp)
+; ZVFBFMIN32-NEXT: sh a4, 140(sp)
+; ZVFBFMIN32-NEXT: sh a3, 142(sp)
+; ZVFBFMIN32-NEXT: sh a2, 188(sp)
+; ZVFBFMIN32-NEXT: lh a2, 58(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 186(sp)
+; ZVFBFMIN32-NEXT: lh a2, 56(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 184(sp)
+; ZVFBFMIN32-NEXT: lh a2, 54(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 182(sp)
+; ZVFBFMIN32-NEXT: lh a2, 52(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 180(sp)
+; ZVFBFMIN32-NEXT: lh a2, 50(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 178(sp)
+; ZVFBFMIN32-NEXT: lh a2, 48(sp)
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 176(sp)
+; ZVFBFMIN32-NEXT: lh a2, 46(sp)
+; ZVFBFMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFBFMIN32-NEXT: vslidedown.vi v10, v8, 15
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 174(sp)
+; ZVFBFMIN32-NEXT: lh a2, 44(sp)
+; ZVFBFMIN32-NEXT: vslidedown.vi v12, v8, 14
+; ZVFBFMIN32-NEXT: vslidedown.vi v14, v8, 13
+; ZVFBFMIN32-NEXT: vslidedown.vi v16, v8, 12
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 172(sp)
+; ZVFBFMIN32-NEXT: lh a2, 42(sp)
+; ZVFBFMIN32-NEXT: vslidedown.vi v18, v8, 11
+; ZVFBFMIN32-NEXT: vslidedown.vi v20, v8, 10
+; ZVFBFMIN32-NEXT: vslidedown.vi v22, v8, 9
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 170(sp)
+; ZVFBFMIN32-NEXT: lh a2, 40(sp)
+; ZVFBFMIN32-NEXT: vslidedown.vi v8, v8, 8
+; ZVFBFMIN32-NEXT: vmv.x.s a3, v10
+; ZVFBFMIN32-NEXT: vmv.x.s a4, v12
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 168(sp)
+; ZVFBFMIN32-NEXT: lh a2, 38(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s a5, v14
+; ZVFBFMIN32-NEXT: vmv.x.s a6, v16
+; ZVFBFMIN32-NEXT: vmv.x.s a7, v18
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 166(sp)
+; ZVFBFMIN32-NEXT: lh a2, 36(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s t0, v20
+; ZVFBFMIN32-NEXT: vmv.x.s t1, v22
+; ZVFBFMIN32-NEXT: xor a3, a3, a1
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 164(sp)
+; ZVFBFMIN32-NEXT: lh a2, 34(sp)
+; ZVFBFMIN32-NEXT: xor a4, a4, a1
+; ZVFBFMIN32-NEXT: xor a5, a5, a1
+; ZVFBFMIN32-NEXT: xor a6, a6, a1
+; ZVFBFMIN32-NEXT: xor a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 162(sp)
+; ZVFBFMIN32-NEXT: lh a2, 32(sp)
+; ZVFBFMIN32-NEXT: sh a6, 152(sp)
+; ZVFBFMIN32-NEXT: sh a5, 154(sp)
+; ZVFBFMIN32-NEXT: sh a4, 156(sp)
+; ZVFBFMIN32-NEXT: sh a3, 158(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s a3, v8
+; ZVFBFMIN32-NEXT: xor a4, a7, a1
+; ZVFBFMIN32-NEXT: xor a5, t0, a1
+; ZVFBFMIN32-NEXT: xor a6, t1, a1
+; ZVFBFMIN32-NEXT: xor a3, a3, a1
+; ZVFBFMIN32-NEXT: sh a3, 144(sp)
+; ZVFBFMIN32-NEXT: sh a6, 146(sp)
+; ZVFBFMIN32-NEXT: sh a5, 148(sp)
+; ZVFBFMIN32-NEXT: sh a4, 150(sp)
+; ZVFBFMIN32-NEXT: xor a1, a2, a1
+; ZVFBFMIN32-NEXT: sh a1, 160(sp)
+; ZVFBFMIN32-NEXT: addi a1, sp, 128
+; ZVFBFMIN32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFBFMIN32-NEXT: vle16.v v8, (a1)
+; ZVFBFMIN32-NEXT: addi sp, s0, -384
+; ZVFBFMIN32-NEXT: .cfi_def_cfa sp, 384
+; ZVFBFMIN32-NEXT: lw ra, 380(sp) # 4-byte Folded Reload
+; ZVFBFMIN32-NEXT: lw s0, 376(sp) # 4-byte Folded Reload
+; ZVFBFMIN32-NEXT: .cfi_restore ra
+; ZVFBFMIN32-NEXT: .cfi_restore s0
+; ZVFBFMIN32-NEXT: addi sp, sp, 384
+; ZVFBFMIN32-NEXT: .cfi_def_cfa_offset 0
+; ZVFBFMIN32-NEXT: ret
+;
+; ZVFBFMIN64-LABEL: v64bf16:
+; ZVFBFMIN64: # %bb.0:
+; ZVFBFMIN64-NEXT: addi sp, sp, -384
+; ZVFBFMIN64-NEXT: .cfi_def_cfa_offset 384
+; ZVFBFMIN64-NEXT: sd ra, 376(sp) # 8-byte Folded Spill
+; ZVFBFMIN64-NEXT: sd s0, 368(sp) # 8-byte Folded Spill
+; ZVFBFMIN64-NEXT: .cfi_offset ra, -8
+; ZVFBFMIN64-NEXT: .cfi_offset s0, -16
+; ZVFBFMIN64-NEXT: addi s0, sp, 384
+; ZVFBFMIN64-NEXT: .cfi_def_cfa s0, 0
+; ZVFBFMIN64-NEXT: andi sp, sp, -128
+; ZVFBFMIN64-NEXT: li a0, 64
+; ZVFBFMIN64-NEXT: mv a1, sp
+; ZVFBFMIN64-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFBFMIN64-NEXT: vse16.v v8, (a1)
+; ZVFBFMIN64-NEXT: lh a2, 126(sp)
+; ZVFBFMIN64-NEXT: lui a1, 8
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 254(sp)
+; ZVFBFMIN64-NEXT: lh a2, 124(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 252(sp)
+; ZVFBFMIN64-NEXT: lh a2, 122(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 250(sp)
+; ZVFBFMIN64-NEXT: lh a2, 120(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 248(sp)
+; ZVFBFMIN64-NEXT: lh a2, 118(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 246(sp)
+; ZVFBFMIN64-NEXT: lh a2, 116(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 244(sp)
+; ZVFBFMIN64-NEXT: lh a2, 114(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 242(sp)
+; ZVFBFMIN64-NEXT: lh a2, 112(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 240(sp)
+; ZVFBFMIN64-NEXT: lh a2, 110(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 238(sp)
+; ZVFBFMIN64-NEXT: lh a2, 108(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 236(sp)
+; ZVFBFMIN64-NEXT: lh a2, 106(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 234(sp)
+; ZVFBFMIN64-NEXT: lh a2, 104(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 232(sp)
+; ZVFBFMIN64-NEXT: lh a2, 102(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 230(sp)
+; ZVFBFMIN64-NEXT: lh a2, 100(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 228(sp)
+; ZVFBFMIN64-NEXT: lh a2, 98(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 226(sp)
+; ZVFBFMIN64-NEXT: lh a2, 96(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 224(sp)
+; ZVFBFMIN64-NEXT: lh a2, 94(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s a3, v8
+; ZVFBFMIN64-NEXT: xor a3, a3, a1
+; ZVFBFMIN64-NEXT: sh a3, 128(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 222(sp)
+; ZVFBFMIN64-NEXT: lh a2, 92(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 220(sp)
+; ZVFBFMIN64-NEXT: lh a2, 90(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 218(sp)
+; ZVFBFMIN64-NEXT: lh a2, 88(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 216(sp)
+; ZVFBFMIN64-NEXT: lh a2, 86(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 214(sp)
+; ZVFBFMIN64-NEXT: lh a2, 84(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 212(sp)
+; ZVFBFMIN64-NEXT: lh a2, 82(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 210(sp)
+; ZVFBFMIN64-NEXT: lh a2, 80(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 208(sp)
+; ZVFBFMIN64-NEXT: lh a2, 78(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 206(sp)
+; ZVFBFMIN64-NEXT: lh a2, 76(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 204(sp)
+; ZVFBFMIN64-NEXT: lh a2, 74(sp)
+; ZVFBFMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFBFMIN64-NEXT: vslidedown.vi v10, v8, 7
+; ZVFBFMIN64-NEXT: vslidedown.vi v11, v8, 6
+; ZVFBFMIN64-NEXT: vslidedown.vi v12, v8, 5
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 202(sp)
+; ZVFBFMIN64-NEXT: lh a2, 72(sp)
+; ZVFBFMIN64-NEXT: vslidedown.vi v13, v8, 4
+; ZVFBFMIN64-NEXT: vslidedown.vi v14, v8, 3
+; ZVFBFMIN64-NEXT: vslidedown.vi v15, v8, 2
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 200(sp)
+; ZVFBFMIN64-NEXT: lh a2, 70(sp)
+; ZVFBFMIN64-NEXT: vslidedown.vi v16, v8, 1
+; ZVFBFMIN64-NEXT: vmv.x.s a3, v10
+; ZVFBFMIN64-NEXT: vmv.x.s a4, v11
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 198(sp)
+; ZVFBFMIN64-NEXT: lh a2, 68(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s a5, v12
+; ZVFBFMIN64-NEXT: vmv.x.s a6, v13
+; ZVFBFMIN64-NEXT: vmv.x.s a7, v14
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 196(sp)
+; ZVFBFMIN64-NEXT: lh a2, 66(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s t0, v15
+; ZVFBFMIN64-NEXT: vmv.x.s t1, v16
+; ZVFBFMIN64-NEXT: xor a3, a3, a1
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 194(sp)
+; ZVFBFMIN64-NEXT: lh a2, 64(sp)
+; ZVFBFMIN64-NEXT: xor a4, a4, a1
+; ZVFBFMIN64-NEXT: xor a5, a5, a1
+; ZVFBFMIN64-NEXT: xor a6, a6, a1
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 192(sp)
+; ZVFBFMIN64-NEXT: lh a2, 62(sp)
+; ZVFBFMIN64-NEXT: xor a7, a7, a1
+; ZVFBFMIN64-NEXT: xor t0, t0, a1
+; ZVFBFMIN64-NEXT: xor t1, t1, a1
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 190(sp)
+; ZVFBFMIN64-NEXT: lh a2, 60(sp)
+; ZVFBFMIN64-NEXT: sh t1, 130(sp)
+; ZVFBFMIN64-NEXT: sh t0, 132(sp)
+; ZVFBFMIN64-NEXT: sh a7, 134(sp)
+; ZVFBFMIN64-NEXT: sh a6, 136(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a5, 138(sp)
+; ZVFBFMIN64-NEXT: sh a4, 140(sp)
+; ZVFBFMIN64-NEXT: sh a3, 142(sp)
+; ZVFBFMIN64-NEXT: sh a2, 188(sp)
+; ZVFBFMIN64-NEXT: lh a2, 58(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 186(sp)
+; ZVFBFMIN64-NEXT: lh a2, 56(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 184(sp)
+; ZVFBFMIN64-NEXT: lh a2, 54(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 182(sp)
+; ZVFBFMIN64-NEXT: lh a2, 52(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 180(sp)
+; ZVFBFMIN64-NEXT: lh a2, 50(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 178(sp)
+; ZVFBFMIN64-NEXT: lh a2, 48(sp)
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 176(sp)
+; ZVFBFMIN64-NEXT: lh a2, 46(sp)
+; ZVFBFMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFBFMIN64-NEXT: vslidedown.vi v10, v8, 15
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 174(sp)
+; ZVFBFMIN64-NEXT: lh a2, 44(sp)
+; ZVFBFMIN64-NEXT: vslidedown.vi v12, v8, 14
+; ZVFBFMIN64-NEXT: vslidedown.vi v14, v8, 13
+; ZVFBFMIN64-NEXT: vslidedown.vi v16, v8, 12
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 172(sp)
+; ZVFBFMIN64-NEXT: lh a2, 42(sp)
+; ZVFBFMIN64-NEXT: vslidedown.vi v18, v8, 11
+; ZVFBFMIN64-NEXT: vslidedown.vi v20, v8, 10
+; ZVFBFMIN64-NEXT: vslidedown.vi v22, v8, 9
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 170(sp)
+; ZVFBFMIN64-NEXT: lh a2, 40(sp)
+; ZVFBFMIN64-NEXT: vslidedown.vi v8, v8, 8
+; ZVFBFMIN64-NEXT: vmv.x.s a3, v10
+; ZVFBFMIN64-NEXT: vmv.x.s a4, v12
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 168(sp)
+; ZVFBFMIN64-NEXT: lh a2, 38(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s a5, v14
+; ZVFBFMIN64-NEXT: vmv.x.s a6, v16
+; ZVFBFMIN64-NEXT: vmv.x.s a7, v18
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 166(sp)
+; ZVFBFMIN64-NEXT: lh a2, 36(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s t0, v20
+; ZVFBFMIN64-NEXT: vmv.x.s t1, v22
+; ZVFBFMIN64-NEXT: xor a3, a3, a1
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 164(sp)
+; ZVFBFMIN64-NEXT: lh a2, 34(sp)
+; ZVFBFMIN64-NEXT: xor a4, a4, a1
+; ZVFBFMIN64-NEXT: xor a5, a5, a1
+; ZVFBFMIN64-NEXT: xor a6, a6, a1
+; ZVFBFMIN64-NEXT: xor a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 162(sp)
+; ZVFBFMIN64-NEXT: lh a2, 32(sp)
+; ZVFBFMIN64-NEXT: sh a6, 152(sp)
+; ZVFBFMIN64-NEXT: sh a5, 154(sp)
+; ZVFBFMIN64-NEXT: sh a4, 156(sp)
+; ZVFBFMIN64-NEXT: sh a3, 158(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s a3, v8
+; ZVFBFMIN64-NEXT: xor a4, a7, a1
+; ZVFBFMIN64-NEXT: xor a5, t0, a1
+; ZVFBFMIN64-NEXT: xor a6, t1, a1
+; ZVFBFMIN64-NEXT: xor a3, a3, a1
+; ZVFBFMIN64-NEXT: sh a3, 144(sp)
+; ZVFBFMIN64-NEXT: sh a6, 146(sp)
+; ZVFBFMIN64-NEXT: sh a5, 148(sp)
+; ZVFBFMIN64-NEXT: sh a4, 150(sp)
+; ZVFBFMIN64-NEXT: xor a1, a2, a1
+; ZVFBFMIN64-NEXT: sh a1, 160(sp)
+; ZVFBFMIN64-NEXT: addi a1, sp, 128
+; ZVFBFMIN64-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFBFMIN64-NEXT: vle16.v v8, (a1)
+; ZVFBFMIN64-NEXT: addi sp, s0, -384
+; ZVFBFMIN64-NEXT: .cfi_def_cfa sp, 384
+; ZVFBFMIN64-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
+; ZVFBFMIN64-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
+; ZVFBFMIN64-NEXT: .cfi_restore ra
+; ZVFBFMIN64-NEXT: .cfi_restore s0
+; ZVFBFMIN64-NEXT: addi sp, sp, 384
+; ZVFBFMIN64-NEXT: .cfi_def_cfa_offset 0
+; ZVFBFMIN64-NEXT: ret
+ %vb = fneg <64 x bfloat> %va
+ ret <64 x bfloat> %vb
+}
+
+define <1 x half> @v1f16(<1 x half> %va) {
+; CHECK-LABEL: v1f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 8
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; CHECK-NEXT: vxor.vx v8, v8, a0
+; CHECK-NEXT: ret
+ %vb = fneg <1 x half> %va
+ ret <1 x half> %vb
+}
+
+define <2 x half> @v2f16(<2 x half> %va) {
+; CHECK-LABEL: v2f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 8
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vxor.vx v8, v8, a0
+; CHECK-NEXT: ret
+ %vb = fneg <2 x half> %va
+ ret <2 x half> %vb
+}
+
+define <8 x half> @v8f16(<8 x half> %va) {
+; CHECK-LABEL: v8f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 8
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vxor.vx v8, v8, a0
+; CHECK-NEXT: ret
+ %vb = fneg <8 x half> %va
+ ret <8 x half> %vb
+}
+
+define <32 x half> @v32f16(<32 x half> %va) {
+; CHECK-LABEL: v32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma
-; CHECK-NEXT: vfneg.v v8, v8
+; CHECK-NEXT: lui a1, 8
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: vxor.vx v8, v8, a1
; CHECK-NEXT: ret
- %vb = fneg <32 x bfloat> %va
- ret <32 x bfloat> %vb
+ %vb = fneg <32 x half> %va
+ ret <32 x half> %vb
+}
+
+define <64 x half> @v64f16(<64 x half> %va) {
+; ZVFHMIN32-LABEL: v64f16:
+; ZVFHMIN32: # %bb.0:
+; ZVFHMIN32-NEXT: addi sp, sp, -384
+; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 384
+; ZVFHMIN32-NEXT: sw ra, 380(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: sw s0, 376(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: .cfi_offset ra, -4
+; ZVFHMIN32-NEXT: .cfi_offset s0, -8
+; ZVFHMIN32-NEXT: addi s0, sp, 384
+; ZVFHMIN32-NEXT: .cfi_def_cfa s0, 0
+; ZVFHMIN32-NEXT: andi sp, sp, -128
+; ZVFHMIN32-NEXT: li a0, 64
+; ZVFHMIN32-NEXT: mv a1, sp
+; ZVFHMIN32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN32-NEXT: vse16.v v8, (a1)
+; ZVFHMIN32-NEXT: lh a2, 126(sp)
+; ZVFHMIN32-NEXT: lui a1, 8
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 254(sp)
+; ZVFHMIN32-NEXT: lh a2, 124(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 252(sp)
+; ZVFHMIN32-NEXT: lh a2, 122(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 250(sp)
+; ZVFHMIN32-NEXT: lh a2, 120(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 248(sp)
+; ZVFHMIN32-NEXT: lh a2, 118(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 246(sp)
+; ZVFHMIN32-NEXT: lh a2, 116(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 244(sp)
+; ZVFHMIN32-NEXT: lh a2, 114(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 242(sp)
+; ZVFHMIN32-NEXT: lh a2, 112(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 240(sp)
+; ZVFHMIN32-NEXT: lh a2, 110(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 238(sp)
+; ZVFHMIN32-NEXT: lh a2, 108(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 236(sp)
+; ZVFHMIN32-NEXT: lh a2, 106(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 234(sp)
+; ZVFHMIN32-NEXT: lh a2, 104(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 232(sp)
+; ZVFHMIN32-NEXT: lh a2, 102(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 230(sp)
+; ZVFHMIN32-NEXT: lh a2, 100(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 228(sp)
+; ZVFHMIN32-NEXT: lh a2, 98(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 226(sp)
+; ZVFHMIN32-NEXT: lh a2, 96(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 224(sp)
+; ZVFHMIN32-NEXT: lh a2, 94(sp)
+; ZVFHMIN32-NEXT: vmv.x.s a3, v8
+; ZVFHMIN32-NEXT: xor a3, a3, a1
+; ZVFHMIN32-NEXT: sh a3, 128(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 222(sp)
+; ZVFHMIN32-NEXT: lh a2, 92(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 220(sp)
+; ZVFHMIN32-NEXT: lh a2, 90(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 218(sp)
+; ZVFHMIN32-NEXT: lh a2, 88(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 216(sp)
+; ZVFHMIN32-NEXT: lh a2, 86(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 214(sp)
+; ZVFHMIN32-NEXT: lh a2, 84(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 212(sp)
+; ZVFHMIN32-NEXT: lh a2, 82(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 210(sp)
+; ZVFHMIN32-NEXT: lh a2, 80(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 208(sp)
+; ZVFHMIN32-NEXT: lh a2, 78(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 206(sp)
+; ZVFHMIN32-NEXT: lh a2, 76(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 204(sp)
+; ZVFHMIN32-NEXT: lh a2, 74(sp)
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v10, v8, 7
+; ZVFHMIN32-NEXT: vslidedown.vi v11, v8, 6
+; ZVFHMIN32-NEXT: vslidedown.vi v12, v8, 5
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 202(sp)
+; ZVFHMIN32-NEXT: lh a2, 72(sp)
+; ZVFHMIN32-NEXT: vslidedown.vi v13, v8, 4
+; ZVFHMIN32-NEXT: vslidedown.vi v14, v8, 3
+; ZVFHMIN32-NEXT: vslidedown.vi v15, v8, 2
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 200(sp)
+; ZVFHMIN32-NEXT: lh a2, 70(sp)
+; ZVFHMIN32-NEXT: vslidedown.vi v16, v8, 1
+; ZVFHMIN32-NEXT: vmv.x.s a3, v10
+; ZVFHMIN32-NEXT: vmv.x.s a4, v11
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 198(sp)
+; ZVFHMIN32-NEXT: lh a2, 68(sp)
+; ZVFHMIN32-NEXT: vmv.x.s a5, v12
+; ZVFHMIN32-NEXT: vmv.x.s a6, v13
+; ZVFHMIN32-NEXT: vmv.x.s a7, v14
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 196(sp)
+; ZVFHMIN32-NEXT: lh a2, 66(sp)
+; ZVFHMIN32-NEXT: vmv.x.s t0, v15
+; ZVFHMIN32-NEXT: vmv.x.s t1, v16
+; ZVFHMIN32-NEXT: xor a3, a3, a1
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 194(sp)
+; ZVFHMIN32-NEXT: lh a2, 64(sp)
+; ZVFHMIN32-NEXT: xor a4, a4, a1
+; ZVFHMIN32-NEXT: xor a5, a5, a1
+; ZVFHMIN32-NEXT: xor a6, a6, a1
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 192(sp)
+; ZVFHMIN32-NEXT: lh a2, 62(sp)
+; ZVFHMIN32-NEXT: xor a7, a7, a1
+; ZVFHMIN32-NEXT: xor t0, t0, a1
+; ZVFHMIN32-NEXT: xor t1, t1, a1
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 190(sp)
+; ZVFHMIN32-NEXT: lh a2, 60(sp)
+; ZVFHMIN32-NEXT: sh t1, 130(sp)
+; ZVFHMIN32-NEXT: sh t0, 132(sp)
+; ZVFHMIN32-NEXT: sh a7, 134(sp)
+; ZVFHMIN32-NEXT: sh a6, 136(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a5, 138(sp)
+; ZVFHMIN32-NEXT: sh a4, 140(sp)
+; ZVFHMIN32-NEXT: sh a3, 142(sp)
+; ZVFHMIN32-NEXT: sh a2, 188(sp)
+; ZVFHMIN32-NEXT: lh a2, 58(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 186(sp)
+; ZVFHMIN32-NEXT: lh a2, 56(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 184(sp)
+; ZVFHMIN32-NEXT: lh a2, 54(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 182(sp)
+; ZVFHMIN32-NEXT: lh a2, 52(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 180(sp)
+; ZVFHMIN32-NEXT: lh a2, 50(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 178(sp)
+; ZVFHMIN32-NEXT: lh a2, 48(sp)
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 176(sp)
+; ZVFHMIN32-NEXT: lh a2, 46(sp)
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v10, v8, 15
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 174(sp)
+; ZVFHMIN32-NEXT: lh a2, 44(sp)
+; ZVFHMIN32-NEXT: vslidedown.vi v12, v8, 14
+; ZVFHMIN32-NEXT: vslidedown.vi v14, v8, 13
+; ZVFHMIN32-NEXT: vslidedown.vi v16, v8, 12
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 172(sp)
+; ZVFHMIN32-NEXT: lh a2, 42(sp)
+; ZVFHMIN32-NEXT: vslidedown.vi v18, v8, 11
+; ZVFHMIN32-NEXT: vslidedown.vi v20, v8, 10
+; ZVFHMIN32-NEXT: vslidedown.vi v22, v8, 9
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 170(sp)
+; ZVFHMIN32-NEXT: lh a2, 40(sp)
+; ZVFHMIN32-NEXT: vslidedown.vi v8, v8, 8
+; ZVFHMIN32-NEXT: vmv.x.s a3, v10
+; ZVFHMIN32-NEXT: vmv.x.s a4, v12
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 168(sp)
+; ZVFHMIN32-NEXT: lh a2, 38(sp)
+; ZVFHMIN32-NEXT: vmv.x.s a5, v14
+; ZVFHMIN32-NEXT: vmv.x.s a6, v16
+; ZVFHMIN32-NEXT: vmv.x.s a7, v18
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 166(sp)
+; ZVFHMIN32-NEXT: lh a2, 36(sp)
+; ZVFHMIN32-NEXT: vmv.x.s t0, v20
+; ZVFHMIN32-NEXT: vmv.x.s t1, v22
+; ZVFHMIN32-NEXT: xor a3, a3, a1
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 164(sp)
+; ZVFHMIN32-NEXT: lh a2, 34(sp)
+; ZVFHMIN32-NEXT: xor a4, a4, a1
+; ZVFHMIN32-NEXT: xor a5, a5, a1
+; ZVFHMIN32-NEXT: xor a6, a6, a1
+; ZVFHMIN32-NEXT: xor a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 162(sp)
+; ZVFHMIN32-NEXT: lh a2, 32(sp)
+; ZVFHMIN32-NEXT: sh a6, 152(sp)
+; ZVFHMIN32-NEXT: sh a5, 154(sp)
+; ZVFHMIN32-NEXT: sh a4, 156(sp)
+; ZVFHMIN32-NEXT: sh a3, 158(sp)
+; ZVFHMIN32-NEXT: vmv.x.s a3, v8
+; ZVFHMIN32-NEXT: xor a4, a7, a1
+; ZVFHMIN32-NEXT: xor a5, t0, a1
+; ZVFHMIN32-NEXT: xor a6, t1, a1
+; ZVFHMIN32-NEXT: xor a3, a3, a1
+; ZVFHMIN32-NEXT: sh a3, 144(sp)
+; ZVFHMIN32-NEXT: sh a6, 146(sp)
+; ZVFHMIN32-NEXT: sh a5, 148(sp)
+; ZVFHMIN32-NEXT: sh a4, 150(sp)
+; ZVFHMIN32-NEXT: xor a1, a2, a1
+; ZVFHMIN32-NEXT: sh a1, 160(sp)
+; ZVFHMIN32-NEXT: addi a1, sp, 128
+; ZVFHMIN32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN32-NEXT: vle16.v v8, (a1)
+; ZVFHMIN32-NEXT: addi sp, s0, -384
+; ZVFHMIN32-NEXT: .cfi_def_cfa sp, 384
+; ZVFHMIN32-NEXT: lw ra, 380(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: lw s0, 376(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: .cfi_restore ra
+; ZVFHMIN32-NEXT: .cfi_restore s0
+; ZVFHMIN32-NEXT: addi sp, sp, 384
+; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 0
+; ZVFHMIN32-NEXT: ret
+;
+; ZVFHMIN64-LABEL: v64f16:
+; ZVFHMIN64: # %bb.0:
+; ZVFHMIN64-NEXT: addi sp, sp, -384
+; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 384
+; ZVFHMIN64-NEXT: sd ra, 376(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: sd s0, 368(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: .cfi_offset ra, -8
+; ZVFHMIN64-NEXT: .cfi_offset s0, -16
+; ZVFHMIN64-NEXT: addi s0, sp, 384
+; ZVFHMIN64-NEXT: .cfi_def_cfa s0, 0
+; ZVFHMIN64-NEXT: andi sp, sp, -128
+; ZVFHMIN64-NEXT: li a0, 64
+; ZVFHMIN64-NEXT: mv a1, sp
+; ZVFHMIN64-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN64-NEXT: vse16.v v8, (a1)
+; ZVFHMIN64-NEXT: lh a2, 126(sp)
+; ZVFHMIN64-NEXT: lui a1, 8
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 254(sp)
+; ZVFHMIN64-NEXT: lh a2, 124(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 252(sp)
+; ZVFHMIN64-NEXT: lh a2, 122(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 250(sp)
+; ZVFHMIN64-NEXT: lh a2, 120(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 248(sp)
+; ZVFHMIN64-NEXT: lh a2, 118(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 246(sp)
+; ZVFHMIN64-NEXT: lh a2, 116(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 244(sp)
+; ZVFHMIN64-NEXT: lh a2, 114(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 242(sp)
+; ZVFHMIN64-NEXT: lh a2, 112(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 240(sp)
+; ZVFHMIN64-NEXT: lh a2, 110(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 238(sp)
+; ZVFHMIN64-NEXT: lh a2, 108(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 236(sp)
+; ZVFHMIN64-NEXT: lh a2, 106(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 234(sp)
+; ZVFHMIN64-NEXT: lh a2, 104(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 232(sp)
+; ZVFHMIN64-NEXT: lh a2, 102(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 230(sp)
+; ZVFHMIN64-NEXT: lh a2, 100(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 228(sp)
+; ZVFHMIN64-NEXT: lh a2, 98(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 226(sp)
+; ZVFHMIN64-NEXT: lh a2, 96(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 224(sp)
+; ZVFHMIN64-NEXT: lh a2, 94(sp)
+; ZVFHMIN64-NEXT: vmv.x.s a3, v8
+; ZVFHMIN64-NEXT: xor a3, a3, a1
+; ZVFHMIN64-NEXT: sh a3, 128(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 222(sp)
+; ZVFHMIN64-NEXT: lh a2, 92(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 220(sp)
+; ZVFHMIN64-NEXT: lh a2, 90(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 218(sp)
+; ZVFHMIN64-NEXT: lh a2, 88(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 216(sp)
+; ZVFHMIN64-NEXT: lh a2, 86(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 214(sp)
+; ZVFHMIN64-NEXT: lh a2, 84(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 212(sp)
+; ZVFHMIN64-NEXT: lh a2, 82(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 210(sp)
+; ZVFHMIN64-NEXT: lh a2, 80(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 208(sp)
+; ZVFHMIN64-NEXT: lh a2, 78(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 206(sp)
+; ZVFHMIN64-NEXT: lh a2, 76(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 204(sp)
+; ZVFHMIN64-NEXT: lh a2, 74(sp)
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v10, v8, 7
+; ZVFHMIN64-NEXT: vslidedown.vi v11, v8, 6
+; ZVFHMIN64-NEXT: vslidedown.vi v12, v8, 5
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 202(sp)
+; ZVFHMIN64-NEXT: lh a2, 72(sp)
+; ZVFHMIN64-NEXT: vslidedown.vi v13, v8, 4
+; ZVFHMIN64-NEXT: vslidedown.vi v14, v8, 3
+; ZVFHMIN64-NEXT: vslidedown.vi v15, v8, 2
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 200(sp)
+; ZVFHMIN64-NEXT: lh a2, 70(sp)
+; ZVFHMIN64-NEXT: vslidedown.vi v16, v8, 1
+; ZVFHMIN64-NEXT: vmv.x.s a3, v10
+; ZVFHMIN64-NEXT: vmv.x.s a4, v11
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 198(sp)
+; ZVFHMIN64-NEXT: lh a2, 68(sp)
+; ZVFHMIN64-NEXT: vmv.x.s a5, v12
+; ZVFHMIN64-NEXT: vmv.x.s a6, v13
+; ZVFHMIN64-NEXT: vmv.x.s a7, v14
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 196(sp)
+; ZVFHMIN64-NEXT: lh a2, 66(sp)
+; ZVFHMIN64-NEXT: vmv.x.s t0, v15
+; ZVFHMIN64-NEXT: vmv.x.s t1, v16
+; ZVFHMIN64-NEXT: xor a3, a3, a1
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 194(sp)
+; ZVFHMIN64-NEXT: lh a2, 64(sp)
+; ZVFHMIN64-NEXT: xor a4, a4, a1
+; ZVFHMIN64-NEXT: xor a5, a5, a1
+; ZVFHMIN64-NEXT: xor a6, a6, a1
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 192(sp)
+; ZVFHMIN64-NEXT: lh a2, 62(sp)
+; ZVFHMIN64-NEXT: xor a7, a7, a1
+; ZVFHMIN64-NEXT: xor t0, t0, a1
+; ZVFHMIN64-NEXT: xor t1, t1, a1
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 190(sp)
+; ZVFHMIN64-NEXT: lh a2, 60(sp)
+; ZVFHMIN64-NEXT: sh t1, 130(sp)
+; ZVFHMIN64-NEXT: sh t0, 132(sp)
+; ZVFHMIN64-NEXT: sh a7, 134(sp)
+; ZVFHMIN64-NEXT: sh a6, 136(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a5, 138(sp)
+; ZVFHMIN64-NEXT: sh a4, 140(sp)
+; ZVFHMIN64-NEXT: sh a3, 142(sp)
+; ZVFHMIN64-NEXT: sh a2, 188(sp)
+; ZVFHMIN64-NEXT: lh a2, 58(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 186(sp)
+; ZVFHMIN64-NEXT: lh a2, 56(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 184(sp)
+; ZVFHMIN64-NEXT: lh a2, 54(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 182(sp)
+; ZVFHMIN64-NEXT: lh a2, 52(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 180(sp)
+; ZVFHMIN64-NEXT: lh a2, 50(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 178(sp)
+; ZVFHMIN64-NEXT: lh a2, 48(sp)
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 176(sp)
+; ZVFHMIN64-NEXT: lh a2, 46(sp)
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v10, v8, 15
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 174(sp)
+; ZVFHMIN64-NEXT: lh a2, 44(sp)
+; ZVFHMIN64-NEXT: vslidedown.vi v12, v8, 14
+; ZVFHMIN64-NEXT: vslidedown.vi v14, v8, 13
+; ZVFHMIN64-NEXT: vslidedown.vi v16, v8, 12
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 172(sp)
+; ZVFHMIN64-NEXT: lh a2, 42(sp)
+; ZVFHMIN64-NEXT: vslidedown.vi v18, v8, 11
+; ZVFHMIN64-NEXT: vslidedown.vi v20, v8, 10
+; ZVFHMIN64-NEXT: vslidedown.vi v22, v8, 9
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 170(sp)
+; ZVFHMIN64-NEXT: lh a2, 40(sp)
+; ZVFHMIN64-NEXT: vslidedown.vi v8, v8, 8
+; ZVFHMIN64-NEXT: vmv.x.s a3, v10
+; ZVFHMIN64-NEXT: vmv.x.s a4, v12
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 168(sp)
+; ZVFHMIN64-NEXT: lh a2, 38(sp)
+; ZVFHMIN64-NEXT: vmv.x.s a5, v14
+; ZVFHMIN64-NEXT: vmv.x.s a6, v16
+; ZVFHMIN64-NEXT: vmv.x.s a7, v18
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 166(sp)
+; ZVFHMIN64-NEXT: lh a2, 36(sp)
+; ZVFHMIN64-NEXT: vmv.x.s t0, v20
+; ZVFHMIN64-NEXT: vmv.x.s t1, v22
+; ZVFHMIN64-NEXT: xor a3, a3, a1
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 164(sp)
+; ZVFHMIN64-NEXT: lh a2, 34(sp)
+; ZVFHMIN64-NEXT: xor a4, a4, a1
+; ZVFHMIN64-NEXT: xor a5, a5, a1
+; ZVFHMIN64-NEXT: xor a6, a6, a1
+; ZVFHMIN64-NEXT: xor a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 162(sp)
+; ZVFHMIN64-NEXT: lh a2, 32(sp)
+; ZVFHMIN64-NEXT: sh a6, 152(sp)
+; ZVFHMIN64-NEXT: sh a5, 154(sp)
+; ZVFHMIN64-NEXT: sh a4, 156(sp)
+; ZVFHMIN64-NEXT: sh a3, 158(sp)
+; ZVFHMIN64-NEXT: vmv.x.s a3, v8
+; ZVFHMIN64-NEXT: xor a4, a7, a1
+; ZVFHMIN64-NEXT: xor a5, t0, a1
+; ZVFHMIN64-NEXT: xor a6, t1, a1
+; ZVFHMIN64-NEXT: xor a3, a3, a1
+; ZVFHMIN64-NEXT: sh a3, 144(sp)
+; ZVFHMIN64-NEXT: sh a6, 146(sp)
+; ZVFHMIN64-NEXT: sh a5, 148(sp)
+; ZVFHMIN64-NEXT: sh a4, 150(sp)
+; ZVFHMIN64-NEXT: xor a1, a2, a1
+; ZVFHMIN64-NEXT: sh a1, 160(sp)
+; ZVFHMIN64-NEXT: addi a1, sp, 128
+; ZVFHMIN64-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN64-NEXT: vle16.v v8, (a1)
+; ZVFHMIN64-NEXT: addi sp, s0, -384
+; ZVFHMIN64-NEXT: .cfi_def_cfa sp, 384
+; ZVFHMIN64-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: .cfi_restore ra
+; ZVFHMIN64-NEXT: .cfi_restore s0
+; ZVFHMIN64-NEXT: addi sp, sp, 384
+; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 0
+; ZVFHMIN64-NEXT: ret
+ %vb = fneg <64 x half> %va
+ ret <64 x half> %vb
}
>From 1aebc886a6f237ad7862af20484d1508b07816a5 Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Tue, 28 Apr 2026 14:48:53 +0800
Subject: [PATCH 2/3] [llvm][RISCV] Optimize fneg for fixed vectors
vfneg is not available on zvfhmin or zvfbfmin, it's expected to expand
to integer operations instead of unrolling to scalar operations.
General expandFNEG already handles that in most of cases except for
fixed vector types that are not promotable, we need to find a better
heuristic to gate this.
---
.../SelectionDAG/LegalizeVectorOps.cpp | 21 +-
llvm/test/CodeGen/NVPTX/f16-instructions.ll | 3 +-
.../RISCV/rvv/fixed-vectors-vfneg-sdnode.ll | 972 +-----------------
llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll | 47 +-
4 files changed, 50 insertions(+), 993 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index 1aa21fc636a9d..9544fe580c4a3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -2060,10 +2060,23 @@ SDValue VectorLegalizer::ExpandFNEG(SDNode *Node) {
if (!TLI.isOperationLegalOrCustom(ISD::XOR, IntVT))
return SDValue();
- // FIXME: The FSUB check is here to force unrolling v1f64 vectors on AArch64.
- if (!TLI.isOperationLegalOrCustomOrPromote(ISD::FSUB, VT) &&
- !VT.isScalableVector())
- return SDValue();
+ // Heuristic check to determine whether vector should be expanded to integer
+ // operations or unrolled to scalar operations.
+ // 1. Scalable vector is never unrolled.
+ // 2. Fixed vector is unrolled if one of followings is true:
+ // a. Vector only has 1 element and target knows how to handle scalar
+ // FNEG (either legal or custom expand or promote).
+ // b. Vector has more than 1 element and target supports scalar
+ // FNEG natively and vector length <= 3 (2 AND + 1 OR).
+ if (VT.isFixedLengthVector()) {
+ EVT EltVT = VT.getVectorElementType();
+ if ((VT.getVectorNumElements() == 1 &&
+ TLI.isOperationLegalOrCustomOrPromote(ISD::FNEG, EltVT)) ||
+ (VT.getVectorNumElements() < 4 &&
+ TLI.isOperationLegal(ISD::FNEG, EltVT) &&
+ TLI.isExtractVecEltCheap(VT, 0)))
+ return SDValue();
+ }
SDLoc DL(Node);
SDValue Cast = DAG.getNode(ISD::BITCAST, DL, IntVT, Node->getOperand(0));
diff --git a/llvm/test/CodeGen/NVPTX/f16-instructions.ll b/llvm/test/CodeGen/NVPTX/f16-instructions.ll
index 53288b35d55a4..38c5b567b1378 100644
--- a/llvm/test/CodeGen/NVPTX/f16-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/f16-instructions.ll
@@ -1176,8 +1176,7 @@ define half @test_neg_f16(half noundef %arg) #0 {
; CHECK-LABEL: test_neg_f16x2(
; CHECK-F16-NOFTZ: neg.f16x2
; CHECK-F16-FTZ: neg.ftz.f16x2
-; CHECK-NOF16: xor.b16 %rs{{.*}}, %rs{{.*}}, -32768
-; CHECK-NOF16: xor.b16 %rs{{.*}}, %rs{{.*}}, -32768
+; CHECK-NOF16: xor.b32 %r{{.*}}, %r{{.*}}, -2147450880
define <2 x half> @test_neg_f16x2(<2 x half> noundef %arg) #0 {
%res = fneg <2 x half> %arg
ret <2 x half> %res
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-sdnode.ll
index 49195a9bde914..cf16fde1354b3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-sdnode.ll
@@ -1,16 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+experimental-zvfbfa \
; RUN: -target-abi=ilp32d -verify-machineinstrs < %s \
-; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFA,ZVFHMIN32
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFA
; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+experimental-zvfbfa \
; RUN: -target-abi=lp64d -verify-machineinstrs < %s \
-; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFA,ZVFHMIN64
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFA
; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s \
-; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFHMIN32,ZVFBFMIN32
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN
; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s \
-; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFHMIN64,ZVFBFMIN64
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN
define <1 x bfloat> @v1bf16(<1 x bfloat> %va) {
; ZVFBFA-LABEL: v1bf16:
@@ -124,481 +124,13 @@ define <64 x bfloat> @v64bf16(<64 x bfloat> %va) {
; ZVFBFA-NEXT: vfneg.v v8, v8
; ZVFBFA-NEXT: ret
;
-; ZVFBFMIN32-LABEL: v64bf16:
-; ZVFBFMIN32: # %bb.0:
-; ZVFBFMIN32-NEXT: addi sp, sp, -384
-; ZVFBFMIN32-NEXT: .cfi_def_cfa_offset 384
-; ZVFBFMIN32-NEXT: sw ra, 380(sp) # 4-byte Folded Spill
-; ZVFBFMIN32-NEXT: sw s0, 376(sp) # 4-byte Folded Spill
-; ZVFBFMIN32-NEXT: .cfi_offset ra, -4
-; ZVFBFMIN32-NEXT: .cfi_offset s0, -8
-; ZVFBFMIN32-NEXT: addi s0, sp, 384
-; ZVFBFMIN32-NEXT: .cfi_def_cfa s0, 0
-; ZVFBFMIN32-NEXT: andi sp, sp, -128
-; ZVFBFMIN32-NEXT: li a0, 64
-; ZVFBFMIN32-NEXT: mv a1, sp
-; ZVFBFMIN32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFBFMIN32-NEXT: vse16.v v8, (a1)
-; ZVFBFMIN32-NEXT: lh a2, 126(sp)
-; ZVFBFMIN32-NEXT: lui a1, 8
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 254(sp)
-; ZVFBFMIN32-NEXT: lh a2, 124(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 252(sp)
-; ZVFBFMIN32-NEXT: lh a2, 122(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 250(sp)
-; ZVFBFMIN32-NEXT: lh a2, 120(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 248(sp)
-; ZVFBFMIN32-NEXT: lh a2, 118(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 246(sp)
-; ZVFBFMIN32-NEXT: lh a2, 116(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 244(sp)
-; ZVFBFMIN32-NEXT: lh a2, 114(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 242(sp)
-; ZVFBFMIN32-NEXT: lh a2, 112(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 240(sp)
-; ZVFBFMIN32-NEXT: lh a2, 110(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 238(sp)
-; ZVFBFMIN32-NEXT: lh a2, 108(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 236(sp)
-; ZVFBFMIN32-NEXT: lh a2, 106(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 234(sp)
-; ZVFBFMIN32-NEXT: lh a2, 104(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 232(sp)
-; ZVFBFMIN32-NEXT: lh a2, 102(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 230(sp)
-; ZVFBFMIN32-NEXT: lh a2, 100(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 228(sp)
-; ZVFBFMIN32-NEXT: lh a2, 98(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 226(sp)
-; ZVFBFMIN32-NEXT: lh a2, 96(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 224(sp)
-; ZVFBFMIN32-NEXT: lh a2, 94(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s a3, v8
-; ZVFBFMIN32-NEXT: xor a3, a3, a1
-; ZVFBFMIN32-NEXT: sh a3, 128(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 222(sp)
-; ZVFBFMIN32-NEXT: lh a2, 92(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 220(sp)
-; ZVFBFMIN32-NEXT: lh a2, 90(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 218(sp)
-; ZVFBFMIN32-NEXT: lh a2, 88(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 216(sp)
-; ZVFBFMIN32-NEXT: lh a2, 86(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 214(sp)
-; ZVFBFMIN32-NEXT: lh a2, 84(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 212(sp)
-; ZVFBFMIN32-NEXT: lh a2, 82(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 210(sp)
-; ZVFBFMIN32-NEXT: lh a2, 80(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 208(sp)
-; ZVFBFMIN32-NEXT: lh a2, 78(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 206(sp)
-; ZVFBFMIN32-NEXT: lh a2, 76(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 204(sp)
-; ZVFBFMIN32-NEXT: lh a2, 74(sp)
-; ZVFBFMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFBFMIN32-NEXT: vslidedown.vi v10, v8, 7
-; ZVFBFMIN32-NEXT: vslidedown.vi v11, v8, 6
-; ZVFBFMIN32-NEXT: vslidedown.vi v12, v8, 5
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 202(sp)
-; ZVFBFMIN32-NEXT: lh a2, 72(sp)
-; ZVFBFMIN32-NEXT: vslidedown.vi v13, v8, 4
-; ZVFBFMIN32-NEXT: vslidedown.vi v14, v8, 3
-; ZVFBFMIN32-NEXT: vslidedown.vi v15, v8, 2
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 200(sp)
-; ZVFBFMIN32-NEXT: lh a2, 70(sp)
-; ZVFBFMIN32-NEXT: vslidedown.vi v16, v8, 1
-; ZVFBFMIN32-NEXT: vmv.x.s a3, v10
-; ZVFBFMIN32-NEXT: vmv.x.s a4, v11
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 198(sp)
-; ZVFBFMIN32-NEXT: lh a2, 68(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s a5, v12
-; ZVFBFMIN32-NEXT: vmv.x.s a6, v13
-; ZVFBFMIN32-NEXT: vmv.x.s a7, v14
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 196(sp)
-; ZVFBFMIN32-NEXT: lh a2, 66(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s t0, v15
-; ZVFBFMIN32-NEXT: vmv.x.s t1, v16
-; ZVFBFMIN32-NEXT: xor a3, a3, a1
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 194(sp)
-; ZVFBFMIN32-NEXT: lh a2, 64(sp)
-; ZVFBFMIN32-NEXT: xor a4, a4, a1
-; ZVFBFMIN32-NEXT: xor a5, a5, a1
-; ZVFBFMIN32-NEXT: xor a6, a6, a1
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 192(sp)
-; ZVFBFMIN32-NEXT: lh a2, 62(sp)
-; ZVFBFMIN32-NEXT: xor a7, a7, a1
-; ZVFBFMIN32-NEXT: xor t0, t0, a1
-; ZVFBFMIN32-NEXT: xor t1, t1, a1
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 190(sp)
-; ZVFBFMIN32-NEXT: lh a2, 60(sp)
-; ZVFBFMIN32-NEXT: sh t1, 130(sp)
-; ZVFBFMIN32-NEXT: sh t0, 132(sp)
-; ZVFBFMIN32-NEXT: sh a7, 134(sp)
-; ZVFBFMIN32-NEXT: sh a6, 136(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a5, 138(sp)
-; ZVFBFMIN32-NEXT: sh a4, 140(sp)
-; ZVFBFMIN32-NEXT: sh a3, 142(sp)
-; ZVFBFMIN32-NEXT: sh a2, 188(sp)
-; ZVFBFMIN32-NEXT: lh a2, 58(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 186(sp)
-; ZVFBFMIN32-NEXT: lh a2, 56(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 184(sp)
-; ZVFBFMIN32-NEXT: lh a2, 54(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 182(sp)
-; ZVFBFMIN32-NEXT: lh a2, 52(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 180(sp)
-; ZVFBFMIN32-NEXT: lh a2, 50(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 178(sp)
-; ZVFBFMIN32-NEXT: lh a2, 48(sp)
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 176(sp)
-; ZVFBFMIN32-NEXT: lh a2, 46(sp)
-; ZVFBFMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
-; ZVFBFMIN32-NEXT: vslidedown.vi v10, v8, 15
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 174(sp)
-; ZVFBFMIN32-NEXT: lh a2, 44(sp)
-; ZVFBFMIN32-NEXT: vslidedown.vi v12, v8, 14
-; ZVFBFMIN32-NEXT: vslidedown.vi v14, v8, 13
-; ZVFBFMIN32-NEXT: vslidedown.vi v16, v8, 12
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 172(sp)
-; ZVFBFMIN32-NEXT: lh a2, 42(sp)
-; ZVFBFMIN32-NEXT: vslidedown.vi v18, v8, 11
-; ZVFBFMIN32-NEXT: vslidedown.vi v20, v8, 10
-; ZVFBFMIN32-NEXT: vslidedown.vi v22, v8, 9
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 170(sp)
-; ZVFBFMIN32-NEXT: lh a2, 40(sp)
-; ZVFBFMIN32-NEXT: vslidedown.vi v8, v8, 8
-; ZVFBFMIN32-NEXT: vmv.x.s a3, v10
-; ZVFBFMIN32-NEXT: vmv.x.s a4, v12
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 168(sp)
-; ZVFBFMIN32-NEXT: lh a2, 38(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s a5, v14
-; ZVFBFMIN32-NEXT: vmv.x.s a6, v16
-; ZVFBFMIN32-NEXT: vmv.x.s a7, v18
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 166(sp)
-; ZVFBFMIN32-NEXT: lh a2, 36(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s t0, v20
-; ZVFBFMIN32-NEXT: vmv.x.s t1, v22
-; ZVFBFMIN32-NEXT: xor a3, a3, a1
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 164(sp)
-; ZVFBFMIN32-NEXT: lh a2, 34(sp)
-; ZVFBFMIN32-NEXT: xor a4, a4, a1
-; ZVFBFMIN32-NEXT: xor a5, a5, a1
-; ZVFBFMIN32-NEXT: xor a6, a6, a1
-; ZVFBFMIN32-NEXT: xor a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 162(sp)
-; ZVFBFMIN32-NEXT: lh a2, 32(sp)
-; ZVFBFMIN32-NEXT: sh a6, 152(sp)
-; ZVFBFMIN32-NEXT: sh a5, 154(sp)
-; ZVFBFMIN32-NEXT: sh a4, 156(sp)
-; ZVFBFMIN32-NEXT: sh a3, 158(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s a3, v8
-; ZVFBFMIN32-NEXT: xor a4, a7, a1
-; ZVFBFMIN32-NEXT: xor a5, t0, a1
-; ZVFBFMIN32-NEXT: xor a6, t1, a1
-; ZVFBFMIN32-NEXT: xor a3, a3, a1
-; ZVFBFMIN32-NEXT: sh a3, 144(sp)
-; ZVFBFMIN32-NEXT: sh a6, 146(sp)
-; ZVFBFMIN32-NEXT: sh a5, 148(sp)
-; ZVFBFMIN32-NEXT: sh a4, 150(sp)
-; ZVFBFMIN32-NEXT: xor a1, a2, a1
-; ZVFBFMIN32-NEXT: sh a1, 160(sp)
-; ZVFBFMIN32-NEXT: addi a1, sp, 128
-; ZVFBFMIN32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFBFMIN32-NEXT: vle16.v v8, (a1)
-; ZVFBFMIN32-NEXT: addi sp, s0, -384
-; ZVFBFMIN32-NEXT: .cfi_def_cfa sp, 384
-; ZVFBFMIN32-NEXT: lw ra, 380(sp) # 4-byte Folded Reload
-; ZVFBFMIN32-NEXT: lw s0, 376(sp) # 4-byte Folded Reload
-; ZVFBFMIN32-NEXT: .cfi_restore ra
-; ZVFBFMIN32-NEXT: .cfi_restore s0
-; ZVFBFMIN32-NEXT: addi sp, sp, 384
-; ZVFBFMIN32-NEXT: .cfi_def_cfa_offset 0
-; ZVFBFMIN32-NEXT: ret
-;
-; ZVFBFMIN64-LABEL: v64bf16:
-; ZVFBFMIN64: # %bb.0:
-; ZVFBFMIN64-NEXT: addi sp, sp, -384
-; ZVFBFMIN64-NEXT: .cfi_def_cfa_offset 384
-; ZVFBFMIN64-NEXT: sd ra, 376(sp) # 8-byte Folded Spill
-; ZVFBFMIN64-NEXT: sd s0, 368(sp) # 8-byte Folded Spill
-; ZVFBFMIN64-NEXT: .cfi_offset ra, -8
-; ZVFBFMIN64-NEXT: .cfi_offset s0, -16
-; ZVFBFMIN64-NEXT: addi s0, sp, 384
-; ZVFBFMIN64-NEXT: .cfi_def_cfa s0, 0
-; ZVFBFMIN64-NEXT: andi sp, sp, -128
-; ZVFBFMIN64-NEXT: li a0, 64
-; ZVFBFMIN64-NEXT: mv a1, sp
-; ZVFBFMIN64-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFBFMIN64-NEXT: vse16.v v8, (a1)
-; ZVFBFMIN64-NEXT: lh a2, 126(sp)
-; ZVFBFMIN64-NEXT: lui a1, 8
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 254(sp)
-; ZVFBFMIN64-NEXT: lh a2, 124(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 252(sp)
-; ZVFBFMIN64-NEXT: lh a2, 122(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 250(sp)
-; ZVFBFMIN64-NEXT: lh a2, 120(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 248(sp)
-; ZVFBFMIN64-NEXT: lh a2, 118(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 246(sp)
-; ZVFBFMIN64-NEXT: lh a2, 116(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 244(sp)
-; ZVFBFMIN64-NEXT: lh a2, 114(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 242(sp)
-; ZVFBFMIN64-NEXT: lh a2, 112(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 240(sp)
-; ZVFBFMIN64-NEXT: lh a2, 110(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 238(sp)
-; ZVFBFMIN64-NEXT: lh a2, 108(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 236(sp)
-; ZVFBFMIN64-NEXT: lh a2, 106(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 234(sp)
-; ZVFBFMIN64-NEXT: lh a2, 104(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 232(sp)
-; ZVFBFMIN64-NEXT: lh a2, 102(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 230(sp)
-; ZVFBFMIN64-NEXT: lh a2, 100(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 228(sp)
-; ZVFBFMIN64-NEXT: lh a2, 98(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 226(sp)
-; ZVFBFMIN64-NEXT: lh a2, 96(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 224(sp)
-; ZVFBFMIN64-NEXT: lh a2, 94(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s a3, v8
-; ZVFBFMIN64-NEXT: xor a3, a3, a1
-; ZVFBFMIN64-NEXT: sh a3, 128(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 222(sp)
-; ZVFBFMIN64-NEXT: lh a2, 92(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 220(sp)
-; ZVFBFMIN64-NEXT: lh a2, 90(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 218(sp)
-; ZVFBFMIN64-NEXT: lh a2, 88(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 216(sp)
-; ZVFBFMIN64-NEXT: lh a2, 86(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 214(sp)
-; ZVFBFMIN64-NEXT: lh a2, 84(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 212(sp)
-; ZVFBFMIN64-NEXT: lh a2, 82(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 210(sp)
-; ZVFBFMIN64-NEXT: lh a2, 80(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 208(sp)
-; ZVFBFMIN64-NEXT: lh a2, 78(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 206(sp)
-; ZVFBFMIN64-NEXT: lh a2, 76(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 204(sp)
-; ZVFBFMIN64-NEXT: lh a2, 74(sp)
-; ZVFBFMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFBFMIN64-NEXT: vslidedown.vi v10, v8, 7
-; ZVFBFMIN64-NEXT: vslidedown.vi v11, v8, 6
-; ZVFBFMIN64-NEXT: vslidedown.vi v12, v8, 5
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 202(sp)
-; ZVFBFMIN64-NEXT: lh a2, 72(sp)
-; ZVFBFMIN64-NEXT: vslidedown.vi v13, v8, 4
-; ZVFBFMIN64-NEXT: vslidedown.vi v14, v8, 3
-; ZVFBFMIN64-NEXT: vslidedown.vi v15, v8, 2
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 200(sp)
-; ZVFBFMIN64-NEXT: lh a2, 70(sp)
-; ZVFBFMIN64-NEXT: vslidedown.vi v16, v8, 1
-; ZVFBFMIN64-NEXT: vmv.x.s a3, v10
-; ZVFBFMIN64-NEXT: vmv.x.s a4, v11
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 198(sp)
-; ZVFBFMIN64-NEXT: lh a2, 68(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s a5, v12
-; ZVFBFMIN64-NEXT: vmv.x.s a6, v13
-; ZVFBFMIN64-NEXT: vmv.x.s a7, v14
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 196(sp)
-; ZVFBFMIN64-NEXT: lh a2, 66(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s t0, v15
-; ZVFBFMIN64-NEXT: vmv.x.s t1, v16
-; ZVFBFMIN64-NEXT: xor a3, a3, a1
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 194(sp)
-; ZVFBFMIN64-NEXT: lh a2, 64(sp)
-; ZVFBFMIN64-NEXT: xor a4, a4, a1
-; ZVFBFMIN64-NEXT: xor a5, a5, a1
-; ZVFBFMIN64-NEXT: xor a6, a6, a1
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 192(sp)
-; ZVFBFMIN64-NEXT: lh a2, 62(sp)
-; ZVFBFMIN64-NEXT: xor a7, a7, a1
-; ZVFBFMIN64-NEXT: xor t0, t0, a1
-; ZVFBFMIN64-NEXT: xor t1, t1, a1
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 190(sp)
-; ZVFBFMIN64-NEXT: lh a2, 60(sp)
-; ZVFBFMIN64-NEXT: sh t1, 130(sp)
-; ZVFBFMIN64-NEXT: sh t0, 132(sp)
-; ZVFBFMIN64-NEXT: sh a7, 134(sp)
-; ZVFBFMIN64-NEXT: sh a6, 136(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a5, 138(sp)
-; ZVFBFMIN64-NEXT: sh a4, 140(sp)
-; ZVFBFMIN64-NEXT: sh a3, 142(sp)
-; ZVFBFMIN64-NEXT: sh a2, 188(sp)
-; ZVFBFMIN64-NEXT: lh a2, 58(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 186(sp)
-; ZVFBFMIN64-NEXT: lh a2, 56(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 184(sp)
-; ZVFBFMIN64-NEXT: lh a2, 54(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 182(sp)
-; ZVFBFMIN64-NEXT: lh a2, 52(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 180(sp)
-; ZVFBFMIN64-NEXT: lh a2, 50(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 178(sp)
-; ZVFBFMIN64-NEXT: lh a2, 48(sp)
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 176(sp)
-; ZVFBFMIN64-NEXT: lh a2, 46(sp)
-; ZVFBFMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
-; ZVFBFMIN64-NEXT: vslidedown.vi v10, v8, 15
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 174(sp)
-; ZVFBFMIN64-NEXT: lh a2, 44(sp)
-; ZVFBFMIN64-NEXT: vslidedown.vi v12, v8, 14
-; ZVFBFMIN64-NEXT: vslidedown.vi v14, v8, 13
-; ZVFBFMIN64-NEXT: vslidedown.vi v16, v8, 12
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 172(sp)
-; ZVFBFMIN64-NEXT: lh a2, 42(sp)
-; ZVFBFMIN64-NEXT: vslidedown.vi v18, v8, 11
-; ZVFBFMIN64-NEXT: vslidedown.vi v20, v8, 10
-; ZVFBFMIN64-NEXT: vslidedown.vi v22, v8, 9
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 170(sp)
-; ZVFBFMIN64-NEXT: lh a2, 40(sp)
-; ZVFBFMIN64-NEXT: vslidedown.vi v8, v8, 8
-; ZVFBFMIN64-NEXT: vmv.x.s a3, v10
-; ZVFBFMIN64-NEXT: vmv.x.s a4, v12
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 168(sp)
-; ZVFBFMIN64-NEXT: lh a2, 38(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s a5, v14
-; ZVFBFMIN64-NEXT: vmv.x.s a6, v16
-; ZVFBFMIN64-NEXT: vmv.x.s a7, v18
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 166(sp)
-; ZVFBFMIN64-NEXT: lh a2, 36(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s t0, v20
-; ZVFBFMIN64-NEXT: vmv.x.s t1, v22
-; ZVFBFMIN64-NEXT: xor a3, a3, a1
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 164(sp)
-; ZVFBFMIN64-NEXT: lh a2, 34(sp)
-; ZVFBFMIN64-NEXT: xor a4, a4, a1
-; ZVFBFMIN64-NEXT: xor a5, a5, a1
-; ZVFBFMIN64-NEXT: xor a6, a6, a1
-; ZVFBFMIN64-NEXT: xor a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 162(sp)
-; ZVFBFMIN64-NEXT: lh a2, 32(sp)
-; ZVFBFMIN64-NEXT: sh a6, 152(sp)
-; ZVFBFMIN64-NEXT: sh a5, 154(sp)
-; ZVFBFMIN64-NEXT: sh a4, 156(sp)
-; ZVFBFMIN64-NEXT: sh a3, 158(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s a3, v8
-; ZVFBFMIN64-NEXT: xor a4, a7, a1
-; ZVFBFMIN64-NEXT: xor a5, t0, a1
-; ZVFBFMIN64-NEXT: xor a6, t1, a1
-; ZVFBFMIN64-NEXT: xor a3, a3, a1
-; ZVFBFMIN64-NEXT: sh a3, 144(sp)
-; ZVFBFMIN64-NEXT: sh a6, 146(sp)
-; ZVFBFMIN64-NEXT: sh a5, 148(sp)
-; ZVFBFMIN64-NEXT: sh a4, 150(sp)
-; ZVFBFMIN64-NEXT: xor a1, a2, a1
-; ZVFBFMIN64-NEXT: sh a1, 160(sp)
-; ZVFBFMIN64-NEXT: addi a1, sp, 128
-; ZVFBFMIN64-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFBFMIN64-NEXT: vle16.v v8, (a1)
-; ZVFBFMIN64-NEXT: addi sp, s0, -384
-; ZVFBFMIN64-NEXT: .cfi_def_cfa sp, 384
-; ZVFBFMIN64-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
-; ZVFBFMIN64-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
-; ZVFBFMIN64-NEXT: .cfi_restore ra
-; ZVFBFMIN64-NEXT: .cfi_restore s0
-; ZVFBFMIN64-NEXT: addi sp, sp, 384
-; ZVFBFMIN64-NEXT: .cfi_def_cfa_offset 0
-; ZVFBFMIN64-NEXT: ret
+; ZVFBFMIN-LABEL: v64bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: li a0, 64
+; ZVFBFMIN-NEXT: lui a1, 8
+; ZVFBFMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFBFMIN-NEXT: vxor.vx v8, v8, a1
+; ZVFBFMIN-NEXT: ret
%vb = fneg <64 x bfloat> %va
ret <64 x bfloat> %vb
}
@@ -649,481 +181,13 @@ define <32 x half> @v32f16(<32 x half> %va) {
}
define <64 x half> @v64f16(<64 x half> %va) {
-; ZVFHMIN32-LABEL: v64f16:
-; ZVFHMIN32: # %bb.0:
-; ZVFHMIN32-NEXT: addi sp, sp, -384
-; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 384
-; ZVFHMIN32-NEXT: sw ra, 380(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT: sw s0, 376(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT: .cfi_offset ra, -4
-; ZVFHMIN32-NEXT: .cfi_offset s0, -8
-; ZVFHMIN32-NEXT: addi s0, sp, 384
-; ZVFHMIN32-NEXT: .cfi_def_cfa s0, 0
-; ZVFHMIN32-NEXT: andi sp, sp, -128
-; ZVFHMIN32-NEXT: li a0, 64
-; ZVFHMIN32-NEXT: mv a1, sp
-; ZVFHMIN32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN32-NEXT: vse16.v v8, (a1)
-; ZVFHMIN32-NEXT: lh a2, 126(sp)
-; ZVFHMIN32-NEXT: lui a1, 8
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 254(sp)
-; ZVFHMIN32-NEXT: lh a2, 124(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 252(sp)
-; ZVFHMIN32-NEXT: lh a2, 122(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 250(sp)
-; ZVFHMIN32-NEXT: lh a2, 120(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 248(sp)
-; ZVFHMIN32-NEXT: lh a2, 118(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 246(sp)
-; ZVFHMIN32-NEXT: lh a2, 116(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 244(sp)
-; ZVFHMIN32-NEXT: lh a2, 114(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 242(sp)
-; ZVFHMIN32-NEXT: lh a2, 112(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 240(sp)
-; ZVFHMIN32-NEXT: lh a2, 110(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 238(sp)
-; ZVFHMIN32-NEXT: lh a2, 108(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 236(sp)
-; ZVFHMIN32-NEXT: lh a2, 106(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 234(sp)
-; ZVFHMIN32-NEXT: lh a2, 104(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 232(sp)
-; ZVFHMIN32-NEXT: lh a2, 102(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 230(sp)
-; ZVFHMIN32-NEXT: lh a2, 100(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 228(sp)
-; ZVFHMIN32-NEXT: lh a2, 98(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 226(sp)
-; ZVFHMIN32-NEXT: lh a2, 96(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 224(sp)
-; ZVFHMIN32-NEXT: lh a2, 94(sp)
-; ZVFHMIN32-NEXT: vmv.x.s a3, v8
-; ZVFHMIN32-NEXT: xor a3, a3, a1
-; ZVFHMIN32-NEXT: sh a3, 128(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 222(sp)
-; ZVFHMIN32-NEXT: lh a2, 92(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 220(sp)
-; ZVFHMIN32-NEXT: lh a2, 90(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 218(sp)
-; ZVFHMIN32-NEXT: lh a2, 88(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 216(sp)
-; ZVFHMIN32-NEXT: lh a2, 86(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 214(sp)
-; ZVFHMIN32-NEXT: lh a2, 84(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 212(sp)
-; ZVFHMIN32-NEXT: lh a2, 82(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 210(sp)
-; ZVFHMIN32-NEXT: lh a2, 80(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 208(sp)
-; ZVFHMIN32-NEXT: lh a2, 78(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 206(sp)
-; ZVFHMIN32-NEXT: lh a2, 76(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 204(sp)
-; ZVFHMIN32-NEXT: lh a2, 74(sp)
-; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFHMIN32-NEXT: vslidedown.vi v10, v8, 7
-; ZVFHMIN32-NEXT: vslidedown.vi v11, v8, 6
-; ZVFHMIN32-NEXT: vslidedown.vi v12, v8, 5
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 202(sp)
-; ZVFHMIN32-NEXT: lh a2, 72(sp)
-; ZVFHMIN32-NEXT: vslidedown.vi v13, v8, 4
-; ZVFHMIN32-NEXT: vslidedown.vi v14, v8, 3
-; ZVFHMIN32-NEXT: vslidedown.vi v15, v8, 2
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 200(sp)
-; ZVFHMIN32-NEXT: lh a2, 70(sp)
-; ZVFHMIN32-NEXT: vslidedown.vi v16, v8, 1
-; ZVFHMIN32-NEXT: vmv.x.s a3, v10
-; ZVFHMIN32-NEXT: vmv.x.s a4, v11
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 198(sp)
-; ZVFHMIN32-NEXT: lh a2, 68(sp)
-; ZVFHMIN32-NEXT: vmv.x.s a5, v12
-; ZVFHMIN32-NEXT: vmv.x.s a6, v13
-; ZVFHMIN32-NEXT: vmv.x.s a7, v14
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 196(sp)
-; ZVFHMIN32-NEXT: lh a2, 66(sp)
-; ZVFHMIN32-NEXT: vmv.x.s t0, v15
-; ZVFHMIN32-NEXT: vmv.x.s t1, v16
-; ZVFHMIN32-NEXT: xor a3, a3, a1
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 194(sp)
-; ZVFHMIN32-NEXT: lh a2, 64(sp)
-; ZVFHMIN32-NEXT: xor a4, a4, a1
-; ZVFHMIN32-NEXT: xor a5, a5, a1
-; ZVFHMIN32-NEXT: xor a6, a6, a1
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 192(sp)
-; ZVFHMIN32-NEXT: lh a2, 62(sp)
-; ZVFHMIN32-NEXT: xor a7, a7, a1
-; ZVFHMIN32-NEXT: xor t0, t0, a1
-; ZVFHMIN32-NEXT: xor t1, t1, a1
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 190(sp)
-; ZVFHMIN32-NEXT: lh a2, 60(sp)
-; ZVFHMIN32-NEXT: sh t1, 130(sp)
-; ZVFHMIN32-NEXT: sh t0, 132(sp)
-; ZVFHMIN32-NEXT: sh a7, 134(sp)
-; ZVFHMIN32-NEXT: sh a6, 136(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a5, 138(sp)
-; ZVFHMIN32-NEXT: sh a4, 140(sp)
-; ZVFHMIN32-NEXT: sh a3, 142(sp)
-; ZVFHMIN32-NEXT: sh a2, 188(sp)
-; ZVFHMIN32-NEXT: lh a2, 58(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 186(sp)
-; ZVFHMIN32-NEXT: lh a2, 56(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 184(sp)
-; ZVFHMIN32-NEXT: lh a2, 54(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 182(sp)
-; ZVFHMIN32-NEXT: lh a2, 52(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 180(sp)
-; ZVFHMIN32-NEXT: lh a2, 50(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 178(sp)
-; ZVFHMIN32-NEXT: lh a2, 48(sp)
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 176(sp)
-; ZVFHMIN32-NEXT: lh a2, 46(sp)
-; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
-; ZVFHMIN32-NEXT: vslidedown.vi v10, v8, 15
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 174(sp)
-; ZVFHMIN32-NEXT: lh a2, 44(sp)
-; ZVFHMIN32-NEXT: vslidedown.vi v12, v8, 14
-; ZVFHMIN32-NEXT: vslidedown.vi v14, v8, 13
-; ZVFHMIN32-NEXT: vslidedown.vi v16, v8, 12
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 172(sp)
-; ZVFHMIN32-NEXT: lh a2, 42(sp)
-; ZVFHMIN32-NEXT: vslidedown.vi v18, v8, 11
-; ZVFHMIN32-NEXT: vslidedown.vi v20, v8, 10
-; ZVFHMIN32-NEXT: vslidedown.vi v22, v8, 9
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 170(sp)
-; ZVFHMIN32-NEXT: lh a2, 40(sp)
-; ZVFHMIN32-NEXT: vslidedown.vi v8, v8, 8
-; ZVFHMIN32-NEXT: vmv.x.s a3, v10
-; ZVFHMIN32-NEXT: vmv.x.s a4, v12
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 168(sp)
-; ZVFHMIN32-NEXT: lh a2, 38(sp)
-; ZVFHMIN32-NEXT: vmv.x.s a5, v14
-; ZVFHMIN32-NEXT: vmv.x.s a6, v16
-; ZVFHMIN32-NEXT: vmv.x.s a7, v18
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 166(sp)
-; ZVFHMIN32-NEXT: lh a2, 36(sp)
-; ZVFHMIN32-NEXT: vmv.x.s t0, v20
-; ZVFHMIN32-NEXT: vmv.x.s t1, v22
-; ZVFHMIN32-NEXT: xor a3, a3, a1
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 164(sp)
-; ZVFHMIN32-NEXT: lh a2, 34(sp)
-; ZVFHMIN32-NEXT: xor a4, a4, a1
-; ZVFHMIN32-NEXT: xor a5, a5, a1
-; ZVFHMIN32-NEXT: xor a6, a6, a1
-; ZVFHMIN32-NEXT: xor a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 162(sp)
-; ZVFHMIN32-NEXT: lh a2, 32(sp)
-; ZVFHMIN32-NEXT: sh a6, 152(sp)
-; ZVFHMIN32-NEXT: sh a5, 154(sp)
-; ZVFHMIN32-NEXT: sh a4, 156(sp)
-; ZVFHMIN32-NEXT: sh a3, 158(sp)
-; ZVFHMIN32-NEXT: vmv.x.s a3, v8
-; ZVFHMIN32-NEXT: xor a4, a7, a1
-; ZVFHMIN32-NEXT: xor a5, t0, a1
-; ZVFHMIN32-NEXT: xor a6, t1, a1
-; ZVFHMIN32-NEXT: xor a3, a3, a1
-; ZVFHMIN32-NEXT: sh a3, 144(sp)
-; ZVFHMIN32-NEXT: sh a6, 146(sp)
-; ZVFHMIN32-NEXT: sh a5, 148(sp)
-; ZVFHMIN32-NEXT: sh a4, 150(sp)
-; ZVFHMIN32-NEXT: xor a1, a2, a1
-; ZVFHMIN32-NEXT: sh a1, 160(sp)
-; ZVFHMIN32-NEXT: addi a1, sp, 128
-; ZVFHMIN32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN32-NEXT: vle16.v v8, (a1)
-; ZVFHMIN32-NEXT: addi sp, s0, -384
-; ZVFHMIN32-NEXT: .cfi_def_cfa sp, 384
-; ZVFHMIN32-NEXT: lw ra, 380(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT: lw s0, 376(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT: .cfi_restore ra
-; ZVFHMIN32-NEXT: .cfi_restore s0
-; ZVFHMIN32-NEXT: addi sp, sp, 384
-; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 0
-; ZVFHMIN32-NEXT: ret
-;
-; ZVFHMIN64-LABEL: v64f16:
-; ZVFHMIN64: # %bb.0:
-; ZVFHMIN64-NEXT: addi sp, sp, -384
-; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 384
-; ZVFHMIN64-NEXT: sd ra, 376(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT: sd s0, 368(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT: .cfi_offset ra, -8
-; ZVFHMIN64-NEXT: .cfi_offset s0, -16
-; ZVFHMIN64-NEXT: addi s0, sp, 384
-; ZVFHMIN64-NEXT: .cfi_def_cfa s0, 0
-; ZVFHMIN64-NEXT: andi sp, sp, -128
-; ZVFHMIN64-NEXT: li a0, 64
-; ZVFHMIN64-NEXT: mv a1, sp
-; ZVFHMIN64-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN64-NEXT: vse16.v v8, (a1)
-; ZVFHMIN64-NEXT: lh a2, 126(sp)
-; ZVFHMIN64-NEXT: lui a1, 8
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 254(sp)
-; ZVFHMIN64-NEXT: lh a2, 124(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 252(sp)
-; ZVFHMIN64-NEXT: lh a2, 122(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 250(sp)
-; ZVFHMIN64-NEXT: lh a2, 120(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 248(sp)
-; ZVFHMIN64-NEXT: lh a2, 118(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 246(sp)
-; ZVFHMIN64-NEXT: lh a2, 116(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 244(sp)
-; ZVFHMIN64-NEXT: lh a2, 114(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 242(sp)
-; ZVFHMIN64-NEXT: lh a2, 112(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 240(sp)
-; ZVFHMIN64-NEXT: lh a2, 110(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 238(sp)
-; ZVFHMIN64-NEXT: lh a2, 108(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 236(sp)
-; ZVFHMIN64-NEXT: lh a2, 106(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 234(sp)
-; ZVFHMIN64-NEXT: lh a2, 104(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 232(sp)
-; ZVFHMIN64-NEXT: lh a2, 102(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 230(sp)
-; ZVFHMIN64-NEXT: lh a2, 100(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 228(sp)
-; ZVFHMIN64-NEXT: lh a2, 98(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 226(sp)
-; ZVFHMIN64-NEXT: lh a2, 96(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 224(sp)
-; ZVFHMIN64-NEXT: lh a2, 94(sp)
-; ZVFHMIN64-NEXT: vmv.x.s a3, v8
-; ZVFHMIN64-NEXT: xor a3, a3, a1
-; ZVFHMIN64-NEXT: sh a3, 128(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 222(sp)
-; ZVFHMIN64-NEXT: lh a2, 92(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 220(sp)
-; ZVFHMIN64-NEXT: lh a2, 90(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 218(sp)
-; ZVFHMIN64-NEXT: lh a2, 88(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 216(sp)
-; ZVFHMIN64-NEXT: lh a2, 86(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 214(sp)
-; ZVFHMIN64-NEXT: lh a2, 84(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 212(sp)
-; ZVFHMIN64-NEXT: lh a2, 82(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 210(sp)
-; ZVFHMIN64-NEXT: lh a2, 80(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 208(sp)
-; ZVFHMIN64-NEXT: lh a2, 78(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 206(sp)
-; ZVFHMIN64-NEXT: lh a2, 76(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 204(sp)
-; ZVFHMIN64-NEXT: lh a2, 74(sp)
-; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFHMIN64-NEXT: vslidedown.vi v10, v8, 7
-; ZVFHMIN64-NEXT: vslidedown.vi v11, v8, 6
-; ZVFHMIN64-NEXT: vslidedown.vi v12, v8, 5
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 202(sp)
-; ZVFHMIN64-NEXT: lh a2, 72(sp)
-; ZVFHMIN64-NEXT: vslidedown.vi v13, v8, 4
-; ZVFHMIN64-NEXT: vslidedown.vi v14, v8, 3
-; ZVFHMIN64-NEXT: vslidedown.vi v15, v8, 2
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 200(sp)
-; ZVFHMIN64-NEXT: lh a2, 70(sp)
-; ZVFHMIN64-NEXT: vslidedown.vi v16, v8, 1
-; ZVFHMIN64-NEXT: vmv.x.s a3, v10
-; ZVFHMIN64-NEXT: vmv.x.s a4, v11
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 198(sp)
-; ZVFHMIN64-NEXT: lh a2, 68(sp)
-; ZVFHMIN64-NEXT: vmv.x.s a5, v12
-; ZVFHMIN64-NEXT: vmv.x.s a6, v13
-; ZVFHMIN64-NEXT: vmv.x.s a7, v14
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 196(sp)
-; ZVFHMIN64-NEXT: lh a2, 66(sp)
-; ZVFHMIN64-NEXT: vmv.x.s t0, v15
-; ZVFHMIN64-NEXT: vmv.x.s t1, v16
-; ZVFHMIN64-NEXT: xor a3, a3, a1
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 194(sp)
-; ZVFHMIN64-NEXT: lh a2, 64(sp)
-; ZVFHMIN64-NEXT: xor a4, a4, a1
-; ZVFHMIN64-NEXT: xor a5, a5, a1
-; ZVFHMIN64-NEXT: xor a6, a6, a1
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 192(sp)
-; ZVFHMIN64-NEXT: lh a2, 62(sp)
-; ZVFHMIN64-NEXT: xor a7, a7, a1
-; ZVFHMIN64-NEXT: xor t0, t0, a1
-; ZVFHMIN64-NEXT: xor t1, t1, a1
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 190(sp)
-; ZVFHMIN64-NEXT: lh a2, 60(sp)
-; ZVFHMIN64-NEXT: sh t1, 130(sp)
-; ZVFHMIN64-NEXT: sh t0, 132(sp)
-; ZVFHMIN64-NEXT: sh a7, 134(sp)
-; ZVFHMIN64-NEXT: sh a6, 136(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a5, 138(sp)
-; ZVFHMIN64-NEXT: sh a4, 140(sp)
-; ZVFHMIN64-NEXT: sh a3, 142(sp)
-; ZVFHMIN64-NEXT: sh a2, 188(sp)
-; ZVFHMIN64-NEXT: lh a2, 58(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 186(sp)
-; ZVFHMIN64-NEXT: lh a2, 56(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 184(sp)
-; ZVFHMIN64-NEXT: lh a2, 54(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 182(sp)
-; ZVFHMIN64-NEXT: lh a2, 52(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 180(sp)
-; ZVFHMIN64-NEXT: lh a2, 50(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 178(sp)
-; ZVFHMIN64-NEXT: lh a2, 48(sp)
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 176(sp)
-; ZVFHMIN64-NEXT: lh a2, 46(sp)
-; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
-; ZVFHMIN64-NEXT: vslidedown.vi v10, v8, 15
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 174(sp)
-; ZVFHMIN64-NEXT: lh a2, 44(sp)
-; ZVFHMIN64-NEXT: vslidedown.vi v12, v8, 14
-; ZVFHMIN64-NEXT: vslidedown.vi v14, v8, 13
-; ZVFHMIN64-NEXT: vslidedown.vi v16, v8, 12
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 172(sp)
-; ZVFHMIN64-NEXT: lh a2, 42(sp)
-; ZVFHMIN64-NEXT: vslidedown.vi v18, v8, 11
-; ZVFHMIN64-NEXT: vslidedown.vi v20, v8, 10
-; ZVFHMIN64-NEXT: vslidedown.vi v22, v8, 9
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 170(sp)
-; ZVFHMIN64-NEXT: lh a2, 40(sp)
-; ZVFHMIN64-NEXT: vslidedown.vi v8, v8, 8
-; ZVFHMIN64-NEXT: vmv.x.s a3, v10
-; ZVFHMIN64-NEXT: vmv.x.s a4, v12
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 168(sp)
-; ZVFHMIN64-NEXT: lh a2, 38(sp)
-; ZVFHMIN64-NEXT: vmv.x.s a5, v14
-; ZVFHMIN64-NEXT: vmv.x.s a6, v16
-; ZVFHMIN64-NEXT: vmv.x.s a7, v18
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 166(sp)
-; ZVFHMIN64-NEXT: lh a2, 36(sp)
-; ZVFHMIN64-NEXT: vmv.x.s t0, v20
-; ZVFHMIN64-NEXT: vmv.x.s t1, v22
-; ZVFHMIN64-NEXT: xor a3, a3, a1
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 164(sp)
-; ZVFHMIN64-NEXT: lh a2, 34(sp)
-; ZVFHMIN64-NEXT: xor a4, a4, a1
-; ZVFHMIN64-NEXT: xor a5, a5, a1
-; ZVFHMIN64-NEXT: xor a6, a6, a1
-; ZVFHMIN64-NEXT: xor a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 162(sp)
-; ZVFHMIN64-NEXT: lh a2, 32(sp)
-; ZVFHMIN64-NEXT: sh a6, 152(sp)
-; ZVFHMIN64-NEXT: sh a5, 154(sp)
-; ZVFHMIN64-NEXT: sh a4, 156(sp)
-; ZVFHMIN64-NEXT: sh a3, 158(sp)
-; ZVFHMIN64-NEXT: vmv.x.s a3, v8
-; ZVFHMIN64-NEXT: xor a4, a7, a1
-; ZVFHMIN64-NEXT: xor a5, t0, a1
-; ZVFHMIN64-NEXT: xor a6, t1, a1
-; ZVFHMIN64-NEXT: xor a3, a3, a1
-; ZVFHMIN64-NEXT: sh a3, 144(sp)
-; ZVFHMIN64-NEXT: sh a6, 146(sp)
-; ZVFHMIN64-NEXT: sh a5, 148(sp)
-; ZVFHMIN64-NEXT: sh a4, 150(sp)
-; ZVFHMIN64-NEXT: xor a1, a2, a1
-; ZVFHMIN64-NEXT: sh a1, 160(sp)
-; ZVFHMIN64-NEXT: addi a1, sp, 128
-; ZVFHMIN64-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN64-NEXT: vle16.v v8, (a1)
-; ZVFHMIN64-NEXT: addi sp, s0, -384
-; ZVFHMIN64-NEXT: .cfi_def_cfa sp, 384
-; ZVFHMIN64-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT: .cfi_restore ra
-; ZVFHMIN64-NEXT: .cfi_restore s0
-; ZVFHMIN64-NEXT: addi sp, sp, 384
-; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 0
-; ZVFHMIN64-NEXT: ret
+; CHECK-LABEL: v64f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a0, 64
+; CHECK-NEXT: lui a1, 8
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: vxor.vx v8, v8, a1
+; CHECK-NEXT: ret
%vb = fneg <64 x half> %va
ret <64 x half> %vb
}
diff --git a/llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll b/llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll
index 0e993f35ce85d..8b8b897a32eda 100644
--- a/llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll
@@ -5,22 +5,8 @@
define arm_aapcs_vfpcc <8 x half> @fneg_float16_t(<8 x half> %src) {
; CHECK-MVE-LABEL: fneg_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vmovx.f16 s4, s0
-; CHECK-MVE-NEXT: vneg.f16 s0, s0
-; CHECK-MVE-NEXT: vneg.f16 s4, s4
-; CHECK-MVE-NEXT: vins.f16 s0, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s1
-; CHECK-MVE-NEXT: vneg.f16 s4, s4
-; CHECK-MVE-NEXT: vneg.f16 s1, s1
-; CHECK-MVE-NEXT: vins.f16 s1, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s2
-; CHECK-MVE-NEXT: vneg.f16 s4, s4
-; CHECK-MVE-NEXT: vneg.f16 s2, s2
-; CHECK-MVE-NEXT: vins.f16 s2, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s3
-; CHECK-MVE-NEXT: vneg.f16 s4, s4
-; CHECK-MVE-NEXT: vneg.f16 s3, s3
-; CHECK-MVE-NEXT: vins.f16 s3, s4
+; CHECK-MVE-NEXT: vmov.i16 q1, #0x8000
+; CHECK-MVE-NEXT: veor q0, q0, q1
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: fneg_float16_t:
@@ -35,10 +21,8 @@ entry:
define arm_aapcs_vfpcc <4 x float> @fneg_float32_t(<4 x float> %src) {
; CHECK-MVE-LABEL: fneg_float32_t:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vneg.f32 s3, s3
-; CHECK-MVE-NEXT: vneg.f32 s2, s2
-; CHECK-MVE-NEXT: vneg.f32 s1, s1
-; CHECK-MVE-NEXT: vneg.f32 s0, s0
+; CHECK-MVE-NEXT: vmov.i32 q1, #0x80000000
+; CHECK-MVE-NEXT: veor q0, q0, q1
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: fneg_float32_t:
@@ -53,20 +37,17 @@ entry:
define arm_aapcs_vfpcc <2 x double> @fneg_float64_t(<2 x double> %src) {
; CHECK-LABEL: fneg_float64_t:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .pad #16
-; CHECK-NEXT: sub sp, #16
-; CHECK-NEXT: vstr d1, [sp]
-; CHECK-NEXT: ldrb.w r0, [sp, #7]
-; CHECK-NEXT: vstr d0, [sp, #8]
-; CHECK-NEXT: ldrb.w r1, [sp, #15]
-; CHECK-NEXT: eor r0, r0, #128
-; CHECK-NEXT: strb.w r0, [sp, #7]
-; CHECK-NEXT: vldr d1, [sp]
-; CHECK-NEXT: eor r0, r1, #128
-; CHECK-NEXT: strb.w r0, [sp, #15]
-; CHECK-NEXT: vldr d0, [sp, #8]
-; CHECK-NEXT: add sp, #16
+; CHECK-NEXT: adr r0, .LCPI2_0
+; CHECK-NEXT: vldrw.u32 q1, [r0]
+; CHECK-NEXT: veor q0, q0, q1
; CHECK-NEXT: bx lr
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: @ %bb.1:
+; CHECK-NEXT: .LCPI2_0:
+; CHECK-NEXT: .long 0 @ 0x0
+; CHECK-NEXT: .long 2147483648 @ 0x80000000
+; CHECK-NEXT: .long 0 @ 0x0
+; CHECK-NEXT: .long 2147483648 @ 0x80000000
entry:
%0 = fsub nnan ninf nsz <2 x double> <double 0.0e0, double 0.0e0>, %src
ret <2 x double> %0
>From dc9cb3e73a21d1d5f9aeaf6c3f9f536404f81cb4 Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Wed, 29 Apr 2026 17:08:43 +0800
Subject: [PATCH 3/3] fixup! revise heuristic
---
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index 9544fe580c4a3..106739147d213 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -2067,12 +2067,14 @@ SDValue VectorLegalizer::ExpandFNEG(SDNode *Node) {
// a. Vector only has 1 element and target knows how to handle scalar
// FNEG (either legal or custom expand or promote).
// b. Vector has more than 1 element and target supports scalar
- // FNEG natively and vector length <= 3 (2 AND + 1 OR).
+ // FNEG natively and vector length <= 2(1 XOR + 1 CONST).
+ // FIXME: Scalar construction instruction count varies in every architecture,
+ // here we assume 1 instruction for now.
if (VT.isFixedLengthVector()) {
EVT EltVT = VT.getVectorElementType();
if ((VT.getVectorNumElements() == 1 &&
TLI.isOperationLegalOrCustomOrPromote(ISD::FNEG, EltVT)) ||
- (VT.getVectorNumElements() < 4 &&
+ (VT.getVectorNumElements() < 3 &&
TLI.isOperationLegal(ISD::FNEG, EltVT) &&
TLI.isExtractVecEltCheap(VT, 0)))
return SDValue();
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