[llvm] [llvm][RISCV] Optimize fabs for fixed vectors (PR #194554)
Brandon Wu via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 29 08:36:24 PDT 2026
https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/194554
>From 469b510cd9af0a997cc416c8bd8ffb02209a7687 Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Tue, 28 Apr 2026 13:56:56 +0800
Subject: [PATCH 1/3] pre commit test
---
.../RISCV/rvv/fixed-vectors-vfabs-sdnode.ll | 1147 ++++++++++++++++-
1 file changed, 1112 insertions(+), 35 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-sdnode.ll
index 27c00de3c3487..4db2d1a09cffe 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-sdnode.ll
@@ -1,66 +1,1143 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfa,+v \
-; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfa,+v \
-; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+experimental-zvfbfa \
+; RUN: -target-abi=ilp32d -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFA,ZVFHMIN32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+experimental-zvfbfa \
+; RUN: -target-abi=lp64d -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFA,ZVFHMIN64
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin -target-abi=ilp32d \
+; RUN: -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFHMIN32,ZVFBFMIN32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin -target-abi=lp64d \
+; RUN: -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFHMIN64,ZVFBFMIN64
define <1 x bfloat> @v1bf16(<1 x bfloat> %v) {
-; CHECK-LABEL: v1bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 1, e16alt, mf4, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
-; CHECK-NEXT: ret
+; ZVFBFA-LABEL: v1bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 1, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfabs.v v8, v8
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN-LABEL: v1bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 8
+; ZVFBFMIN-NEXT: addi a0, a0, -1
+; ZVFBFMIN-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vand.vx v8, v8, a0
+; ZVFBFMIN-NEXT: ret
%r = call <1 x bfloat> @llvm.fabs.v1bf16(<1 x bfloat> %v)
ret <1 x bfloat> %r
}
define <2 x bfloat> @v2bf16(<2 x bfloat> %v) {
-; CHECK-LABEL: v2bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
-; CHECK-NEXT: ret
+; ZVFBFA-LABEL: v2bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfabs.v v8, v8
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN-LABEL: v2bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 8
+; ZVFBFMIN-NEXT: addi a0, a0, -1
+; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFBFMIN-NEXT: vand.vx v8, v8, a0
+; ZVFBFMIN-NEXT: ret
%r = call <2 x bfloat> @llvm.fabs.v2bf16(<2 x bfloat> %v)
ret <2 x bfloat> %r
}
define <4 x bfloat> @v4bf16(<4 x bfloat> %v) {
-; CHECK-LABEL: v4bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
-; CHECK-NEXT: ret
+; ZVFBFA-LABEL: v4bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma
+; ZVFBFA-NEXT: vfabs.v v8, v8
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN-LABEL: v4bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 8
+; ZVFBFMIN-NEXT: addi a0, a0, -1
+; ZVFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFBFMIN-NEXT: vand.vx v8, v8, a0
+; ZVFBFMIN-NEXT: ret
%r = call <4 x bfloat> @llvm.fabs.v4bf16(<4 x bfloat> %v)
ret <4 x bfloat> %r
}
define <8 x bfloat> @v8bf16(<8 x bfloat> %v) {
-; CHECK-LABEL: v8bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16alt, m1, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
-; CHECK-NEXT: ret
+; ZVFBFA-LABEL: v8bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 8, e16alt, m1, ta, ma
+; ZVFBFA-NEXT: vfabs.v v8, v8
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN-LABEL: v8bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 8
+; ZVFBFMIN-NEXT: addi a0, a0, -1
+; ZVFBFMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFBFMIN-NEXT: vand.vx v8, v8, a0
+; ZVFBFMIN-NEXT: ret
%r = call <8 x bfloat> @llvm.fabs.v8bf16(<8 x bfloat> %v)
ret <8 x bfloat> %r
}
define <16 x bfloat> @v16bf16(<16 x bfloat> %v) {
-; CHECK-LABEL: v16bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e16alt, m2, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
-; CHECK-NEXT: ret
+; ZVFBFA-LABEL: v16bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 16, e16alt, m2, ta, ma
+; ZVFBFA-NEXT: vfabs.v v8, v8
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN-LABEL: v16bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 8
+; ZVFBFMIN-NEXT: addi a0, a0, -1
+; ZVFBFMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFBFMIN-NEXT: vand.vx v8, v8, a0
+; ZVFBFMIN-NEXT: ret
%r = call <16 x bfloat> @llvm.fabs.v16bf16(<16 x bfloat> %v)
ret <16 x bfloat> %r
}
define <32 x bfloat> @v32bf16(<32 x bfloat> %v) {
-; CHECK-LABEL: v32bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma
-; CHECK-NEXT: vfabs.v v8, v8
-; CHECK-NEXT: ret
+; ZVFBFA-LABEL: v32bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: li a0, 32
+; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfabs.v v8, v8
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN-LABEL: v32bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 8
+; ZVFBFMIN-NEXT: addi a0, a0, -1
+; ZVFBFMIN-NEXT: li a1, 32
+; ZVFBFMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFBFMIN-NEXT: vand.vx v8, v8, a0
+; ZVFBFMIN-NEXT: ret
%r = call <32 x bfloat> @llvm.fabs.v32bf16(<32 x bfloat> %v)
ret <32 x bfloat> %r
}
+
+define <64 x bfloat> @v64bf16(<64 x bfloat> %v) {
+; ZVFBFA-LABEL: v64bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: li a0, 64
+; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma
+; ZVFBFA-NEXT: vfabs.v v8, v8
+; ZVFBFA-NEXT: ret
+;
+; ZVFBFMIN32-LABEL: v64bf16:
+; ZVFBFMIN32: # %bb.0:
+; ZVFBFMIN32-NEXT: addi sp, sp, -384
+; ZVFBFMIN32-NEXT: .cfi_def_cfa_offset 384
+; ZVFBFMIN32-NEXT: sw ra, 380(sp) # 4-byte Folded Spill
+; ZVFBFMIN32-NEXT: sw s0, 376(sp) # 4-byte Folded Spill
+; ZVFBFMIN32-NEXT: .cfi_offset ra, -4
+; ZVFBFMIN32-NEXT: .cfi_offset s0, -8
+; ZVFBFMIN32-NEXT: addi s0, sp, 384
+; ZVFBFMIN32-NEXT: .cfi_def_cfa s0, 0
+; ZVFBFMIN32-NEXT: andi sp, sp, -128
+; ZVFBFMIN32-NEXT: li a0, 64
+; ZVFBFMIN32-NEXT: mv a1, sp
+; ZVFBFMIN32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFBFMIN32-NEXT: vse16.v v8, (a1)
+; ZVFBFMIN32-NEXT: lhu a2, 126(sp)
+; ZVFBFMIN32-NEXT: lui a1, 8
+; ZVFBFMIN32-NEXT: addi a1, a1, -1
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 254(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 124(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 252(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 122(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 250(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 120(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 248(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 118(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 246(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 116(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 244(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 114(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 242(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 112(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 240(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 110(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 238(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 108(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 236(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 106(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 234(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 104(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 232(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 102(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 230(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 100(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 228(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 98(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 226(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 96(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 224(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 94(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s a3, v8
+; ZVFBFMIN32-NEXT: and a3, a3, a1
+; ZVFBFMIN32-NEXT: sh a3, 128(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 222(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 92(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 220(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 90(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 218(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 88(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 216(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 86(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 214(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 84(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 212(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 82(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 210(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 80(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 208(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 78(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 206(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 76(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 204(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 74(sp)
+; ZVFBFMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFBFMIN32-NEXT: vslidedown.vi v10, v8, 7
+; ZVFBFMIN32-NEXT: vslidedown.vi v11, v8, 6
+; ZVFBFMIN32-NEXT: vslidedown.vi v12, v8, 5
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 202(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 72(sp)
+; ZVFBFMIN32-NEXT: vslidedown.vi v13, v8, 4
+; ZVFBFMIN32-NEXT: vslidedown.vi v14, v8, 3
+; ZVFBFMIN32-NEXT: vslidedown.vi v15, v8, 2
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 200(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 70(sp)
+; ZVFBFMIN32-NEXT: vslidedown.vi v16, v8, 1
+; ZVFBFMIN32-NEXT: vmv.x.s a3, v10
+; ZVFBFMIN32-NEXT: vmv.x.s a4, v11
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 198(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 68(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s a5, v12
+; ZVFBFMIN32-NEXT: vmv.x.s a6, v13
+; ZVFBFMIN32-NEXT: vmv.x.s a7, v14
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 196(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 66(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s t0, v15
+; ZVFBFMIN32-NEXT: vmv.x.s t1, v16
+; ZVFBFMIN32-NEXT: and a3, a3, a1
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 194(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 64(sp)
+; ZVFBFMIN32-NEXT: and a4, a4, a1
+; ZVFBFMIN32-NEXT: and a5, a5, a1
+; ZVFBFMIN32-NEXT: and a6, a6, a1
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 192(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 62(sp)
+; ZVFBFMIN32-NEXT: and a7, a7, a1
+; ZVFBFMIN32-NEXT: and t0, t0, a1
+; ZVFBFMIN32-NEXT: and t1, t1, a1
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 190(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 60(sp)
+; ZVFBFMIN32-NEXT: sh t1, 130(sp)
+; ZVFBFMIN32-NEXT: sh t0, 132(sp)
+; ZVFBFMIN32-NEXT: sh a7, 134(sp)
+; ZVFBFMIN32-NEXT: sh a6, 136(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a5, 138(sp)
+; ZVFBFMIN32-NEXT: sh a4, 140(sp)
+; ZVFBFMIN32-NEXT: sh a3, 142(sp)
+; ZVFBFMIN32-NEXT: sh a2, 188(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 58(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 186(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 56(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 184(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 54(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 182(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 52(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 180(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 50(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 178(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 48(sp)
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 176(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 46(sp)
+; ZVFBFMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFBFMIN32-NEXT: vslidedown.vi v10, v8, 15
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 174(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 44(sp)
+; ZVFBFMIN32-NEXT: vslidedown.vi v12, v8, 14
+; ZVFBFMIN32-NEXT: vslidedown.vi v14, v8, 13
+; ZVFBFMIN32-NEXT: vslidedown.vi v16, v8, 12
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 172(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 42(sp)
+; ZVFBFMIN32-NEXT: vslidedown.vi v18, v8, 11
+; ZVFBFMIN32-NEXT: vslidedown.vi v20, v8, 10
+; ZVFBFMIN32-NEXT: vslidedown.vi v22, v8, 9
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 170(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 40(sp)
+; ZVFBFMIN32-NEXT: vslidedown.vi v8, v8, 8
+; ZVFBFMIN32-NEXT: vmv.x.s a3, v10
+; ZVFBFMIN32-NEXT: vmv.x.s a4, v12
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 168(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 38(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s a5, v14
+; ZVFBFMIN32-NEXT: vmv.x.s a6, v16
+; ZVFBFMIN32-NEXT: vmv.x.s a7, v18
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 166(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 36(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s t0, v20
+; ZVFBFMIN32-NEXT: vmv.x.s t1, v22
+; ZVFBFMIN32-NEXT: and a3, a3, a1
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 164(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 34(sp)
+; ZVFBFMIN32-NEXT: and a4, a4, a1
+; ZVFBFMIN32-NEXT: and a5, a5, a1
+; ZVFBFMIN32-NEXT: and a6, a6, a1
+; ZVFBFMIN32-NEXT: and a2, a2, a1
+; ZVFBFMIN32-NEXT: sh a2, 162(sp)
+; ZVFBFMIN32-NEXT: lhu a2, 32(sp)
+; ZVFBFMIN32-NEXT: sh a6, 152(sp)
+; ZVFBFMIN32-NEXT: sh a5, 154(sp)
+; ZVFBFMIN32-NEXT: sh a4, 156(sp)
+; ZVFBFMIN32-NEXT: sh a3, 158(sp)
+; ZVFBFMIN32-NEXT: vmv.x.s a3, v8
+; ZVFBFMIN32-NEXT: and a4, a7, a1
+; ZVFBFMIN32-NEXT: and a5, t0, a1
+; ZVFBFMIN32-NEXT: and a6, t1, a1
+; ZVFBFMIN32-NEXT: and a3, a3, a1
+; ZVFBFMIN32-NEXT: sh a3, 144(sp)
+; ZVFBFMIN32-NEXT: sh a6, 146(sp)
+; ZVFBFMIN32-NEXT: sh a5, 148(sp)
+; ZVFBFMIN32-NEXT: sh a4, 150(sp)
+; ZVFBFMIN32-NEXT: and a1, a2, a1
+; ZVFBFMIN32-NEXT: sh a1, 160(sp)
+; ZVFBFMIN32-NEXT: addi a1, sp, 128
+; ZVFBFMIN32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFBFMIN32-NEXT: vle16.v v8, (a1)
+; ZVFBFMIN32-NEXT: addi sp, s0, -384
+; ZVFBFMIN32-NEXT: .cfi_def_cfa sp, 384
+; ZVFBFMIN32-NEXT: lw ra, 380(sp) # 4-byte Folded Reload
+; ZVFBFMIN32-NEXT: lw s0, 376(sp) # 4-byte Folded Reload
+; ZVFBFMIN32-NEXT: .cfi_restore ra
+; ZVFBFMIN32-NEXT: .cfi_restore s0
+; ZVFBFMIN32-NEXT: addi sp, sp, 384
+; ZVFBFMIN32-NEXT: .cfi_def_cfa_offset 0
+; ZVFBFMIN32-NEXT: ret
+;
+; ZVFBFMIN64-LABEL: v64bf16:
+; ZVFBFMIN64: # %bb.0:
+; ZVFBFMIN64-NEXT: addi sp, sp, -384
+; ZVFBFMIN64-NEXT: .cfi_def_cfa_offset 384
+; ZVFBFMIN64-NEXT: sd ra, 376(sp) # 8-byte Folded Spill
+; ZVFBFMIN64-NEXT: sd s0, 368(sp) # 8-byte Folded Spill
+; ZVFBFMIN64-NEXT: .cfi_offset ra, -8
+; ZVFBFMIN64-NEXT: .cfi_offset s0, -16
+; ZVFBFMIN64-NEXT: addi s0, sp, 384
+; ZVFBFMIN64-NEXT: .cfi_def_cfa s0, 0
+; ZVFBFMIN64-NEXT: andi sp, sp, -128
+; ZVFBFMIN64-NEXT: li a0, 64
+; ZVFBFMIN64-NEXT: mv a1, sp
+; ZVFBFMIN64-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFBFMIN64-NEXT: vse16.v v8, (a1)
+; ZVFBFMIN64-NEXT: lhu a2, 126(sp)
+; ZVFBFMIN64-NEXT: lui a1, 8
+; ZVFBFMIN64-NEXT: addi a1, a1, -1
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 254(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 124(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 252(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 122(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 250(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 120(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 248(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 118(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 246(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 116(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 244(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 114(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 242(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 112(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 240(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 110(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 238(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 108(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 236(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 106(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 234(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 104(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 232(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 102(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 230(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 100(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 228(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 98(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 226(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 96(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 224(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 94(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s a3, v8
+; ZVFBFMIN64-NEXT: and a3, a3, a1
+; ZVFBFMIN64-NEXT: sh a3, 128(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 222(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 92(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 220(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 90(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 218(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 88(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 216(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 86(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 214(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 84(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 212(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 82(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 210(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 80(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 208(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 78(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 206(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 76(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 204(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 74(sp)
+; ZVFBFMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFBFMIN64-NEXT: vslidedown.vi v10, v8, 7
+; ZVFBFMIN64-NEXT: vslidedown.vi v11, v8, 6
+; ZVFBFMIN64-NEXT: vslidedown.vi v12, v8, 5
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 202(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 72(sp)
+; ZVFBFMIN64-NEXT: vslidedown.vi v13, v8, 4
+; ZVFBFMIN64-NEXT: vslidedown.vi v14, v8, 3
+; ZVFBFMIN64-NEXT: vslidedown.vi v15, v8, 2
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 200(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 70(sp)
+; ZVFBFMIN64-NEXT: vslidedown.vi v16, v8, 1
+; ZVFBFMIN64-NEXT: vmv.x.s a3, v10
+; ZVFBFMIN64-NEXT: vmv.x.s a4, v11
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 198(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 68(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s a5, v12
+; ZVFBFMIN64-NEXT: vmv.x.s a6, v13
+; ZVFBFMIN64-NEXT: vmv.x.s a7, v14
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 196(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 66(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s t0, v15
+; ZVFBFMIN64-NEXT: vmv.x.s t1, v16
+; ZVFBFMIN64-NEXT: and a3, a3, a1
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 194(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 64(sp)
+; ZVFBFMIN64-NEXT: and a4, a4, a1
+; ZVFBFMIN64-NEXT: and a5, a5, a1
+; ZVFBFMIN64-NEXT: and a6, a6, a1
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 192(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 62(sp)
+; ZVFBFMIN64-NEXT: and a7, a7, a1
+; ZVFBFMIN64-NEXT: and t0, t0, a1
+; ZVFBFMIN64-NEXT: and t1, t1, a1
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 190(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 60(sp)
+; ZVFBFMIN64-NEXT: sh t1, 130(sp)
+; ZVFBFMIN64-NEXT: sh t0, 132(sp)
+; ZVFBFMIN64-NEXT: sh a7, 134(sp)
+; ZVFBFMIN64-NEXT: sh a6, 136(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a5, 138(sp)
+; ZVFBFMIN64-NEXT: sh a4, 140(sp)
+; ZVFBFMIN64-NEXT: sh a3, 142(sp)
+; ZVFBFMIN64-NEXT: sh a2, 188(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 58(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 186(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 56(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 184(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 54(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 182(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 52(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 180(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 50(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 178(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 48(sp)
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 176(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 46(sp)
+; ZVFBFMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFBFMIN64-NEXT: vslidedown.vi v10, v8, 15
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 174(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 44(sp)
+; ZVFBFMIN64-NEXT: vslidedown.vi v12, v8, 14
+; ZVFBFMIN64-NEXT: vslidedown.vi v14, v8, 13
+; ZVFBFMIN64-NEXT: vslidedown.vi v16, v8, 12
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 172(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 42(sp)
+; ZVFBFMIN64-NEXT: vslidedown.vi v18, v8, 11
+; ZVFBFMIN64-NEXT: vslidedown.vi v20, v8, 10
+; ZVFBFMIN64-NEXT: vslidedown.vi v22, v8, 9
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 170(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 40(sp)
+; ZVFBFMIN64-NEXT: vslidedown.vi v8, v8, 8
+; ZVFBFMIN64-NEXT: vmv.x.s a3, v10
+; ZVFBFMIN64-NEXT: vmv.x.s a4, v12
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 168(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 38(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s a5, v14
+; ZVFBFMIN64-NEXT: vmv.x.s a6, v16
+; ZVFBFMIN64-NEXT: vmv.x.s a7, v18
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 166(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 36(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s t0, v20
+; ZVFBFMIN64-NEXT: vmv.x.s t1, v22
+; ZVFBFMIN64-NEXT: and a3, a3, a1
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 164(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 34(sp)
+; ZVFBFMIN64-NEXT: and a4, a4, a1
+; ZVFBFMIN64-NEXT: and a5, a5, a1
+; ZVFBFMIN64-NEXT: and a6, a6, a1
+; ZVFBFMIN64-NEXT: and a2, a2, a1
+; ZVFBFMIN64-NEXT: sh a2, 162(sp)
+; ZVFBFMIN64-NEXT: lhu a2, 32(sp)
+; ZVFBFMIN64-NEXT: sh a6, 152(sp)
+; ZVFBFMIN64-NEXT: sh a5, 154(sp)
+; ZVFBFMIN64-NEXT: sh a4, 156(sp)
+; ZVFBFMIN64-NEXT: sh a3, 158(sp)
+; ZVFBFMIN64-NEXT: vmv.x.s a3, v8
+; ZVFBFMIN64-NEXT: and a4, a7, a1
+; ZVFBFMIN64-NEXT: and a5, t0, a1
+; ZVFBFMIN64-NEXT: and a6, t1, a1
+; ZVFBFMIN64-NEXT: and a3, a3, a1
+; ZVFBFMIN64-NEXT: sh a3, 144(sp)
+; ZVFBFMIN64-NEXT: sh a6, 146(sp)
+; ZVFBFMIN64-NEXT: sh a5, 148(sp)
+; ZVFBFMIN64-NEXT: sh a4, 150(sp)
+; ZVFBFMIN64-NEXT: and a1, a2, a1
+; ZVFBFMIN64-NEXT: sh a1, 160(sp)
+; ZVFBFMIN64-NEXT: addi a1, sp, 128
+; ZVFBFMIN64-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFBFMIN64-NEXT: vle16.v v8, (a1)
+; ZVFBFMIN64-NEXT: addi sp, s0, -384
+; ZVFBFMIN64-NEXT: .cfi_def_cfa sp, 384
+; ZVFBFMIN64-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
+; ZVFBFMIN64-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
+; ZVFBFMIN64-NEXT: .cfi_restore ra
+; ZVFBFMIN64-NEXT: .cfi_restore s0
+; ZVFBFMIN64-NEXT: addi sp, sp, 384
+; ZVFBFMIN64-NEXT: .cfi_def_cfa_offset 0
+; ZVFBFMIN64-NEXT: ret
+ %r = call <64 x bfloat> @llvm.fabs.v64bf16(<64 x bfloat> %v)
+ ret <64 x bfloat> %r
+}
+
+define <1 x half> @v1f16(<1 x half> %v) {
+; CHECK-LABEL: v1f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 8
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: ret
+ %r = call <1 x half> @llvm.fabs.v1f16(<1 x half> %v)
+ ret <1 x half> %r
+}
+
+define <2 x half> @v2f16(<2 x half> %v) {
+; CHECK-LABEL: v2f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 8
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: ret
+ %r = call <2 x half> @llvm.fabs.v2f16(<2 x half> %v)
+ ret <2 x half> %r
+}
+
+define <8 x half> @v8f16(<8 x half> %v) {
+; CHECK-LABEL: v8f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 8
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: ret
+ %r = call <8 x half> @llvm.fabs.v8f16(<8 x half> %v)
+ ret <8 x half> %r
+}
+
+define <32 x half> @v32f16(<32 x half> %v) {
+; CHECK-LABEL: v32f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 8
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: li a1, 32
+; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: ret
+ %r = call <32 x half> @llvm.fabs.v32f16(<32 x half> %v)
+ ret <32 x half> %r
+}
+
+define <64 x half> @v64f16(<64 x half> %v) {
+; ZVFHMIN32-LABEL: v64f16:
+; ZVFHMIN32: # %bb.0:
+; ZVFHMIN32-NEXT: addi sp, sp, -384
+; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 384
+; ZVFHMIN32-NEXT: sw ra, 380(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: sw s0, 376(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: .cfi_offset ra, -4
+; ZVFHMIN32-NEXT: .cfi_offset s0, -8
+; ZVFHMIN32-NEXT: addi s0, sp, 384
+; ZVFHMIN32-NEXT: .cfi_def_cfa s0, 0
+; ZVFHMIN32-NEXT: andi sp, sp, -128
+; ZVFHMIN32-NEXT: li a0, 64
+; ZVFHMIN32-NEXT: mv a1, sp
+; ZVFHMIN32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN32-NEXT: vse16.v v8, (a1)
+; ZVFHMIN32-NEXT: lhu a2, 126(sp)
+; ZVFHMIN32-NEXT: lui a1, 8
+; ZVFHMIN32-NEXT: addi a1, a1, -1
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 254(sp)
+; ZVFHMIN32-NEXT: lhu a2, 124(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 252(sp)
+; ZVFHMIN32-NEXT: lhu a2, 122(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 250(sp)
+; ZVFHMIN32-NEXT: lhu a2, 120(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 248(sp)
+; ZVFHMIN32-NEXT: lhu a2, 118(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 246(sp)
+; ZVFHMIN32-NEXT: lhu a2, 116(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 244(sp)
+; ZVFHMIN32-NEXT: lhu a2, 114(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 242(sp)
+; ZVFHMIN32-NEXT: lhu a2, 112(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 240(sp)
+; ZVFHMIN32-NEXT: lhu a2, 110(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 238(sp)
+; ZVFHMIN32-NEXT: lhu a2, 108(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 236(sp)
+; ZVFHMIN32-NEXT: lhu a2, 106(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 234(sp)
+; ZVFHMIN32-NEXT: lhu a2, 104(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 232(sp)
+; ZVFHMIN32-NEXT: lhu a2, 102(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 230(sp)
+; ZVFHMIN32-NEXT: lhu a2, 100(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 228(sp)
+; ZVFHMIN32-NEXT: lhu a2, 98(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 226(sp)
+; ZVFHMIN32-NEXT: lhu a2, 96(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 224(sp)
+; ZVFHMIN32-NEXT: lhu a2, 94(sp)
+; ZVFHMIN32-NEXT: vmv.x.s a3, v8
+; ZVFHMIN32-NEXT: and a3, a3, a1
+; ZVFHMIN32-NEXT: sh a3, 128(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 222(sp)
+; ZVFHMIN32-NEXT: lhu a2, 92(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 220(sp)
+; ZVFHMIN32-NEXT: lhu a2, 90(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 218(sp)
+; ZVFHMIN32-NEXT: lhu a2, 88(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 216(sp)
+; ZVFHMIN32-NEXT: lhu a2, 86(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 214(sp)
+; ZVFHMIN32-NEXT: lhu a2, 84(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 212(sp)
+; ZVFHMIN32-NEXT: lhu a2, 82(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 210(sp)
+; ZVFHMIN32-NEXT: lhu a2, 80(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 208(sp)
+; ZVFHMIN32-NEXT: lhu a2, 78(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 206(sp)
+; ZVFHMIN32-NEXT: lhu a2, 76(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 204(sp)
+; ZVFHMIN32-NEXT: lhu a2, 74(sp)
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v10, v8, 7
+; ZVFHMIN32-NEXT: vslidedown.vi v11, v8, 6
+; ZVFHMIN32-NEXT: vslidedown.vi v12, v8, 5
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 202(sp)
+; ZVFHMIN32-NEXT: lhu a2, 72(sp)
+; ZVFHMIN32-NEXT: vslidedown.vi v13, v8, 4
+; ZVFHMIN32-NEXT: vslidedown.vi v14, v8, 3
+; ZVFHMIN32-NEXT: vslidedown.vi v15, v8, 2
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 200(sp)
+; ZVFHMIN32-NEXT: lhu a2, 70(sp)
+; ZVFHMIN32-NEXT: vslidedown.vi v16, v8, 1
+; ZVFHMIN32-NEXT: vmv.x.s a3, v10
+; ZVFHMIN32-NEXT: vmv.x.s a4, v11
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 198(sp)
+; ZVFHMIN32-NEXT: lhu a2, 68(sp)
+; ZVFHMIN32-NEXT: vmv.x.s a5, v12
+; ZVFHMIN32-NEXT: vmv.x.s a6, v13
+; ZVFHMIN32-NEXT: vmv.x.s a7, v14
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 196(sp)
+; ZVFHMIN32-NEXT: lhu a2, 66(sp)
+; ZVFHMIN32-NEXT: vmv.x.s t0, v15
+; ZVFHMIN32-NEXT: vmv.x.s t1, v16
+; ZVFHMIN32-NEXT: and a3, a3, a1
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 194(sp)
+; ZVFHMIN32-NEXT: lhu a2, 64(sp)
+; ZVFHMIN32-NEXT: and a4, a4, a1
+; ZVFHMIN32-NEXT: and a5, a5, a1
+; ZVFHMIN32-NEXT: and a6, a6, a1
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 192(sp)
+; ZVFHMIN32-NEXT: lhu a2, 62(sp)
+; ZVFHMIN32-NEXT: and a7, a7, a1
+; ZVFHMIN32-NEXT: and t0, t0, a1
+; ZVFHMIN32-NEXT: and t1, t1, a1
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 190(sp)
+; ZVFHMIN32-NEXT: lhu a2, 60(sp)
+; ZVFHMIN32-NEXT: sh t1, 130(sp)
+; ZVFHMIN32-NEXT: sh t0, 132(sp)
+; ZVFHMIN32-NEXT: sh a7, 134(sp)
+; ZVFHMIN32-NEXT: sh a6, 136(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a5, 138(sp)
+; ZVFHMIN32-NEXT: sh a4, 140(sp)
+; ZVFHMIN32-NEXT: sh a3, 142(sp)
+; ZVFHMIN32-NEXT: sh a2, 188(sp)
+; ZVFHMIN32-NEXT: lhu a2, 58(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 186(sp)
+; ZVFHMIN32-NEXT: lhu a2, 56(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 184(sp)
+; ZVFHMIN32-NEXT: lhu a2, 54(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 182(sp)
+; ZVFHMIN32-NEXT: lhu a2, 52(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 180(sp)
+; ZVFHMIN32-NEXT: lhu a2, 50(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 178(sp)
+; ZVFHMIN32-NEXT: lhu a2, 48(sp)
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 176(sp)
+; ZVFHMIN32-NEXT: lhu a2, 46(sp)
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v10, v8, 15
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 174(sp)
+; ZVFHMIN32-NEXT: lhu a2, 44(sp)
+; ZVFHMIN32-NEXT: vslidedown.vi v12, v8, 14
+; ZVFHMIN32-NEXT: vslidedown.vi v14, v8, 13
+; ZVFHMIN32-NEXT: vslidedown.vi v16, v8, 12
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 172(sp)
+; ZVFHMIN32-NEXT: lhu a2, 42(sp)
+; ZVFHMIN32-NEXT: vslidedown.vi v18, v8, 11
+; ZVFHMIN32-NEXT: vslidedown.vi v20, v8, 10
+; ZVFHMIN32-NEXT: vslidedown.vi v22, v8, 9
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 170(sp)
+; ZVFHMIN32-NEXT: lhu a2, 40(sp)
+; ZVFHMIN32-NEXT: vslidedown.vi v8, v8, 8
+; ZVFHMIN32-NEXT: vmv.x.s a3, v10
+; ZVFHMIN32-NEXT: vmv.x.s a4, v12
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 168(sp)
+; ZVFHMIN32-NEXT: lhu a2, 38(sp)
+; ZVFHMIN32-NEXT: vmv.x.s a5, v14
+; ZVFHMIN32-NEXT: vmv.x.s a6, v16
+; ZVFHMIN32-NEXT: vmv.x.s a7, v18
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 166(sp)
+; ZVFHMIN32-NEXT: lhu a2, 36(sp)
+; ZVFHMIN32-NEXT: vmv.x.s t0, v20
+; ZVFHMIN32-NEXT: vmv.x.s t1, v22
+; ZVFHMIN32-NEXT: and a3, a3, a1
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 164(sp)
+; ZVFHMIN32-NEXT: lhu a2, 34(sp)
+; ZVFHMIN32-NEXT: and a4, a4, a1
+; ZVFHMIN32-NEXT: and a5, a5, a1
+; ZVFHMIN32-NEXT: and a6, a6, a1
+; ZVFHMIN32-NEXT: and a2, a2, a1
+; ZVFHMIN32-NEXT: sh a2, 162(sp)
+; ZVFHMIN32-NEXT: lhu a2, 32(sp)
+; ZVFHMIN32-NEXT: sh a6, 152(sp)
+; ZVFHMIN32-NEXT: sh a5, 154(sp)
+; ZVFHMIN32-NEXT: sh a4, 156(sp)
+; ZVFHMIN32-NEXT: sh a3, 158(sp)
+; ZVFHMIN32-NEXT: vmv.x.s a3, v8
+; ZVFHMIN32-NEXT: and a4, a7, a1
+; ZVFHMIN32-NEXT: and a5, t0, a1
+; ZVFHMIN32-NEXT: and a6, t1, a1
+; ZVFHMIN32-NEXT: and a3, a3, a1
+; ZVFHMIN32-NEXT: sh a3, 144(sp)
+; ZVFHMIN32-NEXT: sh a6, 146(sp)
+; ZVFHMIN32-NEXT: sh a5, 148(sp)
+; ZVFHMIN32-NEXT: sh a4, 150(sp)
+; ZVFHMIN32-NEXT: and a1, a2, a1
+; ZVFHMIN32-NEXT: sh a1, 160(sp)
+; ZVFHMIN32-NEXT: addi a1, sp, 128
+; ZVFHMIN32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN32-NEXT: vle16.v v8, (a1)
+; ZVFHMIN32-NEXT: addi sp, s0, -384
+; ZVFHMIN32-NEXT: .cfi_def_cfa sp, 384
+; ZVFHMIN32-NEXT: lw ra, 380(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: lw s0, 376(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: .cfi_restore ra
+; ZVFHMIN32-NEXT: .cfi_restore s0
+; ZVFHMIN32-NEXT: addi sp, sp, 384
+; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 0
+; ZVFHMIN32-NEXT: ret
+;
+; ZVFHMIN64-LABEL: v64f16:
+; ZVFHMIN64: # %bb.0:
+; ZVFHMIN64-NEXT: addi sp, sp, -384
+; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 384
+; ZVFHMIN64-NEXT: sd ra, 376(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: sd s0, 368(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: .cfi_offset ra, -8
+; ZVFHMIN64-NEXT: .cfi_offset s0, -16
+; ZVFHMIN64-NEXT: addi s0, sp, 384
+; ZVFHMIN64-NEXT: .cfi_def_cfa s0, 0
+; ZVFHMIN64-NEXT: andi sp, sp, -128
+; ZVFHMIN64-NEXT: li a0, 64
+; ZVFHMIN64-NEXT: mv a1, sp
+; ZVFHMIN64-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN64-NEXT: vse16.v v8, (a1)
+; ZVFHMIN64-NEXT: lhu a2, 126(sp)
+; ZVFHMIN64-NEXT: lui a1, 8
+; ZVFHMIN64-NEXT: addi a1, a1, -1
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 254(sp)
+; ZVFHMIN64-NEXT: lhu a2, 124(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 252(sp)
+; ZVFHMIN64-NEXT: lhu a2, 122(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 250(sp)
+; ZVFHMIN64-NEXT: lhu a2, 120(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 248(sp)
+; ZVFHMIN64-NEXT: lhu a2, 118(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 246(sp)
+; ZVFHMIN64-NEXT: lhu a2, 116(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 244(sp)
+; ZVFHMIN64-NEXT: lhu a2, 114(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 242(sp)
+; ZVFHMIN64-NEXT: lhu a2, 112(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 240(sp)
+; ZVFHMIN64-NEXT: lhu a2, 110(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 238(sp)
+; ZVFHMIN64-NEXT: lhu a2, 108(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 236(sp)
+; ZVFHMIN64-NEXT: lhu a2, 106(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 234(sp)
+; ZVFHMIN64-NEXT: lhu a2, 104(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 232(sp)
+; ZVFHMIN64-NEXT: lhu a2, 102(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 230(sp)
+; ZVFHMIN64-NEXT: lhu a2, 100(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 228(sp)
+; ZVFHMIN64-NEXT: lhu a2, 98(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 226(sp)
+; ZVFHMIN64-NEXT: lhu a2, 96(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 224(sp)
+; ZVFHMIN64-NEXT: lhu a2, 94(sp)
+; ZVFHMIN64-NEXT: vmv.x.s a3, v8
+; ZVFHMIN64-NEXT: and a3, a3, a1
+; ZVFHMIN64-NEXT: sh a3, 128(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 222(sp)
+; ZVFHMIN64-NEXT: lhu a2, 92(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 220(sp)
+; ZVFHMIN64-NEXT: lhu a2, 90(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 218(sp)
+; ZVFHMIN64-NEXT: lhu a2, 88(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 216(sp)
+; ZVFHMIN64-NEXT: lhu a2, 86(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 214(sp)
+; ZVFHMIN64-NEXT: lhu a2, 84(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 212(sp)
+; ZVFHMIN64-NEXT: lhu a2, 82(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 210(sp)
+; ZVFHMIN64-NEXT: lhu a2, 80(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 208(sp)
+; ZVFHMIN64-NEXT: lhu a2, 78(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 206(sp)
+; ZVFHMIN64-NEXT: lhu a2, 76(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 204(sp)
+; ZVFHMIN64-NEXT: lhu a2, 74(sp)
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v10, v8, 7
+; ZVFHMIN64-NEXT: vslidedown.vi v11, v8, 6
+; ZVFHMIN64-NEXT: vslidedown.vi v12, v8, 5
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 202(sp)
+; ZVFHMIN64-NEXT: lhu a2, 72(sp)
+; ZVFHMIN64-NEXT: vslidedown.vi v13, v8, 4
+; ZVFHMIN64-NEXT: vslidedown.vi v14, v8, 3
+; ZVFHMIN64-NEXT: vslidedown.vi v15, v8, 2
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 200(sp)
+; ZVFHMIN64-NEXT: lhu a2, 70(sp)
+; ZVFHMIN64-NEXT: vslidedown.vi v16, v8, 1
+; ZVFHMIN64-NEXT: vmv.x.s a3, v10
+; ZVFHMIN64-NEXT: vmv.x.s a4, v11
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 198(sp)
+; ZVFHMIN64-NEXT: lhu a2, 68(sp)
+; ZVFHMIN64-NEXT: vmv.x.s a5, v12
+; ZVFHMIN64-NEXT: vmv.x.s a6, v13
+; ZVFHMIN64-NEXT: vmv.x.s a7, v14
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 196(sp)
+; ZVFHMIN64-NEXT: lhu a2, 66(sp)
+; ZVFHMIN64-NEXT: vmv.x.s t0, v15
+; ZVFHMIN64-NEXT: vmv.x.s t1, v16
+; ZVFHMIN64-NEXT: and a3, a3, a1
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 194(sp)
+; ZVFHMIN64-NEXT: lhu a2, 64(sp)
+; ZVFHMIN64-NEXT: and a4, a4, a1
+; ZVFHMIN64-NEXT: and a5, a5, a1
+; ZVFHMIN64-NEXT: and a6, a6, a1
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 192(sp)
+; ZVFHMIN64-NEXT: lhu a2, 62(sp)
+; ZVFHMIN64-NEXT: and a7, a7, a1
+; ZVFHMIN64-NEXT: and t0, t0, a1
+; ZVFHMIN64-NEXT: and t1, t1, a1
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 190(sp)
+; ZVFHMIN64-NEXT: lhu a2, 60(sp)
+; ZVFHMIN64-NEXT: sh t1, 130(sp)
+; ZVFHMIN64-NEXT: sh t0, 132(sp)
+; ZVFHMIN64-NEXT: sh a7, 134(sp)
+; ZVFHMIN64-NEXT: sh a6, 136(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a5, 138(sp)
+; ZVFHMIN64-NEXT: sh a4, 140(sp)
+; ZVFHMIN64-NEXT: sh a3, 142(sp)
+; ZVFHMIN64-NEXT: sh a2, 188(sp)
+; ZVFHMIN64-NEXT: lhu a2, 58(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 186(sp)
+; ZVFHMIN64-NEXT: lhu a2, 56(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 184(sp)
+; ZVFHMIN64-NEXT: lhu a2, 54(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 182(sp)
+; ZVFHMIN64-NEXT: lhu a2, 52(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 180(sp)
+; ZVFHMIN64-NEXT: lhu a2, 50(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 178(sp)
+; ZVFHMIN64-NEXT: lhu a2, 48(sp)
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 176(sp)
+; ZVFHMIN64-NEXT: lhu a2, 46(sp)
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v10, v8, 15
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 174(sp)
+; ZVFHMIN64-NEXT: lhu a2, 44(sp)
+; ZVFHMIN64-NEXT: vslidedown.vi v12, v8, 14
+; ZVFHMIN64-NEXT: vslidedown.vi v14, v8, 13
+; ZVFHMIN64-NEXT: vslidedown.vi v16, v8, 12
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 172(sp)
+; ZVFHMIN64-NEXT: lhu a2, 42(sp)
+; ZVFHMIN64-NEXT: vslidedown.vi v18, v8, 11
+; ZVFHMIN64-NEXT: vslidedown.vi v20, v8, 10
+; ZVFHMIN64-NEXT: vslidedown.vi v22, v8, 9
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 170(sp)
+; ZVFHMIN64-NEXT: lhu a2, 40(sp)
+; ZVFHMIN64-NEXT: vslidedown.vi v8, v8, 8
+; ZVFHMIN64-NEXT: vmv.x.s a3, v10
+; ZVFHMIN64-NEXT: vmv.x.s a4, v12
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 168(sp)
+; ZVFHMIN64-NEXT: lhu a2, 38(sp)
+; ZVFHMIN64-NEXT: vmv.x.s a5, v14
+; ZVFHMIN64-NEXT: vmv.x.s a6, v16
+; ZVFHMIN64-NEXT: vmv.x.s a7, v18
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 166(sp)
+; ZVFHMIN64-NEXT: lhu a2, 36(sp)
+; ZVFHMIN64-NEXT: vmv.x.s t0, v20
+; ZVFHMIN64-NEXT: vmv.x.s t1, v22
+; ZVFHMIN64-NEXT: and a3, a3, a1
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 164(sp)
+; ZVFHMIN64-NEXT: lhu a2, 34(sp)
+; ZVFHMIN64-NEXT: and a4, a4, a1
+; ZVFHMIN64-NEXT: and a5, a5, a1
+; ZVFHMIN64-NEXT: and a6, a6, a1
+; ZVFHMIN64-NEXT: and a2, a2, a1
+; ZVFHMIN64-NEXT: sh a2, 162(sp)
+; ZVFHMIN64-NEXT: lhu a2, 32(sp)
+; ZVFHMIN64-NEXT: sh a6, 152(sp)
+; ZVFHMIN64-NEXT: sh a5, 154(sp)
+; ZVFHMIN64-NEXT: sh a4, 156(sp)
+; ZVFHMIN64-NEXT: sh a3, 158(sp)
+; ZVFHMIN64-NEXT: vmv.x.s a3, v8
+; ZVFHMIN64-NEXT: and a4, a7, a1
+; ZVFHMIN64-NEXT: and a5, t0, a1
+; ZVFHMIN64-NEXT: and a6, t1, a1
+; ZVFHMIN64-NEXT: and a3, a3, a1
+; ZVFHMIN64-NEXT: sh a3, 144(sp)
+; ZVFHMIN64-NEXT: sh a6, 146(sp)
+; ZVFHMIN64-NEXT: sh a5, 148(sp)
+; ZVFHMIN64-NEXT: sh a4, 150(sp)
+; ZVFHMIN64-NEXT: and a1, a2, a1
+; ZVFHMIN64-NEXT: sh a1, 160(sp)
+; ZVFHMIN64-NEXT: addi a1, sp, 128
+; ZVFHMIN64-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN64-NEXT: vle16.v v8, (a1)
+; ZVFHMIN64-NEXT: addi sp, s0, -384
+; ZVFHMIN64-NEXT: .cfi_def_cfa sp, 384
+; ZVFHMIN64-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: .cfi_restore ra
+; ZVFHMIN64-NEXT: .cfi_restore s0
+; ZVFHMIN64-NEXT: addi sp, sp, 384
+; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 0
+; ZVFHMIN64-NEXT: ret
+ %r = call <64 x half> @llvm.fabs.v64f16(<64 x half> %v)
+ ret <64 x half> %r
+}
>From ae343759bfab52d2fb9a2686c42b168c67749035 Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Tue, 28 Apr 2026 14:25:48 +0800
Subject: [PATCH 2/3] [llvm][RISCV] Optimize fabs for fixed vectors
vfabs is not available on zvfhmin or zvfbfmin, it's expected to expand
to integer operations instead of unrolling to scalar operations.
General expandFABS already handles that in most of cases except for
fixed vector types that are not promotable, we need to find a better
heuristic to gate this.
---
.../SelectionDAG/LegalizeVectorOps.cpp | 21 +-
llvm/test/CodeGen/NVPTX/f16x2-instructions.ll | 36 +-
.../RISCV/rvv/fixed-vectors-vfabs-sdnode.ll | 978 +-----------------
llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll | 42 +-
llvm/test/CodeGen/Thumb2/mve-vabd.ll | 66 +-
5 files changed, 82 insertions(+), 1061 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index 1aa21fc636a9d..3bf6e97a7cafe 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -2080,10 +2080,23 @@ SDValue VectorLegalizer::ExpandFABS(SDNode *Node) {
if (!TLI.isOperationLegalOrCustom(ISD::AND, IntVT))
return SDValue();
- // FIXME: The FSUB check is here to force unrolling v1f64 vectors on AArch64.
- if (!TLI.isOperationLegalOrCustomOrPromote(ISD::FSUB, VT) &&
- !VT.isScalableVector())
- return SDValue();
+ // Heuristic check to determine whether vector should be expanded to integer
+ // operations or unrolled to scalar operations.
+ // 1. Scalable vector is never unrolled.
+ // 2. Fixed vector is unrolled if one of followings is true:
+ // a. Vector only has 1 element and target knows how to handle scalar
+ // FABS(either legal or custom expand or promote).
+ // b. Vector has more than 1 element and target supports scalar
+ // FABS natively and vector length <= 3(2 AND + 1 OR).
+ if (VT.isFixedLengthVector()) {
+ EVT EltVT = VT.getVectorElementType();
+ if ((VT.getVectorNumElements() == 1 &&
+ TLI.isOperationLegalOrCustomOrPromote(ISD::FCOPYSIGN, EltVT)) ||
+ (VT.getVectorNumElements() < 4 &&
+ TLI.isOperationLegal(ISD::FCOPYSIGN, EltVT) &&
+ TLI.isExtractVecEltCheap(VT, 0)))
+ return SDValue();
+ }
SDLoc DL(Node);
SDValue Cast = DAG.getNode(ISD::BITCAST, DL, IntVT, Node->getOperand(0));
diff --git a/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll b/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
index 3ebaf68d4a15f..9ba15737ff641 100644
--- a/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
@@ -1794,33 +1794,15 @@ define <2 x half> @test_fma(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 {
}
define <2 x half> @test_fabs(<2 x half> %a) #0 {
-; CHECK-F16-LABEL: test_fabs(
-; CHECK-F16: {
-; CHECK-F16-NEXT: .reg .b32 %r<3>;
-; CHECK-F16-EMPTY:
-; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fabs_param_0];
-; CHECK-F16-NEXT: and.b32 %r2, %r1, 2147450879;
-; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r2;
-; CHECK-F16-NEXT: ret;
-;
-; CHECK-NOF16-LABEL: test_fabs(
-; CHECK-NOF16: {
-; CHECK-NOF16-NEXT: .reg .b16 %rs<5>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<7>;
-; CHECK-NOF16-EMPTY:
-; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fabs_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs2;
-; CHECK-NOF16-NEXT: abs.f32 %r3, %r2;
-; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs3, %r3;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs1;
-; CHECK-NOF16-NEXT: abs.f32 %r5, %r4;
-; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs4, %r5;
-; CHECK-NOF16-NEXT: mov.b32 %r6, {%rs4, %rs3};
-; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r6;
-; CHECK-NOF16-NEXT: ret;
+; CHECK-LABEL: test_fabs(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_fabs_param_0];
+; CHECK-NEXT: and.b32 %r2, %r1, 2147450879;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
%r = call <2 x half> @llvm.fabs.f16(<2 x half> %a)
ret <2 x half> %r
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-sdnode.ll
index 4db2d1a09cffe..5b76750e441aa 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-sdnode.ll
@@ -1,16 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+experimental-zvfbfa \
; RUN: -target-abi=ilp32d -verify-machineinstrs < %s \
-; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFA,ZVFHMIN32
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFA
; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+experimental-zvfbfa \
; RUN: -target-abi=lp64d -verify-machineinstrs < %s \
-; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFA,ZVFHMIN64
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFA
; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s \
-; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFHMIN32,ZVFBFMIN32
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN
; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s \
-; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN,ZVFHMIN64,ZVFBFMIN64
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN
define <1 x bfloat> @v1bf16(<1 x bfloat> %v) {
; ZVFBFA-LABEL: v1bf16:
@@ -130,483 +130,14 @@ define <64 x bfloat> @v64bf16(<64 x bfloat> %v) {
; ZVFBFA-NEXT: vfabs.v v8, v8
; ZVFBFA-NEXT: ret
;
-; ZVFBFMIN32-LABEL: v64bf16:
-; ZVFBFMIN32: # %bb.0:
-; ZVFBFMIN32-NEXT: addi sp, sp, -384
-; ZVFBFMIN32-NEXT: .cfi_def_cfa_offset 384
-; ZVFBFMIN32-NEXT: sw ra, 380(sp) # 4-byte Folded Spill
-; ZVFBFMIN32-NEXT: sw s0, 376(sp) # 4-byte Folded Spill
-; ZVFBFMIN32-NEXT: .cfi_offset ra, -4
-; ZVFBFMIN32-NEXT: .cfi_offset s0, -8
-; ZVFBFMIN32-NEXT: addi s0, sp, 384
-; ZVFBFMIN32-NEXT: .cfi_def_cfa s0, 0
-; ZVFBFMIN32-NEXT: andi sp, sp, -128
-; ZVFBFMIN32-NEXT: li a0, 64
-; ZVFBFMIN32-NEXT: mv a1, sp
-; ZVFBFMIN32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFBFMIN32-NEXT: vse16.v v8, (a1)
-; ZVFBFMIN32-NEXT: lhu a2, 126(sp)
-; ZVFBFMIN32-NEXT: lui a1, 8
-; ZVFBFMIN32-NEXT: addi a1, a1, -1
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 254(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 124(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 252(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 122(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 250(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 120(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 248(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 118(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 246(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 116(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 244(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 114(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 242(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 112(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 240(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 110(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 238(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 108(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 236(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 106(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 234(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 104(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 232(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 102(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 230(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 100(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 228(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 98(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 226(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 96(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 224(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 94(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s a3, v8
-; ZVFBFMIN32-NEXT: and a3, a3, a1
-; ZVFBFMIN32-NEXT: sh a3, 128(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 222(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 92(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 220(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 90(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 218(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 88(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 216(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 86(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 214(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 84(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 212(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 82(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 210(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 80(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 208(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 78(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 206(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 76(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 204(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 74(sp)
-; ZVFBFMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFBFMIN32-NEXT: vslidedown.vi v10, v8, 7
-; ZVFBFMIN32-NEXT: vslidedown.vi v11, v8, 6
-; ZVFBFMIN32-NEXT: vslidedown.vi v12, v8, 5
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 202(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 72(sp)
-; ZVFBFMIN32-NEXT: vslidedown.vi v13, v8, 4
-; ZVFBFMIN32-NEXT: vslidedown.vi v14, v8, 3
-; ZVFBFMIN32-NEXT: vslidedown.vi v15, v8, 2
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 200(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 70(sp)
-; ZVFBFMIN32-NEXT: vslidedown.vi v16, v8, 1
-; ZVFBFMIN32-NEXT: vmv.x.s a3, v10
-; ZVFBFMIN32-NEXT: vmv.x.s a4, v11
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 198(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 68(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s a5, v12
-; ZVFBFMIN32-NEXT: vmv.x.s a6, v13
-; ZVFBFMIN32-NEXT: vmv.x.s a7, v14
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 196(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 66(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s t0, v15
-; ZVFBFMIN32-NEXT: vmv.x.s t1, v16
-; ZVFBFMIN32-NEXT: and a3, a3, a1
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 194(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 64(sp)
-; ZVFBFMIN32-NEXT: and a4, a4, a1
-; ZVFBFMIN32-NEXT: and a5, a5, a1
-; ZVFBFMIN32-NEXT: and a6, a6, a1
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 192(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 62(sp)
-; ZVFBFMIN32-NEXT: and a7, a7, a1
-; ZVFBFMIN32-NEXT: and t0, t0, a1
-; ZVFBFMIN32-NEXT: and t1, t1, a1
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 190(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 60(sp)
-; ZVFBFMIN32-NEXT: sh t1, 130(sp)
-; ZVFBFMIN32-NEXT: sh t0, 132(sp)
-; ZVFBFMIN32-NEXT: sh a7, 134(sp)
-; ZVFBFMIN32-NEXT: sh a6, 136(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a5, 138(sp)
-; ZVFBFMIN32-NEXT: sh a4, 140(sp)
-; ZVFBFMIN32-NEXT: sh a3, 142(sp)
-; ZVFBFMIN32-NEXT: sh a2, 188(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 58(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 186(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 56(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 184(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 54(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 182(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 52(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 180(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 50(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 178(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 48(sp)
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 176(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 46(sp)
-; ZVFBFMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
-; ZVFBFMIN32-NEXT: vslidedown.vi v10, v8, 15
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 174(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 44(sp)
-; ZVFBFMIN32-NEXT: vslidedown.vi v12, v8, 14
-; ZVFBFMIN32-NEXT: vslidedown.vi v14, v8, 13
-; ZVFBFMIN32-NEXT: vslidedown.vi v16, v8, 12
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 172(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 42(sp)
-; ZVFBFMIN32-NEXT: vslidedown.vi v18, v8, 11
-; ZVFBFMIN32-NEXT: vslidedown.vi v20, v8, 10
-; ZVFBFMIN32-NEXT: vslidedown.vi v22, v8, 9
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 170(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 40(sp)
-; ZVFBFMIN32-NEXT: vslidedown.vi v8, v8, 8
-; ZVFBFMIN32-NEXT: vmv.x.s a3, v10
-; ZVFBFMIN32-NEXT: vmv.x.s a4, v12
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 168(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 38(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s a5, v14
-; ZVFBFMIN32-NEXT: vmv.x.s a6, v16
-; ZVFBFMIN32-NEXT: vmv.x.s a7, v18
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 166(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 36(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s t0, v20
-; ZVFBFMIN32-NEXT: vmv.x.s t1, v22
-; ZVFBFMIN32-NEXT: and a3, a3, a1
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 164(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 34(sp)
-; ZVFBFMIN32-NEXT: and a4, a4, a1
-; ZVFBFMIN32-NEXT: and a5, a5, a1
-; ZVFBFMIN32-NEXT: and a6, a6, a1
-; ZVFBFMIN32-NEXT: and a2, a2, a1
-; ZVFBFMIN32-NEXT: sh a2, 162(sp)
-; ZVFBFMIN32-NEXT: lhu a2, 32(sp)
-; ZVFBFMIN32-NEXT: sh a6, 152(sp)
-; ZVFBFMIN32-NEXT: sh a5, 154(sp)
-; ZVFBFMIN32-NEXT: sh a4, 156(sp)
-; ZVFBFMIN32-NEXT: sh a3, 158(sp)
-; ZVFBFMIN32-NEXT: vmv.x.s a3, v8
-; ZVFBFMIN32-NEXT: and a4, a7, a1
-; ZVFBFMIN32-NEXT: and a5, t0, a1
-; ZVFBFMIN32-NEXT: and a6, t1, a1
-; ZVFBFMIN32-NEXT: and a3, a3, a1
-; ZVFBFMIN32-NEXT: sh a3, 144(sp)
-; ZVFBFMIN32-NEXT: sh a6, 146(sp)
-; ZVFBFMIN32-NEXT: sh a5, 148(sp)
-; ZVFBFMIN32-NEXT: sh a4, 150(sp)
-; ZVFBFMIN32-NEXT: and a1, a2, a1
-; ZVFBFMIN32-NEXT: sh a1, 160(sp)
-; ZVFBFMIN32-NEXT: addi a1, sp, 128
-; ZVFBFMIN32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFBFMIN32-NEXT: vle16.v v8, (a1)
-; ZVFBFMIN32-NEXT: addi sp, s0, -384
-; ZVFBFMIN32-NEXT: .cfi_def_cfa sp, 384
-; ZVFBFMIN32-NEXT: lw ra, 380(sp) # 4-byte Folded Reload
-; ZVFBFMIN32-NEXT: lw s0, 376(sp) # 4-byte Folded Reload
-; ZVFBFMIN32-NEXT: .cfi_restore ra
-; ZVFBFMIN32-NEXT: .cfi_restore s0
-; ZVFBFMIN32-NEXT: addi sp, sp, 384
-; ZVFBFMIN32-NEXT: .cfi_def_cfa_offset 0
-; ZVFBFMIN32-NEXT: ret
-;
-; ZVFBFMIN64-LABEL: v64bf16:
-; ZVFBFMIN64: # %bb.0:
-; ZVFBFMIN64-NEXT: addi sp, sp, -384
-; ZVFBFMIN64-NEXT: .cfi_def_cfa_offset 384
-; ZVFBFMIN64-NEXT: sd ra, 376(sp) # 8-byte Folded Spill
-; ZVFBFMIN64-NEXT: sd s0, 368(sp) # 8-byte Folded Spill
-; ZVFBFMIN64-NEXT: .cfi_offset ra, -8
-; ZVFBFMIN64-NEXT: .cfi_offset s0, -16
-; ZVFBFMIN64-NEXT: addi s0, sp, 384
-; ZVFBFMIN64-NEXT: .cfi_def_cfa s0, 0
-; ZVFBFMIN64-NEXT: andi sp, sp, -128
-; ZVFBFMIN64-NEXT: li a0, 64
-; ZVFBFMIN64-NEXT: mv a1, sp
-; ZVFBFMIN64-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFBFMIN64-NEXT: vse16.v v8, (a1)
-; ZVFBFMIN64-NEXT: lhu a2, 126(sp)
-; ZVFBFMIN64-NEXT: lui a1, 8
-; ZVFBFMIN64-NEXT: addi a1, a1, -1
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 254(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 124(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 252(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 122(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 250(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 120(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 248(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 118(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 246(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 116(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 244(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 114(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 242(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 112(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 240(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 110(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 238(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 108(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 236(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 106(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 234(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 104(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 232(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 102(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 230(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 100(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 228(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 98(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 226(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 96(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 224(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 94(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s a3, v8
-; ZVFBFMIN64-NEXT: and a3, a3, a1
-; ZVFBFMIN64-NEXT: sh a3, 128(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 222(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 92(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 220(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 90(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 218(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 88(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 216(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 86(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 214(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 84(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 212(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 82(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 210(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 80(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 208(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 78(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 206(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 76(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 204(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 74(sp)
-; ZVFBFMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFBFMIN64-NEXT: vslidedown.vi v10, v8, 7
-; ZVFBFMIN64-NEXT: vslidedown.vi v11, v8, 6
-; ZVFBFMIN64-NEXT: vslidedown.vi v12, v8, 5
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 202(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 72(sp)
-; ZVFBFMIN64-NEXT: vslidedown.vi v13, v8, 4
-; ZVFBFMIN64-NEXT: vslidedown.vi v14, v8, 3
-; ZVFBFMIN64-NEXT: vslidedown.vi v15, v8, 2
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 200(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 70(sp)
-; ZVFBFMIN64-NEXT: vslidedown.vi v16, v8, 1
-; ZVFBFMIN64-NEXT: vmv.x.s a3, v10
-; ZVFBFMIN64-NEXT: vmv.x.s a4, v11
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 198(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 68(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s a5, v12
-; ZVFBFMIN64-NEXT: vmv.x.s a6, v13
-; ZVFBFMIN64-NEXT: vmv.x.s a7, v14
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 196(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 66(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s t0, v15
-; ZVFBFMIN64-NEXT: vmv.x.s t1, v16
-; ZVFBFMIN64-NEXT: and a3, a3, a1
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 194(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 64(sp)
-; ZVFBFMIN64-NEXT: and a4, a4, a1
-; ZVFBFMIN64-NEXT: and a5, a5, a1
-; ZVFBFMIN64-NEXT: and a6, a6, a1
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 192(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 62(sp)
-; ZVFBFMIN64-NEXT: and a7, a7, a1
-; ZVFBFMIN64-NEXT: and t0, t0, a1
-; ZVFBFMIN64-NEXT: and t1, t1, a1
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 190(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 60(sp)
-; ZVFBFMIN64-NEXT: sh t1, 130(sp)
-; ZVFBFMIN64-NEXT: sh t0, 132(sp)
-; ZVFBFMIN64-NEXT: sh a7, 134(sp)
-; ZVFBFMIN64-NEXT: sh a6, 136(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a5, 138(sp)
-; ZVFBFMIN64-NEXT: sh a4, 140(sp)
-; ZVFBFMIN64-NEXT: sh a3, 142(sp)
-; ZVFBFMIN64-NEXT: sh a2, 188(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 58(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 186(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 56(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 184(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 54(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 182(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 52(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 180(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 50(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 178(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 48(sp)
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 176(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 46(sp)
-; ZVFBFMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
-; ZVFBFMIN64-NEXT: vslidedown.vi v10, v8, 15
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 174(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 44(sp)
-; ZVFBFMIN64-NEXT: vslidedown.vi v12, v8, 14
-; ZVFBFMIN64-NEXT: vslidedown.vi v14, v8, 13
-; ZVFBFMIN64-NEXT: vslidedown.vi v16, v8, 12
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 172(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 42(sp)
-; ZVFBFMIN64-NEXT: vslidedown.vi v18, v8, 11
-; ZVFBFMIN64-NEXT: vslidedown.vi v20, v8, 10
-; ZVFBFMIN64-NEXT: vslidedown.vi v22, v8, 9
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 170(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 40(sp)
-; ZVFBFMIN64-NEXT: vslidedown.vi v8, v8, 8
-; ZVFBFMIN64-NEXT: vmv.x.s a3, v10
-; ZVFBFMIN64-NEXT: vmv.x.s a4, v12
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 168(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 38(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s a5, v14
-; ZVFBFMIN64-NEXT: vmv.x.s a6, v16
-; ZVFBFMIN64-NEXT: vmv.x.s a7, v18
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 166(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 36(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s t0, v20
-; ZVFBFMIN64-NEXT: vmv.x.s t1, v22
-; ZVFBFMIN64-NEXT: and a3, a3, a1
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 164(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 34(sp)
-; ZVFBFMIN64-NEXT: and a4, a4, a1
-; ZVFBFMIN64-NEXT: and a5, a5, a1
-; ZVFBFMIN64-NEXT: and a6, a6, a1
-; ZVFBFMIN64-NEXT: and a2, a2, a1
-; ZVFBFMIN64-NEXT: sh a2, 162(sp)
-; ZVFBFMIN64-NEXT: lhu a2, 32(sp)
-; ZVFBFMIN64-NEXT: sh a6, 152(sp)
-; ZVFBFMIN64-NEXT: sh a5, 154(sp)
-; ZVFBFMIN64-NEXT: sh a4, 156(sp)
-; ZVFBFMIN64-NEXT: sh a3, 158(sp)
-; ZVFBFMIN64-NEXT: vmv.x.s a3, v8
-; ZVFBFMIN64-NEXT: and a4, a7, a1
-; ZVFBFMIN64-NEXT: and a5, t0, a1
-; ZVFBFMIN64-NEXT: and a6, t1, a1
-; ZVFBFMIN64-NEXT: and a3, a3, a1
-; ZVFBFMIN64-NEXT: sh a3, 144(sp)
-; ZVFBFMIN64-NEXT: sh a6, 146(sp)
-; ZVFBFMIN64-NEXT: sh a5, 148(sp)
-; ZVFBFMIN64-NEXT: sh a4, 150(sp)
-; ZVFBFMIN64-NEXT: and a1, a2, a1
-; ZVFBFMIN64-NEXT: sh a1, 160(sp)
-; ZVFBFMIN64-NEXT: addi a1, sp, 128
-; ZVFBFMIN64-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFBFMIN64-NEXT: vle16.v v8, (a1)
-; ZVFBFMIN64-NEXT: addi sp, s0, -384
-; ZVFBFMIN64-NEXT: .cfi_def_cfa sp, 384
-; ZVFBFMIN64-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
-; ZVFBFMIN64-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
-; ZVFBFMIN64-NEXT: .cfi_restore ra
-; ZVFBFMIN64-NEXT: .cfi_restore s0
-; ZVFBFMIN64-NEXT: addi sp, sp, 384
-; ZVFBFMIN64-NEXT: .cfi_def_cfa_offset 0
-; ZVFBFMIN64-NEXT: ret
+; ZVFBFMIN-LABEL: v64bf16:
+; ZVFBFMIN: # %bb.0:
+; ZVFBFMIN-NEXT: lui a0, 8
+; ZVFBFMIN-NEXT: addi a0, a0, -1
+; ZVFBFMIN-NEXT: li a1, 64
+; ZVFBFMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFBFMIN-NEXT: vand.vx v8, v8, a0
+; ZVFBFMIN-NEXT: ret
%r = call <64 x bfloat> @llvm.fabs.v64bf16(<64 x bfloat> %v)
ret <64 x bfloat> %r
}
@@ -661,483 +192,14 @@ define <32 x half> @v32f16(<32 x half> %v) {
}
define <64 x half> @v64f16(<64 x half> %v) {
-; ZVFHMIN32-LABEL: v64f16:
-; ZVFHMIN32: # %bb.0:
-; ZVFHMIN32-NEXT: addi sp, sp, -384
-; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 384
-; ZVFHMIN32-NEXT: sw ra, 380(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT: sw s0, 376(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT: .cfi_offset ra, -4
-; ZVFHMIN32-NEXT: .cfi_offset s0, -8
-; ZVFHMIN32-NEXT: addi s0, sp, 384
-; ZVFHMIN32-NEXT: .cfi_def_cfa s0, 0
-; ZVFHMIN32-NEXT: andi sp, sp, -128
-; ZVFHMIN32-NEXT: li a0, 64
-; ZVFHMIN32-NEXT: mv a1, sp
-; ZVFHMIN32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN32-NEXT: vse16.v v8, (a1)
-; ZVFHMIN32-NEXT: lhu a2, 126(sp)
-; ZVFHMIN32-NEXT: lui a1, 8
-; ZVFHMIN32-NEXT: addi a1, a1, -1
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 254(sp)
-; ZVFHMIN32-NEXT: lhu a2, 124(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 252(sp)
-; ZVFHMIN32-NEXT: lhu a2, 122(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 250(sp)
-; ZVFHMIN32-NEXT: lhu a2, 120(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 248(sp)
-; ZVFHMIN32-NEXT: lhu a2, 118(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 246(sp)
-; ZVFHMIN32-NEXT: lhu a2, 116(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 244(sp)
-; ZVFHMIN32-NEXT: lhu a2, 114(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 242(sp)
-; ZVFHMIN32-NEXT: lhu a2, 112(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 240(sp)
-; ZVFHMIN32-NEXT: lhu a2, 110(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 238(sp)
-; ZVFHMIN32-NEXT: lhu a2, 108(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 236(sp)
-; ZVFHMIN32-NEXT: lhu a2, 106(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 234(sp)
-; ZVFHMIN32-NEXT: lhu a2, 104(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 232(sp)
-; ZVFHMIN32-NEXT: lhu a2, 102(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 230(sp)
-; ZVFHMIN32-NEXT: lhu a2, 100(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 228(sp)
-; ZVFHMIN32-NEXT: lhu a2, 98(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 226(sp)
-; ZVFHMIN32-NEXT: lhu a2, 96(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 224(sp)
-; ZVFHMIN32-NEXT: lhu a2, 94(sp)
-; ZVFHMIN32-NEXT: vmv.x.s a3, v8
-; ZVFHMIN32-NEXT: and a3, a3, a1
-; ZVFHMIN32-NEXT: sh a3, 128(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 222(sp)
-; ZVFHMIN32-NEXT: lhu a2, 92(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 220(sp)
-; ZVFHMIN32-NEXT: lhu a2, 90(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 218(sp)
-; ZVFHMIN32-NEXT: lhu a2, 88(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 216(sp)
-; ZVFHMIN32-NEXT: lhu a2, 86(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 214(sp)
-; ZVFHMIN32-NEXT: lhu a2, 84(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 212(sp)
-; ZVFHMIN32-NEXT: lhu a2, 82(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 210(sp)
-; ZVFHMIN32-NEXT: lhu a2, 80(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 208(sp)
-; ZVFHMIN32-NEXT: lhu a2, 78(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 206(sp)
-; ZVFHMIN32-NEXT: lhu a2, 76(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 204(sp)
-; ZVFHMIN32-NEXT: lhu a2, 74(sp)
-; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFHMIN32-NEXT: vslidedown.vi v10, v8, 7
-; ZVFHMIN32-NEXT: vslidedown.vi v11, v8, 6
-; ZVFHMIN32-NEXT: vslidedown.vi v12, v8, 5
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 202(sp)
-; ZVFHMIN32-NEXT: lhu a2, 72(sp)
-; ZVFHMIN32-NEXT: vslidedown.vi v13, v8, 4
-; ZVFHMIN32-NEXT: vslidedown.vi v14, v8, 3
-; ZVFHMIN32-NEXT: vslidedown.vi v15, v8, 2
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 200(sp)
-; ZVFHMIN32-NEXT: lhu a2, 70(sp)
-; ZVFHMIN32-NEXT: vslidedown.vi v16, v8, 1
-; ZVFHMIN32-NEXT: vmv.x.s a3, v10
-; ZVFHMIN32-NEXT: vmv.x.s a4, v11
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 198(sp)
-; ZVFHMIN32-NEXT: lhu a2, 68(sp)
-; ZVFHMIN32-NEXT: vmv.x.s a5, v12
-; ZVFHMIN32-NEXT: vmv.x.s a6, v13
-; ZVFHMIN32-NEXT: vmv.x.s a7, v14
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 196(sp)
-; ZVFHMIN32-NEXT: lhu a2, 66(sp)
-; ZVFHMIN32-NEXT: vmv.x.s t0, v15
-; ZVFHMIN32-NEXT: vmv.x.s t1, v16
-; ZVFHMIN32-NEXT: and a3, a3, a1
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 194(sp)
-; ZVFHMIN32-NEXT: lhu a2, 64(sp)
-; ZVFHMIN32-NEXT: and a4, a4, a1
-; ZVFHMIN32-NEXT: and a5, a5, a1
-; ZVFHMIN32-NEXT: and a6, a6, a1
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 192(sp)
-; ZVFHMIN32-NEXT: lhu a2, 62(sp)
-; ZVFHMIN32-NEXT: and a7, a7, a1
-; ZVFHMIN32-NEXT: and t0, t0, a1
-; ZVFHMIN32-NEXT: and t1, t1, a1
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 190(sp)
-; ZVFHMIN32-NEXT: lhu a2, 60(sp)
-; ZVFHMIN32-NEXT: sh t1, 130(sp)
-; ZVFHMIN32-NEXT: sh t0, 132(sp)
-; ZVFHMIN32-NEXT: sh a7, 134(sp)
-; ZVFHMIN32-NEXT: sh a6, 136(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a5, 138(sp)
-; ZVFHMIN32-NEXT: sh a4, 140(sp)
-; ZVFHMIN32-NEXT: sh a3, 142(sp)
-; ZVFHMIN32-NEXT: sh a2, 188(sp)
-; ZVFHMIN32-NEXT: lhu a2, 58(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 186(sp)
-; ZVFHMIN32-NEXT: lhu a2, 56(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 184(sp)
-; ZVFHMIN32-NEXT: lhu a2, 54(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 182(sp)
-; ZVFHMIN32-NEXT: lhu a2, 52(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 180(sp)
-; ZVFHMIN32-NEXT: lhu a2, 50(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 178(sp)
-; ZVFHMIN32-NEXT: lhu a2, 48(sp)
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 176(sp)
-; ZVFHMIN32-NEXT: lhu a2, 46(sp)
-; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
-; ZVFHMIN32-NEXT: vslidedown.vi v10, v8, 15
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 174(sp)
-; ZVFHMIN32-NEXT: lhu a2, 44(sp)
-; ZVFHMIN32-NEXT: vslidedown.vi v12, v8, 14
-; ZVFHMIN32-NEXT: vslidedown.vi v14, v8, 13
-; ZVFHMIN32-NEXT: vslidedown.vi v16, v8, 12
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 172(sp)
-; ZVFHMIN32-NEXT: lhu a2, 42(sp)
-; ZVFHMIN32-NEXT: vslidedown.vi v18, v8, 11
-; ZVFHMIN32-NEXT: vslidedown.vi v20, v8, 10
-; ZVFHMIN32-NEXT: vslidedown.vi v22, v8, 9
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 170(sp)
-; ZVFHMIN32-NEXT: lhu a2, 40(sp)
-; ZVFHMIN32-NEXT: vslidedown.vi v8, v8, 8
-; ZVFHMIN32-NEXT: vmv.x.s a3, v10
-; ZVFHMIN32-NEXT: vmv.x.s a4, v12
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 168(sp)
-; ZVFHMIN32-NEXT: lhu a2, 38(sp)
-; ZVFHMIN32-NEXT: vmv.x.s a5, v14
-; ZVFHMIN32-NEXT: vmv.x.s a6, v16
-; ZVFHMIN32-NEXT: vmv.x.s a7, v18
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 166(sp)
-; ZVFHMIN32-NEXT: lhu a2, 36(sp)
-; ZVFHMIN32-NEXT: vmv.x.s t0, v20
-; ZVFHMIN32-NEXT: vmv.x.s t1, v22
-; ZVFHMIN32-NEXT: and a3, a3, a1
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 164(sp)
-; ZVFHMIN32-NEXT: lhu a2, 34(sp)
-; ZVFHMIN32-NEXT: and a4, a4, a1
-; ZVFHMIN32-NEXT: and a5, a5, a1
-; ZVFHMIN32-NEXT: and a6, a6, a1
-; ZVFHMIN32-NEXT: and a2, a2, a1
-; ZVFHMIN32-NEXT: sh a2, 162(sp)
-; ZVFHMIN32-NEXT: lhu a2, 32(sp)
-; ZVFHMIN32-NEXT: sh a6, 152(sp)
-; ZVFHMIN32-NEXT: sh a5, 154(sp)
-; ZVFHMIN32-NEXT: sh a4, 156(sp)
-; ZVFHMIN32-NEXT: sh a3, 158(sp)
-; ZVFHMIN32-NEXT: vmv.x.s a3, v8
-; ZVFHMIN32-NEXT: and a4, a7, a1
-; ZVFHMIN32-NEXT: and a5, t0, a1
-; ZVFHMIN32-NEXT: and a6, t1, a1
-; ZVFHMIN32-NEXT: and a3, a3, a1
-; ZVFHMIN32-NEXT: sh a3, 144(sp)
-; ZVFHMIN32-NEXT: sh a6, 146(sp)
-; ZVFHMIN32-NEXT: sh a5, 148(sp)
-; ZVFHMIN32-NEXT: sh a4, 150(sp)
-; ZVFHMIN32-NEXT: and a1, a2, a1
-; ZVFHMIN32-NEXT: sh a1, 160(sp)
-; ZVFHMIN32-NEXT: addi a1, sp, 128
-; ZVFHMIN32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN32-NEXT: vle16.v v8, (a1)
-; ZVFHMIN32-NEXT: addi sp, s0, -384
-; ZVFHMIN32-NEXT: .cfi_def_cfa sp, 384
-; ZVFHMIN32-NEXT: lw ra, 380(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT: lw s0, 376(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT: .cfi_restore ra
-; ZVFHMIN32-NEXT: .cfi_restore s0
-; ZVFHMIN32-NEXT: addi sp, sp, 384
-; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 0
-; ZVFHMIN32-NEXT: ret
-;
-; ZVFHMIN64-LABEL: v64f16:
-; ZVFHMIN64: # %bb.0:
-; ZVFHMIN64-NEXT: addi sp, sp, -384
-; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 384
-; ZVFHMIN64-NEXT: sd ra, 376(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT: sd s0, 368(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT: .cfi_offset ra, -8
-; ZVFHMIN64-NEXT: .cfi_offset s0, -16
-; ZVFHMIN64-NEXT: addi s0, sp, 384
-; ZVFHMIN64-NEXT: .cfi_def_cfa s0, 0
-; ZVFHMIN64-NEXT: andi sp, sp, -128
-; ZVFHMIN64-NEXT: li a0, 64
-; ZVFHMIN64-NEXT: mv a1, sp
-; ZVFHMIN64-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN64-NEXT: vse16.v v8, (a1)
-; ZVFHMIN64-NEXT: lhu a2, 126(sp)
-; ZVFHMIN64-NEXT: lui a1, 8
-; ZVFHMIN64-NEXT: addi a1, a1, -1
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 254(sp)
-; ZVFHMIN64-NEXT: lhu a2, 124(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 252(sp)
-; ZVFHMIN64-NEXT: lhu a2, 122(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 250(sp)
-; ZVFHMIN64-NEXT: lhu a2, 120(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 248(sp)
-; ZVFHMIN64-NEXT: lhu a2, 118(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 246(sp)
-; ZVFHMIN64-NEXT: lhu a2, 116(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 244(sp)
-; ZVFHMIN64-NEXT: lhu a2, 114(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 242(sp)
-; ZVFHMIN64-NEXT: lhu a2, 112(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 240(sp)
-; ZVFHMIN64-NEXT: lhu a2, 110(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 238(sp)
-; ZVFHMIN64-NEXT: lhu a2, 108(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 236(sp)
-; ZVFHMIN64-NEXT: lhu a2, 106(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 234(sp)
-; ZVFHMIN64-NEXT: lhu a2, 104(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 232(sp)
-; ZVFHMIN64-NEXT: lhu a2, 102(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 230(sp)
-; ZVFHMIN64-NEXT: lhu a2, 100(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 228(sp)
-; ZVFHMIN64-NEXT: lhu a2, 98(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 226(sp)
-; ZVFHMIN64-NEXT: lhu a2, 96(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 224(sp)
-; ZVFHMIN64-NEXT: lhu a2, 94(sp)
-; ZVFHMIN64-NEXT: vmv.x.s a3, v8
-; ZVFHMIN64-NEXT: and a3, a3, a1
-; ZVFHMIN64-NEXT: sh a3, 128(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 222(sp)
-; ZVFHMIN64-NEXT: lhu a2, 92(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 220(sp)
-; ZVFHMIN64-NEXT: lhu a2, 90(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 218(sp)
-; ZVFHMIN64-NEXT: lhu a2, 88(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 216(sp)
-; ZVFHMIN64-NEXT: lhu a2, 86(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 214(sp)
-; ZVFHMIN64-NEXT: lhu a2, 84(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 212(sp)
-; ZVFHMIN64-NEXT: lhu a2, 82(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 210(sp)
-; ZVFHMIN64-NEXT: lhu a2, 80(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 208(sp)
-; ZVFHMIN64-NEXT: lhu a2, 78(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 206(sp)
-; ZVFHMIN64-NEXT: lhu a2, 76(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 204(sp)
-; ZVFHMIN64-NEXT: lhu a2, 74(sp)
-; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFHMIN64-NEXT: vslidedown.vi v10, v8, 7
-; ZVFHMIN64-NEXT: vslidedown.vi v11, v8, 6
-; ZVFHMIN64-NEXT: vslidedown.vi v12, v8, 5
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 202(sp)
-; ZVFHMIN64-NEXT: lhu a2, 72(sp)
-; ZVFHMIN64-NEXT: vslidedown.vi v13, v8, 4
-; ZVFHMIN64-NEXT: vslidedown.vi v14, v8, 3
-; ZVFHMIN64-NEXT: vslidedown.vi v15, v8, 2
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 200(sp)
-; ZVFHMIN64-NEXT: lhu a2, 70(sp)
-; ZVFHMIN64-NEXT: vslidedown.vi v16, v8, 1
-; ZVFHMIN64-NEXT: vmv.x.s a3, v10
-; ZVFHMIN64-NEXT: vmv.x.s a4, v11
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 198(sp)
-; ZVFHMIN64-NEXT: lhu a2, 68(sp)
-; ZVFHMIN64-NEXT: vmv.x.s a5, v12
-; ZVFHMIN64-NEXT: vmv.x.s a6, v13
-; ZVFHMIN64-NEXT: vmv.x.s a7, v14
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 196(sp)
-; ZVFHMIN64-NEXT: lhu a2, 66(sp)
-; ZVFHMIN64-NEXT: vmv.x.s t0, v15
-; ZVFHMIN64-NEXT: vmv.x.s t1, v16
-; ZVFHMIN64-NEXT: and a3, a3, a1
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 194(sp)
-; ZVFHMIN64-NEXT: lhu a2, 64(sp)
-; ZVFHMIN64-NEXT: and a4, a4, a1
-; ZVFHMIN64-NEXT: and a5, a5, a1
-; ZVFHMIN64-NEXT: and a6, a6, a1
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 192(sp)
-; ZVFHMIN64-NEXT: lhu a2, 62(sp)
-; ZVFHMIN64-NEXT: and a7, a7, a1
-; ZVFHMIN64-NEXT: and t0, t0, a1
-; ZVFHMIN64-NEXT: and t1, t1, a1
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 190(sp)
-; ZVFHMIN64-NEXT: lhu a2, 60(sp)
-; ZVFHMIN64-NEXT: sh t1, 130(sp)
-; ZVFHMIN64-NEXT: sh t0, 132(sp)
-; ZVFHMIN64-NEXT: sh a7, 134(sp)
-; ZVFHMIN64-NEXT: sh a6, 136(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a5, 138(sp)
-; ZVFHMIN64-NEXT: sh a4, 140(sp)
-; ZVFHMIN64-NEXT: sh a3, 142(sp)
-; ZVFHMIN64-NEXT: sh a2, 188(sp)
-; ZVFHMIN64-NEXT: lhu a2, 58(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 186(sp)
-; ZVFHMIN64-NEXT: lhu a2, 56(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 184(sp)
-; ZVFHMIN64-NEXT: lhu a2, 54(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 182(sp)
-; ZVFHMIN64-NEXT: lhu a2, 52(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 180(sp)
-; ZVFHMIN64-NEXT: lhu a2, 50(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 178(sp)
-; ZVFHMIN64-NEXT: lhu a2, 48(sp)
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 176(sp)
-; ZVFHMIN64-NEXT: lhu a2, 46(sp)
-; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
-; ZVFHMIN64-NEXT: vslidedown.vi v10, v8, 15
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 174(sp)
-; ZVFHMIN64-NEXT: lhu a2, 44(sp)
-; ZVFHMIN64-NEXT: vslidedown.vi v12, v8, 14
-; ZVFHMIN64-NEXT: vslidedown.vi v14, v8, 13
-; ZVFHMIN64-NEXT: vslidedown.vi v16, v8, 12
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 172(sp)
-; ZVFHMIN64-NEXT: lhu a2, 42(sp)
-; ZVFHMIN64-NEXT: vslidedown.vi v18, v8, 11
-; ZVFHMIN64-NEXT: vslidedown.vi v20, v8, 10
-; ZVFHMIN64-NEXT: vslidedown.vi v22, v8, 9
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 170(sp)
-; ZVFHMIN64-NEXT: lhu a2, 40(sp)
-; ZVFHMIN64-NEXT: vslidedown.vi v8, v8, 8
-; ZVFHMIN64-NEXT: vmv.x.s a3, v10
-; ZVFHMIN64-NEXT: vmv.x.s a4, v12
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 168(sp)
-; ZVFHMIN64-NEXT: lhu a2, 38(sp)
-; ZVFHMIN64-NEXT: vmv.x.s a5, v14
-; ZVFHMIN64-NEXT: vmv.x.s a6, v16
-; ZVFHMIN64-NEXT: vmv.x.s a7, v18
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 166(sp)
-; ZVFHMIN64-NEXT: lhu a2, 36(sp)
-; ZVFHMIN64-NEXT: vmv.x.s t0, v20
-; ZVFHMIN64-NEXT: vmv.x.s t1, v22
-; ZVFHMIN64-NEXT: and a3, a3, a1
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 164(sp)
-; ZVFHMIN64-NEXT: lhu a2, 34(sp)
-; ZVFHMIN64-NEXT: and a4, a4, a1
-; ZVFHMIN64-NEXT: and a5, a5, a1
-; ZVFHMIN64-NEXT: and a6, a6, a1
-; ZVFHMIN64-NEXT: and a2, a2, a1
-; ZVFHMIN64-NEXT: sh a2, 162(sp)
-; ZVFHMIN64-NEXT: lhu a2, 32(sp)
-; ZVFHMIN64-NEXT: sh a6, 152(sp)
-; ZVFHMIN64-NEXT: sh a5, 154(sp)
-; ZVFHMIN64-NEXT: sh a4, 156(sp)
-; ZVFHMIN64-NEXT: sh a3, 158(sp)
-; ZVFHMIN64-NEXT: vmv.x.s a3, v8
-; ZVFHMIN64-NEXT: and a4, a7, a1
-; ZVFHMIN64-NEXT: and a5, t0, a1
-; ZVFHMIN64-NEXT: and a6, t1, a1
-; ZVFHMIN64-NEXT: and a3, a3, a1
-; ZVFHMIN64-NEXT: sh a3, 144(sp)
-; ZVFHMIN64-NEXT: sh a6, 146(sp)
-; ZVFHMIN64-NEXT: sh a5, 148(sp)
-; ZVFHMIN64-NEXT: sh a4, 150(sp)
-; ZVFHMIN64-NEXT: and a1, a2, a1
-; ZVFHMIN64-NEXT: sh a1, 160(sp)
-; ZVFHMIN64-NEXT: addi a1, sp, 128
-; ZVFHMIN64-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN64-NEXT: vle16.v v8, (a1)
-; ZVFHMIN64-NEXT: addi sp, s0, -384
-; ZVFHMIN64-NEXT: .cfi_def_cfa sp, 384
-; ZVFHMIN64-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT: .cfi_restore ra
-; ZVFHMIN64-NEXT: .cfi_restore s0
-; ZVFHMIN64-NEXT: addi sp, sp, 384
-; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 0
-; ZVFHMIN64-NEXT: ret
+; CHECK-LABEL: v64f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 8
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: li a1, 64
+; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: ret
%r = call <64 x half> @llvm.fabs.v64f16(<64 x half> %v)
ret <64 x half> %r
}
diff --git a/llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll b/llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll
index 0e993f35ce85d..1135e78ebeda6 100644
--- a/llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll
@@ -75,22 +75,7 @@ entry:
define arm_aapcs_vfpcc <8 x half> @fabs_float16_t(<8 x half> %src) {
; CHECK-MVE-LABEL: fabs_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vmovx.f16 s4, s0
-; CHECK-MVE-NEXT: vabs.f16 s0, s0
-; CHECK-MVE-NEXT: vabs.f16 s4, s4
-; CHECK-MVE-NEXT: vins.f16 s0, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s1
-; CHECK-MVE-NEXT: vabs.f16 s4, s4
-; CHECK-MVE-NEXT: vabs.f16 s1, s1
-; CHECK-MVE-NEXT: vins.f16 s1, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s2
-; CHECK-MVE-NEXT: vabs.f16 s4, s4
-; CHECK-MVE-NEXT: vabs.f16 s2, s2
-; CHECK-MVE-NEXT: vins.f16 s2, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s3
-; CHECK-MVE-NEXT: vabs.f16 s4, s4
-; CHECK-MVE-NEXT: vabs.f16 s3, s3
-; CHECK-MVE-NEXT: vins.f16 s3, s4
+; CHECK-MVE-NEXT: vbic.i16 q0, #0x8000
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: fabs_float16_t:
@@ -105,10 +90,7 @@ entry:
define arm_aapcs_vfpcc <4 x float> @fabs_float32_t(<4 x float> %src) {
; CHECK-MVE-LABEL: fabs_float32_t:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vabs.f32 s3, s3
-; CHECK-MVE-NEXT: vabs.f32 s2, s2
-; CHECK-MVE-NEXT: vabs.f32 s1, s1
-; CHECK-MVE-NEXT: vabs.f32 s0, s0
+; CHECK-MVE-NEXT: vbic.i32 q0, #0x80000000
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: fabs_float32_t:
@@ -123,21 +105,17 @@ entry:
define arm_aapcs_vfpcc <2 x double> @fabs_float64_t(<2 x double> %src) {
; CHECK-LABEL: fabs_float64_t:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vldr d2, .LCPI5_0
-; CHECK-NEXT: vmov r12, r3, d0
-; CHECK-NEXT: vmov r0, r1, d2
-; CHECK-NEXT: vmov r0, r2, d1
-; CHECK-NEXT: lsrs r1, r1, #31
-; CHECK-NEXT: bfi r2, r1, #31, #1
-; CHECK-NEXT: bfi r3, r1, #31, #1
-; CHECK-NEXT: vmov d1, r0, r2
-; CHECK-NEXT: vmov d0, r12, r3
+; CHECK-NEXT: adr r0, .LCPI5_0
+; CHECK-NEXT: vldrw.u32 q1, [r0]
+; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 3
+; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI5_0:
-; CHECK-NEXT: .long 0 @ double 0
-; CHECK-NEXT: .long 0
+; CHECK-NEXT: .long 4294967295 @ 0xffffffff
+; CHECK-NEXT: .long 2147483647 @ 0x7fffffff
+; CHECK-NEXT: .long 4294967295 @ 0xffffffff
+; CHECK-NEXT: .long 2147483647 @ 0x7fffffff
entry:
%0 = call nnan ninf nsz <2 x double> @llvm.fabs.v2f64(<2 x double> %src)
ret <2 x double> %0
diff --git a/llvm/test/CodeGen/Thumb2/mve-vabd.ll b/llvm/test/CodeGen/Thumb2/mve-vabd.ll
index 3c35a29c0a84c..7b05414373e69 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vabd.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vabd.ll
@@ -14,30 +14,24 @@ define arm_aapcs_vfpcc void @vabd_v4f32(<4 x float> %x, <4 x float> %y, ptr %z)
; CHECK-MVE-NEXT: vmov q4, q1
; CHECK-MVE-NEXT: vmov q5, q0
; CHECK-MVE-NEXT: mov r8, r0
-; CHECK-MVE-NEXT: vmov r0, r6, d10
-; CHECK-MVE-NEXT: vmov r1, r7, d8
+; CHECK-MVE-NEXT: vmov r0, r9, d11
+; CHECK-MVE-NEXT: vmov r1, r6, d9
; CHECK-MVE-NEXT: bl __aeabi_fsub
-; CHECK-MVE-NEXT: mov r9, r0
-; CHECK-MVE-NEXT: mov r0, r6
-; CHECK-MVE-NEXT: mov r1, r7
+; CHECK-MVE-NEXT: mov r7, r0
+; CHECK-MVE-NEXT: vmov r0, r4, d10
+; CHECK-MVE-NEXT: vmov r1, r5, d8
; CHECK-MVE-NEXT: bl __aeabi_fsub
-; CHECK-MVE-NEXT: mov r6, r0
-; CHECK-MVE-NEXT: vmov r0, r7, d11
-; CHECK-MVE-NEXT: vmov r1, r4, d9
+; CHECK-MVE-NEXT: vmov q4[2], q4[0], r0, r7
+; CHECK-MVE-NEXT: mov r0, r9
+; CHECK-MVE-NEXT: mov r1, r6
; CHECK-MVE-NEXT: bl __aeabi_fsub
-; CHECK-MVE-NEXT: mov r5, r0
-; CHECK-MVE-NEXT: mov r0, r7
-; CHECK-MVE-NEXT: mov r1, r4
+; CHECK-MVE-NEXT: mov r6, r0
+; CHECK-MVE-NEXT: mov r0, r4
+; CHECK-MVE-NEXT: mov r1, r5
; CHECK-MVE-NEXT: bl __aeabi_fsub
-; CHECK-MVE-NEXT: bic r0, r0, #-2147483648
-; CHECK-MVE-NEXT: vmov s3, r0
-; CHECK-MVE-NEXT: bic r0, r5, #-2147483648
-; CHECK-MVE-NEXT: vmov s2, r0
-; CHECK-MVE-NEXT: bic r0, r6, #-2147483648
-; CHECK-MVE-NEXT: vmov s1, r0
-; CHECK-MVE-NEXT: bic r0, r9, #-2147483648
-; CHECK-MVE-NEXT: vmov s0, r0
-; CHECK-MVE-NEXT: vstrw.32 q0, [r8]
+; CHECK-MVE-NEXT: vmov q4[3], q4[1], r0, r6
+; CHECK-MVE-NEXT: vbic.i32 q4, #0x80000000
+; CHECK-MVE-NEXT: vstrw.32 q4, [r8]
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: add sp, #4
; CHECK-MVE-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
@@ -58,35 +52,32 @@ entry:
define arm_aapcs_vfpcc void @vabd_v8f16(<8 x half> %x, <8 x half> %y, ptr %z) {
; CHECK-MVE-LABEL: vabd_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: .save {r4, r5, r6, lr}
-; CHECK-MVE-NEXT: push {r4, r5, r6, lr}
+; CHECK-MVE-NEXT: .save {r4, r5, r7, lr}
+; CHECK-MVE-NEXT: push {r4, r5, r7, lr}
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-MVE-NEXT: mov r4, r0
-; CHECK-MVE-NEXT: vmov.u16 r0, q1[1]
+; CHECK-MVE-NEXT: vmov.u16 r0, q1[0]
; CHECK-MVE-NEXT: vmov q5, q1
; CHECK-MVE-NEXT: vmov q4, q0
; CHECK-MVE-NEXT: bl __aeabi_h2f
; CHECK-MVE-NEXT: mov r5, r0
-; CHECK-MVE-NEXT: vmov.u16 r0, q4[1]
+; CHECK-MVE-NEXT: vmov.u16 r0, q4[0]
; CHECK-MVE-NEXT: bl __aeabi_h2f
; CHECK-MVE-NEXT: mov r1, r5
; CHECK-MVE-NEXT: bl __aeabi_fsub
; CHECK-MVE-NEXT: bl __aeabi_f2h
-; CHECK-MVE-NEXT: mov r5, r0
-; CHECK-MVE-NEXT: vmov.u16 r0, q5[0]
+; CHECK-MVE-NEXT: vmov.16 q6[0], r0
+; CHECK-MVE-NEXT: vmov.u16 r0, q5[1]
; CHECK-MVE-NEXT: bl __aeabi_h2f
-; CHECK-MVE-NEXT: mov r6, r0
-; CHECK-MVE-NEXT: vmov.u16 r0, q4[0]
+; CHECK-MVE-NEXT: mov r5, r0
+; CHECK-MVE-NEXT: vmov.u16 r0, q4[1]
; CHECK-MVE-NEXT: bl __aeabi_h2f
-; CHECK-MVE-NEXT: mov r1, r6
+; CHECK-MVE-NEXT: mov r1, r5
; CHECK-MVE-NEXT: bl __aeabi_fsub
; CHECK-MVE-NEXT: bl __aeabi_f2h
-; CHECK-MVE-NEXT: bfc r0, #15, #17
-; CHECK-MVE-NEXT: bfc r5, #15, #17
-; CHECK-MVE-NEXT: vmov.16 q6[0], r0
+; CHECK-MVE-NEXT: vmov.16 q6[1], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q5[2]
-; CHECK-MVE-NEXT: vmov.16 q6[1], r5
; CHECK-MVE-NEXT: bl __aeabi_h2f
; CHECK-MVE-NEXT: mov r5, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q4[2]
@@ -94,7 +85,6 @@ define arm_aapcs_vfpcc void @vabd_v8f16(<8 x half> %x, <8 x half> %y, ptr %z) {
; CHECK-MVE-NEXT: mov r1, r5
; CHECK-MVE-NEXT: bl __aeabi_fsub
; CHECK-MVE-NEXT: bl __aeabi_f2h
-; CHECK-MVE-NEXT: bfc r0, #15, #17
; CHECK-MVE-NEXT: vmov.16 q6[2], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q5[3]
; CHECK-MVE-NEXT: bl __aeabi_h2f
@@ -104,7 +94,6 @@ define arm_aapcs_vfpcc void @vabd_v8f16(<8 x half> %x, <8 x half> %y, ptr %z) {
; CHECK-MVE-NEXT: mov r1, r5
; CHECK-MVE-NEXT: bl __aeabi_fsub
; CHECK-MVE-NEXT: bl __aeabi_f2h
-; CHECK-MVE-NEXT: bfc r0, #15, #17
; CHECK-MVE-NEXT: vmov.16 q6[3], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q5[4]
; CHECK-MVE-NEXT: bl __aeabi_h2f
@@ -114,7 +103,6 @@ define arm_aapcs_vfpcc void @vabd_v8f16(<8 x half> %x, <8 x half> %y, ptr %z) {
; CHECK-MVE-NEXT: mov r1, r5
; CHECK-MVE-NEXT: bl __aeabi_fsub
; CHECK-MVE-NEXT: bl __aeabi_f2h
-; CHECK-MVE-NEXT: bfc r0, #15, #17
; CHECK-MVE-NEXT: vmov.16 q6[4], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q5[5]
; CHECK-MVE-NEXT: bl __aeabi_h2f
@@ -124,7 +112,6 @@ define arm_aapcs_vfpcc void @vabd_v8f16(<8 x half> %x, <8 x half> %y, ptr %z) {
; CHECK-MVE-NEXT: mov r1, r5
; CHECK-MVE-NEXT: bl __aeabi_fsub
; CHECK-MVE-NEXT: bl __aeabi_f2h
-; CHECK-MVE-NEXT: bfc r0, #15, #17
; CHECK-MVE-NEXT: vmov.16 q6[5], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q5[6]
; CHECK-MVE-NEXT: bl __aeabi_h2f
@@ -134,7 +121,6 @@ define arm_aapcs_vfpcc void @vabd_v8f16(<8 x half> %x, <8 x half> %y, ptr %z) {
; CHECK-MVE-NEXT: mov r1, r5
; CHECK-MVE-NEXT: bl __aeabi_fsub
; CHECK-MVE-NEXT: bl __aeabi_f2h
-; CHECK-MVE-NEXT: bfc r0, #15, #17
; CHECK-MVE-NEXT: vmov.16 q6[6], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q5[7]
; CHECK-MVE-NEXT: bl __aeabi_h2f
@@ -144,11 +130,11 @@ define arm_aapcs_vfpcc void @vabd_v8f16(<8 x half> %x, <8 x half> %y, ptr %z) {
; CHECK-MVE-NEXT: mov r1, r5
; CHECK-MVE-NEXT: bl __aeabi_fsub
; CHECK-MVE-NEXT: bl __aeabi_f2h
-; CHECK-MVE-NEXT: bfc r0, #15, #17
; CHECK-MVE-NEXT: vmov.16 q6[7], r0
+; CHECK-MVE-NEXT: vbic.i16 q6, #0x8000
; CHECK-MVE-NEXT: vstrw.32 q6, [r4]
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11, d12, d13}
-; CHECK-MVE-NEXT: pop {r4, r5, r6, pc}
+; CHECK-MVE-NEXT: pop {r4, r5, r7, pc}
;
; CHECK-MVEFP-LABEL: vabd_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry
>From d64a0ce141a48a0dcbb60228753cb1d01a06049e Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Wed, 29 Apr 2026 17:06:17 +0800
Subject: [PATCH 3/3] fixup! revise heuristic
---
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 10 ++++++----
llvm/test/CodeGen/ARM/vfloatintrinsics.ll | 4 ++--
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index 3bf6e97a7cafe..a266f10fb2d5a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -2087,13 +2087,15 @@ SDValue VectorLegalizer::ExpandFABS(SDNode *Node) {
// a. Vector only has 1 element and target knows how to handle scalar
// FABS(either legal or custom expand or promote).
// b. Vector has more than 1 element and target supports scalar
- // FABS natively and vector length <= 3(2 AND + 1 OR).
+ // FABS natively and vector length <= 2(1 AND + 1 CONST).
+ // FIXME: Scalar construction instruction count varies in every architecture,
+ // here we assume 1 instruction for now.
if (VT.isFixedLengthVector()) {
EVT EltVT = VT.getVectorElementType();
if ((VT.getVectorNumElements() == 1 &&
- TLI.isOperationLegalOrCustomOrPromote(ISD::FCOPYSIGN, EltVT)) ||
- (VT.getVectorNumElements() < 4 &&
- TLI.isOperationLegal(ISD::FCOPYSIGN, EltVT) &&
+ TLI.isOperationLegalOrCustomOrPromote(ISD::FABS, EltVT)) ||
+ (VT.getVectorNumElements() < 3 &&
+ TLI.isOperationLegal(ISD::FABS, EltVT) &&
TLI.isExtractVecEltCheap(VT, 0)))
return SDValue();
}
diff --git a/llvm/test/CodeGen/ARM/vfloatintrinsics.ll b/llvm/test/CodeGen/ARM/vfloatintrinsics.ll
index 74782d44c7423..60e772961236a 100644
--- a/llvm/test/CodeGen/ARM/vfloatintrinsics.ll
+++ b/llvm/test/CodeGen/ARM/vfloatintrinsics.ll
@@ -341,8 +341,8 @@ define %v2f64 @test_v2f64.fma(%v2f64 %a, %v2f64 %b, %v2f64 %c) {
}
; CHECK-LABEL: test_v2f64.fabs:{{.*}}
define %v2f64 @test_v2f64.fabs(%v2f64 %a) {
- ; CHECK: bfc {{r[1,3]}}, #31, #1
- ; CHECK: bfc {{r[1,3]}}, #31, #1
+ ; CHECK: vld1.64
+ ; CHECK: vand
%1 = call %v2f64 @llvm.fabs.v2f64(%v2f64 %a)
ret %v2f64 %1
}
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