[llvm] [RISCV] Remove codegen for vp_trunc (PR #194886)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 29 08:30:16 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Luke Lau (lukel97)
<details>
<summary>Changes</summary>
Part of the work to remove trivial VP intrinsics from the RISC-V backend, see https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999
This splits off vp_truncate from #<!-- -->179622.
---
Patch is 89.98 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/194886.diff
13 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+6-126)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.h (+2-2)
- (modified) llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h (-1)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp-mask.ll (+12-12)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll (+148-687)
- (modified) llvm/test/CodeGen/RISCV/rvv/pr141907.ll (+2-3)
- (modified) llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll (+1-1)
- (modified) llvm/test/CodeGen/RISCV/rvv/vnsra-vp.ll (+6-12)
- (modified) llvm/test/CodeGen/RISCV/rvv/vnsrl-vp.ll (+6-12)
- (modified) llvm/test/CodeGen/RISCV/rvv/vp-vaaddu.ll (+23-26)
- (modified) llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll (+4-10)
- (modified) llvm/test/CodeGen/RISCV/rvv/vtrunc-vp-mask.ll (+12-13)
- (modified) llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll (+59-156)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index a896ba637059c..eb0bc24a48af8 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -873,7 +873,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::VP_REDUCE_OR, ISD::VP_REDUCE_XOR, ISD::VP_REDUCE_SMAX,
ISD::VP_REDUCE_SMIN, ISD::VP_REDUCE_UMAX, ISD::VP_REDUCE_UMIN,
ISD::VP_MERGE,
- ISD::VP_TRUNCATE,
ISD::EXPERIMENTAL_VP_REVERSE, ISD::EXPERIMENTAL_VP_SPLICE,
ISD::VP_CTTZ_ELTS, ISD::VP_CTTZ_ELTS_ZERO_UNDEF};
@@ -964,8 +963,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
OtherVT, Expand);
}
- setOperationAction(ISD::VP_TRUNCATE, VT, Custom);
-
setOperationAction(ISD::VECTOR_DEINTERLEAVE, VT, Custom);
setOperationAction(ISD::VECTOR_INTERLEAVE, VT, Custom);
@@ -1523,8 +1520,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::OR, ISD::XOR},
VT, Custom);
- setOperationAction(ISD::VP_TRUNCATE, VT, Custom);
-
setOperationAction(ISD::VP_MERGE, VT, Custom);
setOperationAction(ISD::EXPERIMENTAL_VP_SPLICE, VT, Custom);
@@ -1886,7 +1881,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::BUILD_VECTOR,
ISD::CONCAT_VECTORS,
ISD::VP_STORE,
- ISD::VP_TRUNCATE,
ISD::EXPERIMENTAL_VP_REVERSE,
ISD::SDIV,
ISD::UDIV,
@@ -7890,7 +7884,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
// Only custom-lower vector truncates
if (!Op.getSimpleValueType().isVector())
return Op;
- return lowerVectorTruncLike(Op, DAG);
+ return lowerVectorTrunc(Op, DAG);
case ISD::ANY_EXTEND:
case ISD::ZERO_EXTEND:
if (Op.getOperand(0).getValueType().isVector() &&
@@ -8957,8 +8951,6 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
case ISD::VP_SRL:
case ISD::VP_SHL:
return lowerVPOp(Op, DAG);
- case ISD::VP_TRUNCATE:
- return lowerVectorTruncLike(Op, DAG);
case ISD::EXPERIMENTAL_VP_STRIDED_LOAD:
return lowerVPStridedLoad(Op, DAG);
case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
@@ -10413,9 +10405,8 @@ SDValue RISCVTargetLowering::lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
// Custom-lower truncations from vectors to mask vectors by using a mask and a
// setcc operation:
// (vXi1 = trunc vXiN vec) -> (vXi1 = setcc (and vec, 1), 0, ne)
-SDValue RISCVTargetLowering::lowerVectorMaskTruncLike(SDValue Op,
+SDValue RISCVTargetLowering::lowerVectorMaskTrunc(SDValue Op,
SelectionDAG &DAG) const {
- bool IsVPTrunc = Op.getOpcode() == ISD::VP_TRUNCATE;
SDLoc DL(Op);
EVT MaskVT = Op.getValueType();
// Only expect to custom-lower truncations to mask types
@@ -10423,28 +10414,15 @@ SDValue RISCVTargetLowering::lowerVectorMaskTruncLike(SDValue Op,
"Unexpected type for vector mask lowering");
SDValue Src = Op.getOperand(0);
MVT VecVT = Src.getSimpleValueType();
- SDValue Mask, VL;
- if (IsVPTrunc) {
- Mask = Op.getOperand(1);
- VL = Op.getOperand(2);
- }
// If this is a fixed vector, we need to convert it to a scalable vector.
MVT ContainerVT = VecVT;
if (VecVT.isFixedLengthVector()) {
ContainerVT = getContainerForFixedLengthVector(VecVT);
Src = convertToScalableVector(ContainerVT, Src, DAG, Subtarget);
- if (IsVPTrunc) {
- MVT MaskContainerVT =
- getContainerForFixedLengthVector(Mask.getSimpleValueType());
- Mask = convertToScalableVector(MaskContainerVT, Mask, DAG, Subtarget);
- }
}
- if (!IsVPTrunc) {
- std::tie(Mask, VL) =
- getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget);
- }
+ auto [Mask, VL] = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget);
SDValue SplatOne = DAG.getConstant(1, DL, Subtarget.getXLenVT());
SDValue SplatZero = DAG.getConstant(0, DL, Subtarget.getXLenVT());
@@ -10465,10 +10443,9 @@ SDValue RISCVTargetLowering::lowerVectorMaskTruncLike(SDValue Op,
return Trunc;
}
-SDValue RISCVTargetLowering::lowerVectorTruncLike(SDValue Op,
+SDValue RISCVTargetLowering::lowerVectorTrunc(SDValue Op,
SelectionDAG &DAG) const {
unsigned Opc = Op.getOpcode();
- bool IsVPTrunc = Opc == ISD::VP_TRUNCATE;
SDLoc DL(Op);
MVT VT = Op.getSimpleValueType();
@@ -10477,7 +10454,7 @@ SDValue RISCVTargetLowering::lowerVectorTruncLike(SDValue Op,
// Truncates to mask types are handled differently
if (VT.getVectorElementType() == MVT::i1)
- return lowerVectorMaskTruncLike(Op, DAG);
+ return lowerVectorMaskTrunc(Op, DAG);
// RVV only has truncates which operate from SEW*2->SEW, so lower arbitrary
// truncates as a series of "RISCVISD::TRUNCATE_VECTOR_VL" nodes which
@@ -10493,25 +10470,13 @@ SDValue RISCVTargetLowering::lowerVectorTruncLike(SDValue Op,
"Unexpected vector truncate lowering");
MVT ContainerVT = SrcVT;
- SDValue Mask, VL;
- if (IsVPTrunc) {
- Mask = Op.getOperand(1);
- VL = Op.getOperand(2);
- }
if (SrcVT.isFixedLengthVector()) {
ContainerVT = getContainerForFixedLengthVector(SrcVT);
Src = convertToScalableVector(ContainerVT, Src, DAG, Subtarget);
- if (IsVPTrunc) {
- MVT MaskVT = getMaskTypeFor(ContainerVT);
- Mask = convertToScalableVector(MaskVT, Mask, DAG, Subtarget);
- }
}
SDValue Result = Src;
- if (!IsVPTrunc) {
- std::tie(Mask, VL) =
- getDefaultVLOps(SrcVT, ContainerVT, DL, DAG, Subtarget);
- }
+ auto [Mask, VL] = getDefaultVLOps(SrcVT, ContainerVT, DL, DAG, Subtarget);
unsigned NewOpc;
if (Opc == ISD::TRUNCATE_SSAT_S)
@@ -19216,89 +19181,6 @@ static SDValue performVP_STORECombine(SDNode *N, SelectionDAG &DAG,
VPStore->isTruncatingStore(), VPStore->isCompressingStore());
}
-// Peephole avgceil pattern.
-// %1 = zext <N x i8> %a to <N x i32>
-// %2 = zext <N x i8> %b to <N x i32>
-// %3 = add nuw nsw <N x i32> %1, splat (i32 1)
-// %4 = add nuw nsw <N x i32> %3, %2
-// %5 = lshr <N x i32> %4, splat (i32 1)
-// %6 = trunc <N x i32> %5 to <N x i8>
-static SDValue performVP_TRUNCATECombine(SDNode *N, SelectionDAG &DAG,
- const RISCVSubtarget &Subtarget) {
- EVT VT = N->getValueType(0);
-
- // Ignore fixed vectors.
- const TargetLowering &TLI = DAG.getTargetLoweringInfo();
- if (!VT.isScalableVector() || !TLI.isTypeLegal(VT))
- return SDValue();
-
- SDValue In = N->getOperand(0);
- SDValue Mask = N->getOperand(1);
- SDValue VL = N->getOperand(2);
-
- // Input should be a srl.
- if (In.getOpcode() != ISD::SRL)
- return SDValue();
-
- // Shift amount should be 1.
- if (!isOneOrOneSplat(In.getOperand(1)))
- return SDValue();
-
- // Shifted value should be an add.
- SDValue LHS = In.getOperand(0);
- if (LHS.getOpcode() != ISD::ADD)
- return SDValue();
-
- SDValue Operands[3];
-
- // Matches another add.
- auto FindAdd = [&](SDValue V, SDValue Other) {
- if (V.getOpcode() != ISD::ADD)
- return false;
-
- Operands[0] = Other;
- Operands[1] = V.getOperand(1);
- Operands[2] = V.getOperand(0);
- return true;
- };
-
- // We need to find another add in one of the operands.
- SDValue LHS0 = LHS.getOperand(0);
- SDValue LHS1 = LHS.getOperand(1);
- if (!FindAdd(LHS0, LHS1) && !FindAdd(LHS1, LHS0))
- return SDValue();
-
- // Now we have three operands of two additions. Check that one of them is a
- // constant vector with ones.
- auto I = llvm::find_if(Operands,
- [](const SDValue &Op) { return isOneOrOneSplat(Op); });
- if (I == std::end(Operands))
- return SDValue();
- // We found a vector with ones, move if it to the end of the Operands array.
- std::swap(*I, Operands[2]);
-
- // Make sure the other 2 operands can be promoted from the result type.
- for (SDValue Op : drop_end(Operands)) {
- if (Op.getOpcode() != ISD::ZERO_EXTEND)
- return SDValue();
- // Input must be the same size or smaller than our result.
- if (Op.getOperand(0).getScalarValueSizeInBits() > VT.getScalarSizeInBits())
- return SDValue();
- }
-
- // Pattern is detected.
- // Rebuild the zero extends in case the inputs are smaller than our result.
- SDValue NewOp0 = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(Operands[0]), VT,
- Operands[0].getOperand(0));
- SDValue NewOp1 = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(Operands[1]), VT,
- Operands[1].getOperand(0));
- // Build a AVGCEILU_VL which will be selected as a VAADDU with RNU rounding
- // mode.
- SDLoc DL(N);
- return DAG.getNode(RISCVISD::AVGCEILU_VL, DL, VT,
- {NewOp0, NewOp1, DAG.getUNDEF(VT), Mask, VL});
-}
-
// Convert from one FMA opcode to another based on whether we are negating the
// multiply result and/or the accumulator.
// NOTE: Only supports RVV operations with VL.
@@ -21498,8 +21380,6 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
if (SDValue V = combineTruncOfSraSext(N, DAG))
return V;
return combineTruncToVnclip(N, DAG, Subtarget);
- case ISD::VP_TRUNCATE:
- return performVP_TRUNCATECombine(N, DAG, Subtarget);
case ISD::TRUNCATE:
return performTRUNCATECombine(N, DAG, Subtarget);
case ISD::SELECT:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index b9229782e120f..a39c0f76c3b79 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -504,8 +504,8 @@ class RISCVTargetLowering : public TargetLowering {
SDValue lowerVectorMaskSplat(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
int64_t ExtTrueVal) const;
- SDValue lowerVectorMaskTruncLike(SDValue Op, SelectionDAG &DAG) const;
- SDValue lowerVectorTruncLike(SDValue Op, SelectionDAG &DAG) const;
+ SDValue lowerVectorMaskTrunc(SDValue Op, SelectionDAG &DAG) const;
+ SDValue lowerVectorTrunc(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerVectorFPExtendOrRound(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index 8b76ca6829949..477c419228a6b 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -398,7 +398,6 @@ class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
Intrinsic::vp_sdiv,
Intrinsic::vp_srem,
Intrinsic::vp_store,
- Intrinsic::vp_trunc,
Intrinsic::vp_udiv,
Intrinsic::vp_urem};
if (!ST->hasVInstructions() ||
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp-mask.ll
index 05ac11d1ca9d7..92b6614bed438 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp-mask.ll
@@ -5,9 +5,9 @@
define <2 x i1> @vtrunc_v2i1_v2i16(<2 x i16> %a, <2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i1_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vand.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%v = call <2 x i1> @llvm.vp.trunc.v2i1.v2i16(<2 x i16> %a, <2 x i1> %m, i32 %vl)
ret <2 x i1> %v
@@ -16,7 +16,7 @@ define <2 x i1> @vtrunc_v2i1_v2i16(<2 x i16> %a, <2 x i1> %m, i32 zeroext %vl) {
define <2 x i1> @vtrunc_v2i1_v2i16_unmasked(<2 x i16> %a, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i1_v2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
@@ -27,9 +27,9 @@ define <2 x i1> @vtrunc_v2i1_v2i16_unmasked(<2 x i16> %a, i32 zeroext %vl) {
define <2 x i1> @vtrunc_v2i1_v2i32(<2 x i32> %a, <2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i1_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vand.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%v = call <2 x i1> @llvm.vp.trunc.v2i1.v2i32(<2 x i32> %a, <2 x i1> %m, i32 %vl)
ret <2 x i1> %v
@@ -38,7 +38,7 @@ define <2 x i1> @vtrunc_v2i1_v2i32(<2 x i32> %a, <2 x i1> %m, i32 zeroext %vl) {
define <2 x i1> @vtrunc_v2i1_v2i32_unmasked(<2 x i32> %a, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i1_v2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
@@ -49,9 +49,9 @@ define <2 x i1> @vtrunc_v2i1_v2i32_unmasked(<2 x i32> %a, i32 zeroext %vl) {
define <2 x i1> @vtrunc_v2i1_v2i64(<2 x i64> %a, <2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i1_v2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vand.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%v = call <2 x i1> @llvm.vp.trunc.v2i1.v2i64(<2 x i64> %a, <2 x i1> %m, i32 %vl)
ret <2 x i1> %v
@@ -60,7 +60,7 @@ define <2 x i1> @vtrunc_v2i1_v2i64(<2 x i64> %a, <2 x i1> %m, i32 zeroext %vl) {
define <2 x i1> @vtrunc_v2i1_v2i64_unmasked(<2 x i64> %a, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i1_v2i64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
index f992d1f8f7eee..d726fd0061f07 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
@@ -5,8 +5,8 @@
define <2 x i7> @vtrunc_v2i7_v2i16(<2 x i16> %a, <2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i7_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = call <2 x i7> @llvm.vp.trunc.v2i7.v2i16(<2 x i16> %a, <2 x i1> %m, i32 %vl)
ret <2 x i7> %v
@@ -15,8 +15,8 @@ define <2 x i7> @vtrunc_v2i7_v2i16(<2 x i16> %a, <2 x i1> %m, i32 zeroext %vl) {
define <2 x i8> @vtrunc_v2i8_v2i15(<2 x i15> %a, <2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i8_v2i15:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i15(<2 x i15> %a, <2 x i1> %m, i32 %vl)
ret <2 x i8> %v
@@ -25,8 +25,8 @@ define <2 x i8> @vtrunc_v2i8_v2i15(<2 x i15> %a, <2 x i1> %m, i32 zeroext %vl) {
define <2 x i8> @vtrunc_v2i8_v2i16(<2 x i16> %a, <2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i8_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i16(<2 x i16> %a, <2 x i1> %m, i32 %vl)
ret <2 x i8> %v
@@ -35,7 +35,7 @@ define <2 x i8> @vtrunc_v2i8_v2i16(<2 x i16> %a, <2 x i1> %m, i32 zeroext %vl) {
define <2 x i8> @vtrunc_v2i8_v2i16_unmasked(<2 x i16> %a, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i8_v2i16_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i16(<2 x i16> %a, <2 x i1> <i1 true, i1 true>, i32 %vl)
@@ -45,27 +45,14 @@ define <2 x i8> @vtrunc_v2i8_v2i16_unmasked(<2 x i16> %a, i32 zeroext %vl) {
define <128 x i7> @vtrunc_v128i7_v128i16(<128 x i16> %a, <128 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v128i7_v128i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; CHECK-NEXT: vmv8r.v v24, v8
-; CHECK-NEXT: li a1, 64
-; CHECK-NEXT: vslidedown.vi v12, v0, 8
-; CHECK-NEXT: mv a2, a0
-; CHECK-NEXT: bltu a0, a1, .LBB4_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a2, 64
-; CHECK-NEXT: .LBB4_2:
-; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v24, 0, v0.t
-; CHECK-NEXT: addi a2, a0, -64
-; CHECK-NEXT: sltu a0, a0, a2
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a0, a0, a2
-; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: li a0, 64
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t
-; CHECK-NEXT: li a0, 128
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v24, a1
+; CHECK-NEXT: vnsrl.wi v24, v16, 0
+; CHECK-NEXT: vnsrl.wi v16, v8, 0
+; CHECK-NEXT: li a1, 128
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT: vslideup.vx v16, v24, a0
+; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
%v = call <128 x i7> @llvm.vp.trunc.v128i7.v128i16(<128 x i16> %a, <128 x i1> %m, i32 %vl)
ret <128 x i7> %v
@@ -74,10 +61,10 @@ define <128 x i7> @vtrunc_v128i7_v128i16(<128 x i16> %a, <128 x i1> %m, i32 zero
define <2 x i8> @vtrunc_v2i8_v2i32(<2 x i32> %a, <2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i8_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i32(<2 x i32> %a, <2 x i1> %m, i32 %vl)
ret <2 x i8> %v
@@ -86,7 +73,7 @@ define <2 x i8> @vtrunc_v2i8_v2i32(<2 x i32> %a, <2 x i1> %m, i32 zeroext %vl) {
define <2 x i8> @vtrunc_v2i8_v2i32_unmasked(<2 x i32> %a, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i8_v2i32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
@@ -98,12 +85,12 @@ define <2 x i8> @vtrunc_v2i8_v2i32_unmasked(<2 x i32> %a, i32 zeroext %vl) {
define <2 x i8> @vtrunc_v2i8_v2i64(<2 x i64> %a, <2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i8_v2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i64(<2 x i64> %a, <2 x i1> %m, i32 %vl)
ret ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/194886
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