[llvm] [X86] Add custom ISD::VEC_REDUCE_*MIN/MAX lowering (PR #194848)

[Simon Pilgrim via llvm-commits]

================
@@ -29826,6 +29835,88 @@ static SDValue LowerMINMAX(SDValue Op, const X86Subtarget &Subtarget,
   return SDValue();
 }
 
+// Attempt to replace an min/max v8i16/v16i8 horizontal reduction with
+// PHMINPOSUW.
+static SDValue LowerMINMAX_REDUCE(SDValue Op, const X86Subtarget &Subtarget,
+                                  SelectionDAG &DAG) {
+  EVT ExtractVT = Op.getValueType();
+  if (ExtractVT != MVT::i16 && ExtractVT != MVT::i8)
+    return SDValue();
+
+  // Check for SMAX/SMIN/UMAX/UMIN horizontal reduction patterns.
+  ISD::NodeType BinOp = ISD::getVecReduceBaseOpcode(Op.getOpcode());
+
+  SDValue Src = Op.getOperand(0);
+  EVT SrcVT = Src.getValueType();
+  EVT SrcSVT = SrcVT.getScalarType();
+  if (SrcSVT != ExtractVT || (SrcVT.getSizeInBits() % 128) != 0)
----------------
RKSimon wrote:

ISDOpcodes.h:
```
  /// Integer reductions may have a result type larger than the vector element
  /// type. However, the reduction is performed using the vector element type
  /// and the value in the top bits is unspecified.
```
same as build_vector ./ insert+extract_vector_elt etc.

https://github.com/llvm/llvm-project/pull/194848