[llvm] [AArch64] SME definitions for C1-Ultra scheduling model (PR #194850)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 29 06:09:39 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Nashe Mncube (nasherm)
<details>
<summary>Changes</summary>
This patch extends the C1-Ultra scheduling model to add support SME instructions. These instructions differ from legacy scheduling model instruction definitions in that they are sent to the CME co-processor when in streaming mode. Modelling these instructions requires several changes to the scheduling model
- predicating the process resource groups for SME instructions based on whether we are executing in streaming SVE mode or not
- definitions of CME processor resource. Instructions sent to this co-processor are modelled as having 0 latency when in streaming SVE mode as the software optimization guide mentions that these latencies are not-applicable
- tests for SME instructions
https://developer.arm.com/documentation/111079/3-0
Assisted by Codex
---
Patch is 131.87 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/194850.diff
15 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64.td (+3-1)
- (modified) llvm/lib/Target/AArch64/AArch64Features.td (+3)
- (modified) llvm/lib/Target/AArch64/AArch64SchedC1Ultra.td (+519-266)
- (modified) llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td (+3-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td (+4-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td (+1-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td (+3-2)
- (modified) llvm/lib/Target/AArch64/AArch64SchedNeoverseV3.td (+3-2)
- (modified) llvm/lib/Target/AArch64/AArch64SchedNeoverseV3AE.td (+3-2)
- (modified) llvm/lib/Target/AArch64/AArch64SchedOlympus.td (+7-7)
- (modified) llvm/lib/Target/AArch64/AArch64SchedPredicates.td (+3)
- (added) llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-sme-instructions.s (+135)
- (added) llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-streaming-cme-instructions.s (+244)
- (added) llvm/test/tools/llvm-mca/AArch64/Inputs/sme-instructions.s (+43)
- (added) llvm/test/tools/llvm-mca/AArch64/Inputs/streaming-cme-instructions.s (+22)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 1d6cea38dc163..8aad739eef4cb 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -60,7 +60,9 @@ include "AArch64SystemOperands.td"
class AArch64Unsupported { list<Predicate> F; }
-let F = [HasSVE2p1, HasSVE2p1_or_SME2, HasSVE2p1_or_StreamingSME2, HasSVE2p1_or_SME2p1] in
+let F = [HasSVE2p1, HasSVE2p1_or_SME, HasSVE2p1_or_SME2,
+ HasSVE2p1_or_StreamingSME2, HasSVE2p1_or_SME2p1,
+ HasSMEandIsNonStreamingSafe] in
def SVE2p1Unsupported : AArch64Unsupported;
def SVE2Unsupported : AArch64Unsupported {
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index 0c3d757da8f6b..e35f30ab879dc 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -410,6 +410,9 @@ def FeatureRME : Extension<"rme", "RME", "FEAT_RME",
def FeatureSME : ExtensionWithMArch<"sme", "SME", "FEAT_SME",
"Enable Scalable Matrix Extension (SME)", [FeatureBF16, FeatureFullFP16]>;
+def FeatureMCAStreamingSched : SubtargetFeature<
+ "mca-streaming-sched", "MCAStreamingSched", "true",
+ "Enable streaming-SVE schedule predicates for MC analysis tools">;
def FeatureSMEF64F64 : ExtensionWithMArch<"sme-f64f64", "SMEF64F64", "FEAT_SME_F64F64",
"Enable Scalable Matrix Extension (SME) F64F64 instructions", [FeatureSME]>;
diff --git a/llvm/lib/Target/AArch64/AArch64SchedC1Ultra.td b/llvm/lib/Target/AArch64/AArch64SchedC1Ultra.td
index 1d2f96086b42c..6c38f261ea7a6 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedC1Ultra.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedC1Ultra.td
@@ -55,7 +55,9 @@ def C1UUnitLS0 : ProcResource<1>; // Load/Store 0
def C1UUnitLS1 : ProcResource<1>; // Load/Store 1
def C1UUnitL23 : ProcResource<2>; // Load 2/3
def C1UUnitD : ProcResource<2>; // Store data 0/1
-def C1UUnitCME : ProcResource<1>; // CME operations block
+def C1UUnitCME2X : ProcResource<2>; // CME operations block (2-way)
+def C1UUnitCME3X : ProcResource<3>; // CME operations block (3-way)
+def C1UUnitCME4X : ProcResource<4>; // CME operations block (4-way)
def C1UUnitFlg : ProcResource<4>; // Flags
def C1UUnitS : ProcResGroup<[C1UUnitS0, C1UUnitS1, C1UUnitS2, C1UUnitS3,
@@ -98,6 +100,28 @@ def : WriteRes<WriteLDHi, []> { let Latency = 4; }
// Define generic 0 micro-op types.
def C1UWrite_0c : SchedWriteRes<[]> { let Latency = 0; }
+def C1UWrite_0c_1C_4X : SchedWriteRes<[C1UUnitCME4X]> { let Latency = 0; }
+def C1UWrite_0c_1M_1C_2X : SchedWriteRes<[C1UUnitM, C1UUnitCME2X]> {
+ let Latency = 0;
+}
+def C1UWrite_0c_1SA_1C_2X : SchedWriteRes<[C1UUnitSA, C1UUnitCME2X]> {
+ let Latency = 0;
+}
+def C1UWrite_0c_1L_1C_3X : SchedWriteRes<[C1UUnitL, C1UUnitCME3X]> {
+ let Latency = 0;
+}
+def C1UWrite_0c_1V01_1L_1C_3X : SchedWriteRes<[C1UUnitV01, C1UUnitL,
+ C1UUnitCME3X]> {
+ let Latency = 0;
+}
+def C1UWrite_0c_1I_1L_1C_3X : SchedWriteRes<[C1UUnitI, C1UUnitL,
+ C1UUnitCME3X]> {
+ let Latency = 0;
+}
+def C1UWrite_0c_1I_1V01_1L_1C_3X : SchedWriteRes<[C1UUnitI, C1UUnitV01,
+ C1UUnitL, C1UUnitCME3X]> {
+ let Latency = 0;
+}
// Define a small set of generic 1 micro-op types as placeholders.
def C1UWrite_1c_1B : SchedWriteRes<[C1UUnitB]> { let Latency = 1; }
@@ -111,6 +135,8 @@ def C1UWrite_2c_1I4 : SchedWriteRes<[C1UUnitI4]> { let Latency = 2; }
def C1UWrite_1c_1M : SchedWriteRes<[C1UUnitM]> { let Latency = 1; }
def C1UWrite_1c_2M : SchedWriteRes<[C1UUnitM, C1UUnitM]> { let Latency = 1; }
def C1UWrite_2c_1M : SchedWriteRes<[C1UUnitM]> { let Latency = 2; }
+def C1UWrite_2c_2M : SchedWriteRes<[C1UUnitM, C1UUnitM]> { let Latency = 2; }
+def C1UWrite_3c_1M : SchedWriteRes<[C1UUnitM]> { let Latency = 3; }
def C1UWrite_2c_1M0 : SchedWriteRes<[C1UUnitM0]> { let Latency = 2; }
def C1UWrite_3c_1M0 : SchedWriteRes<[C1UUnitM0]> { let Latency = 3; }
def C1UWrite_4c_1M0 : SchedWriteRes<[C1UUnitM0]> { let Latency = 4; }
@@ -122,6 +148,7 @@ def C1UWrite_1c_1V : SchedWriteRes<[C1UUnitV]> { let Latency = 1; }
def C1UWrite_2c_1V : SchedWriteRes<[C1UUnitV]> { let Latency = 2; }
def C1UWrite_2c_3V : SchedWriteRes<[C1UUnitV, C1UUnitV, C1UUnitV]> { let Latency = 2; }
def C1UWrite_3c_1V : SchedWriteRes<[C1UUnitV]> { let Latency = 3; }
+def C1UWrite_3c_2V : SchedWriteRes<[C1UUnitV, C1UUnitV]> { let Latency = 3; }
def C1UWrite_4c_1V : SchedWriteRes<[C1UUnitV]> { let Latency = 4; }
def C1UWrite_4c_2V : SchedWriteRes<[C1UUnitV, C1UUnitV]> { let Latency = 4; }
def C1UWrite_4c_3V : SchedWriteRes<[C1UUnitV, C1UUnitV, C1UUnitV]> { let Latency = 4; }
@@ -640,6 +667,22 @@ def C1URd_ZBFMAL : SchedReadAdvance<3, [C1UWr_ZBFMAL]>;
def C1UWr_Pred : SchedWriteRes<[C1UUnitM, C1UUnitM]> { let Latency = 2; }
def C1URd_Pred : SchedReadAdvance<1, [C1UWr_Pred]>;
+class C1UStreamingSchedWrite<SchedWrite StreamingWrite, SchedWrite BaseWrite>
+ : SchedWriteVariant<[
+ SchedVar<SMEStreamingSchedPred, [StreamingWrite]>,
+ SchedVar<SMEMCStreamingSchedPred, [StreamingWrite]>,
+ SchedVar<NoSchedPred, [BaseWrite]>
+ ]>;
+
+class C1USMEStreamingSchedWrite<SchedWrite StreamingWrite,
+ SchedWrite SMEWrite>
+ : SchedWriteVariant<[
+ SchedVar<SMEStreamingSchedPred, [StreamingWrite]>,
+ SchedVar<SMEMCStreamingSchedPred, [StreamingWrite]>,
+ SchedVar<SMESchedPred, [SMEWrite]>,
+ SchedVar<NoSchedPred, [C1UWrite_0c]>
+ ]>;
+
// Predicate controlled types
def C1UWrite_ArithI : SchedWriteVariant<[
SchedVar<IsCheapLSL, [C1UWrite_1c_1I]>,
@@ -703,6 +746,162 @@ def C1UWrite_3or4c_1M0_1M : SchedWriteVariant<[
SchedVar<NeoversePdIsPg, [C1UWrite_4c_1M0_1M]>,
SchedVar<NoSchedPred, [C1UWrite_3c_1M0_1M]>]>;
+def C1UWr_FMA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWr_FMA>;
+def C1UWR_VA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWR_VA>;
+def C1UWR_VDOT_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWR_VDOT>;
+def C1UWR_VMMA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWR_VMMA>;
+def C1UWR_VMA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWR_VMA>;
+def C1UWR_VMAH_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWR_VMAH>;
+def C1UWR_VPA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWR_VPA>;
+def C1UWR_VSA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWR_VSA>;
+def C1UWR_VFCMA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWR_VFCMA>;
+def C1UWR_VFMA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWR_VFMA>;
+def C1UWR_VBFDOT_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWR_VBFDOT>;
+def C1UWR_VBFMMA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWR_VBFMMA>;
+def C1UWR_VBFMAL_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWR_VBFMAL>;
+def C1UWr_ZA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWr_ZA>;
+def C1UWr_ZPA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWr_ZPA>;
+def C1UWr_ZSA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWr_ZSA>;
+def C1UWr_ZDOTB_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWr_ZDOTB>;
+def C1UWr_ZDOTH_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWr_ZDOTH>;
+def C1UWr_ZCMABHS_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWr_ZCMABHS>;
+def C1UWr_ZMMA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWr_ZMMA>;
+def C1UWr_ZMA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWr_ZMA>;
+def C1UWr_ZMASQL_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWr_ZMASQL>;
+def C1UWr_ZFCMA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWr_ZFCMA>;
+def C1UWr_ZFMA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWr_ZFMA>;
+def C1UWr_ZFMAL_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWr_ZFMAL>;
+def C1UWr_ZBFDOT_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWr_ZBFDOT>;
+def C1UWr_ZBFMMA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWr_ZBFMMA>;
+def C1UWr_ZBFMAL_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWr_ZBFMAL>;
+
+def C1UWrite_2c_1V_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_2c_1V>;
+def C1UWrite_2c_1V0_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_2c_1V0>;
+def C1UWrite_2c_1V01_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_2c_1V01>;
+def C1UWrite_2c_1V0134_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_2c_1V0134>;
+def C1UWrite_3c_1V_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_3c_1V>;
+def C1UWrite_3c_1V01_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_3c_1V01>;
+def C1UWrite_3c_1V0134_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_3c_1V0134>;
+def C1UWrite_3c_1V1_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_3c_1V1>;
+def C1UWrite_4c_1V_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_4c_1V>;
+def C1UWrite_4c_1V0_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_4c_1V0>;
+def C1UWrite_4c_1V0134_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_4c_1V0134>;
+def C1UWrite_4c_1V0134_1V_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_4c_1V0134_1V>;
+def C1UWrite_4c_1V_1V0134_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_4c_1V_1V0134>;
+def C1UWrite_4c_2V_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_4c_2V>;
+def C1UWrite_4c_2V0134_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_4c_2V0134>;
+def C1UWrite_5c_1V1_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_5c_1V1>;
+def C1UWrite_6c_1V0134_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_6c_1V0134>;
+def C1UWrite_6c_1V_2V0134_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_6c_1V_2V0134>;
+def C1UWrite_6c_2V1_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_6c_2V1>;
+def C1UWrite_6c_2V_1V0134_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_6c_2V_1V0134>;
+def C1UWrite_6c_3V_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_6c_3V>;
+def C1UWrite_6c_6V0_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_6c_6V0>;
+def C1UWrite_8c_1V1_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_8c_1V1>;
+def C1UWrite_8c_1V1_4rc_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_8c_1V1_4rc>;
+def C1UWrite_8c_1V_3V0134_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_8c_1V_3V0134>;
+def C1UWrite_8c_4V_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_8c_4V>;
+def C1UWrite_9c_1V1_2rc_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_9c_1V1_2rc>;
+def C1UWrite_10c_10V0_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_10c_10V0>;
+def C1UWrite_11c_1V0_4rc_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_11c_1V0_4rc>;
+def C1UWrite_11c_1V1_4rc_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_11c_1V1_4rc>;
+def C1UWrite_12c_1V0_8rc_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_12c_1V0_8rc>;
+def C1UWrite_12c_1V1_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_12c_1V1>;
+def C1UWrite_12c_1V1_8rc_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_12c_1V1_8rc>;
+def C1UWrite_12c_7V0_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_12c_7V0>;
+def C1UWrite_13c_1V0_2rc_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_13c_1V0_2rc>;
+def C1UWrite_13c_1V1_2rc_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_13c_1V1_2rc>;
+def C1UWrite_20c_7V0_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_20c_7V0>;
+
+def C1UWrite_3c_1M0_CME : C1UStreamingSchedWrite<C1UWrite_0c_1M_1C_2X, C1UWrite_3c_1M0>;
+def C1UWrite_3c_1M0_1V_CME : C1UStreamingSchedWrite<C1UWrite_0c_1M_1C_2X, C1UWrite_3c_1M0_1V>;
+def C1UWrite_5c_1M0_1V_CME : C1UStreamingSchedWrite<C1UWrite_0c_1M_1C_2X, C1UWrite_5c_1M0_1V>;
+def C1UWrite_5c_1V1_1V01_CME : C1UStreamingSchedWrite<C1UWrite_0c_1M_1C_2X, C1UWrite_5c_1V1_1V01>;
+def C1UWrite_5c_1V_1M0_CME : C1UStreamingSchedWrite<C1UWrite_0c_1M_1C_2X, C1UWrite_5c_1V_1M0>;
+def C1UWrite_7c_1M0_1V0134_CME : C1UStreamingSchedWrite<C1UWrite_0c_1M_1C_2X, C1UWrite_7c_1M0_1V0134>;
+def C1UWrite_8c_1M0_1V1_1V01_CME : C1UStreamingSchedWrite<C1UWrite_0c_1M_1C_2X, C1UWrite_8c_1M0_1V1_1V01>;
+
+def C1UWrite_6c_1L_CME : C1UStreamingSchedWrite<C1UWrite_0c_1L_1C_3X, C1UWrite_6c_1L>;
+def C1UWrite_6c_1L_1I_CME : C1UStreamingSchedWrite<C1UWrite_0c_1I_1L_1C_3X, C1UWrite_6c_1L_1I>;
+def C1UWrite_6c_1L_1M_CME : C1UStreamingSchedWrite<C1UWrite_0c_1L_1C_3X, C1UWrite_6c_1L_1M>;
+def C1UWrite_6c_2L_1I_CME : C1UStreamingSchedWrite<C1UWrite_0c_1I_1L_1C_3X, C1UWrite_6c_2L_1I>;
+def C1UWrite_7c_1L_1I_CME : C1UStreamingSchedWrite<C1UWrite_0c_1I_1L_1C_3X, C1UWrite_7c_1L_1I>;
+def C1UWrite_8c_2L_2V_CME : C1UStreamingSchedWrite<C1UWrite_0c_1V01_1L_1C_3X, C1UWrite_8c_2L_2V>;
+def C1UWrite_8c_3L_3V_CME : C1UStreamingSchedWrite<C1UWrite_0c_1V01_1L_1C_3X, C1UWrite_8c_3L_3V>;
+def C1UWrite_9c_1V01_1L_CME : C1UStreamingSchedWrite<C1UWrite_0c_1V01_1L_1C_3X, C1UWrite_9c_1V01_1L>;
+def C1UWrite_9c_2L_2V_1I_CME : C1UStreamingSchedWrite<C1UWrite_0c_1I_1V01_1L_1C_3X, C1UWrite_9c_2L_2V_1I>;
+def C1UWrite_9c_3L_3V_1I_CME : C1UStreamingSchedWrite<C1UWrite_0c_1I_1V01_1L_1C_3X, C1UWrite_9c_3L_3V_1I>;
+def C1UWrite_10c_4L_8V_CME : C1UStreamingSchedWrite<C1UWrite_0c_1V01_1L_1C_3X, C1UWrite_10c_4L_8V>;
+def C1UWrite_11c_4L_8V_1I_CME : C1UStreamingSchedWrite<C1UWrite_0c_1I_1V01_1L_1C_3X, C1UWrite_11c_4L_8V_1I>;
+
+def C1UWrite_LdrQ_CME : SchedWriteVariant<[
+ SchedVar<FPIsQForm, [C1UWrite_7c_1L_1I_CME]>,
+ SchedVar<NoSchedPred, [C1UWrite_6c_1L_CME]>]>;
+
+def C1UWrite_1c_1SA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1SA_1C_2X, C1UWrite_1c_1SA>;
+def C1UWrite_2c_1SA_1V01_CME : C1UStreamingSchedWrite<C1UWrite_0c_1SA_1C_2X, C1UWrite_2c_1SA_1V01>;
+def C1UWrite_2c_1SA_1V01_1I_CME : C1UStreamingSchedWrite<C1UWrite_0c_1SA_1C_2X, C1UWrite_2c_1SA_1V01_1I>;
+def C1UWrite_2or4c_1SA_1V01_CME : C1UStreamingSchedWrite<C1UWrite_0c_1SA_1C_2X, C1UWrite_2or4c_1SA_1V01>;
+def C1UWrite_2or4c_3SA_6V01_CME : C1UStreamingSchedWrite<C1UWrite_0c_1SA_1C_2X, C1UWrite_2or4c_3SA_6V01>;
+def C1UWrite_2c_2SA_2V01_CME : C1UStreamingSchedWrite<C1UWrite_0c_1SA_1C_2X, C1UWrite_2c_2SA_2V01>;
+def C1UWrite_4c_2SA_2V01_CME : C1UStreamingSchedWrite<C1UWrite_0c_1SA_1C_2X, C1UWrite_4c_2SA_2V01>;
+def C1UWrite_4c_2SA_2V01_1I_CME : C1UStreamingSchedWrite<C1UWrite_0c_1SA_1C_2X, C1UWrite_4c_2SA_2V01_1I>;
+def C1UWrite_4or6c_3SA_3V01_CME : C1UStreamingSchedWrite<C1UWrite_0c_1SA_1C_2X, C1UWrite_4or6c_3SA_3V01>;
+def C1UWrite_5c_3SA_3V01_CME : C1UStreamingSchedWrite<C1UWrite_0c_1SA_1C_2X, C1UWrite_5c_3SA_3V01>;
+def C1UWrite_5c_3SA_3V01_1I_CME : C1UStreamingSchedWrite<C1UWrite_0c_1SA_1C_2X, C1UWrite_5c_3SA_3V01_1I>;
+def C1UWrite_5or7c_3SA_6V01_CME : C1UStreamingSchedWrite<C1UWrite_0c_1SA_1C_2X, C1UWrite_5or7c_3SA_6V01>;
+def C1UWrite_5or7c_5SA_5V01_CME : C1UStreamingSchedWrite<C1UWrite_0c_1SA_1C_2X, C1UWrite_5or7c_5SA_5V01>;
+def C1UWrite_7c_4SA_4V01_CME : C1UStreamingSchedWrite<C1UWrite_0c_1SA_1C_2X, C1UWrite_7c_4SA_4V01>;
+def C1UWrite_7c_4SA_4V01_1I_CME : C1UStreamingSchedWrite<C1UWrite_0c_1SA_1C_2X, C1UWrite_7c_4SA_4V01_1I>;
+
+def C1UWrite_StrQ_CME : SchedWriteVariant<[
+ SchedVar<FPIsQForm, [C1UWrite_2c_1SA_1V01_1I_CME]>,
+ SchedVar<NoSchedPred, [C1UWrite_2c_1SA_1V01_CME]>]>;
+
+// SME predicates
+
+def C1UWrite_1c_1I_Streaming : SchedWriteVariant<[
+ SchedVar<SMESchedPred, [C1UWrite_1c_1I]>,
+ SchedVar<NoSchedPred, [C1UWrite_0c]>]>;
+
+def C1UWrite_1c_1M_Streaming : SchedWriteVariant<[
+ SchedVar<SMESchedPred, [C1UWrite_1c_1M]>,
+ SchedVar<NoSchedPred, [C1UWrite_0c]>]>;
+
+def C1UWrite_2c_1V_Streaming : SchedWriteVariant<[
+ SchedVar<SMESchedPred, [C1UWrite_2c_1V]>,
+ SchedVar<NoSchedPred, [C1UWrite_0c]>]>;
+
+def C1UWrite_3c_1V_Streaming : SchedWriteVariant<[
+ SchedVar<SMESchedPred, [C1UWrite_3c_1V]>,
+ SchedVar<NoSchedPred, [C1UWrite_0c]>]>;
+
+def C1UWrite_3c_1V01_Streaming : SchedWriteVariant<[
+ SchedVar<SMESchedPred, [C1UWrite_3c_1V01]>,
+ SchedVar<NoSchedPred, [C1UWrite_0c]>]>;
+
+def C1UWrite_4c_1V_Streaming : SchedWriteVariant<[
+ SchedVar<SMESchedPred, [C1UWrite_4c_1V]>,
+ SchedVar<NoSchedPred, [C1UWrite_0c]>]>;
+
+def C1UWrite_2c_1M_Streaming : SchedWriteVariant<[
+ SchedVar<SMESchedPred, [C1UWrite_2c_1M]>,
+ SchedVar<NoSchedPred, [C1UWrite_0c]>]>;
+
+def C1UWrite_3c_1M_Streaming : SchedWriteVariant<[
+ SchedVar<SMESchedPred, [C1UWrite_3c_1M]>,
+ SchedVar<NoSchedPred, [C1UWrite_0c]>]>;
+
+def C1UWrite_2c_2M_Streaming : SchedWriteVariant<[
+ SchedVar<SMESchedPred, [C1UWrite_2c_2M]>,
+ SchedVar<NoSchedPred, [C1UWrite_0c]>]>;
+
+def C1UWrite_2c_1V_StreamingCME : C1USMEStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_2c_1V>;
+def C1UWrite_3c_1V01_StreamingCME : C1USMEStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_3c_1V01>;
+def C1UWrite_4c_1V_StreamingCME : C1USMEStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWrite_4c_1V>;
+def C1UWrite_2c_1M_StreamingCME : C1USMEStreamingSchedWrite<C1UWrite_0c_1M_1C_2X, C1UWrite_2c_1M>;
+def C1UWrite_2c_2M_StreamingCME : C1USMEStreamingSchedWrite<C1UWrite_0c_1M_1C_2X, C1UWrite_2c_2M>;
+
// Miscellaneous
// -----------------------------------------------------------------------------
@@ -933,37 +1132,37 @@ def : InstRW<[C1UWrite_1c_1SA_1D], (instrs STGi, ST2Gi, STZGi,
// FP min/max
// FP negate
// FP select
-def : SchedAlias<WriteF, C1UWrite_2c_1V>;
+def : SchedAlias<WriteF, C1UWrite_2c_1V_CME>;
// FP compare
-def : SchedAlias<WriteFCmp, C1UWrite_2c_1V01>;
+def : SchedAlias<WriteFCmp, C1UWrite_2c_1V01_CME>;
// FP divide
-def : SchedAlias<WriteFDiv, C1UWrite_5c_1V1>;
+def : SchedAlias<WriteFDiv, C1UWrite_5c_1V1_CME>;
// FP divide, H-form
-def : InstRW<[C1UWrite_5c_1V1], (instrs FDIVHrr)>;
+def : InstRW<[C1UWrite_5c_1V1_CME], (instrs FDIVHrr)>;
// FP divide, S-form
-def : InstRW<[C1UWrite_8c_1V1], (instrs FDIVSrr)>;
+def : InstRW<[C1UWrite_8c_1V1_CME], (instrs FDIVSrr)>;
// FP divide, D-form
-def : InstRW<[C1UWrite_12c_1V1], (instrs FDIVDrr)>;
+def : InstRW<[C1UWrite_12c_1V1_CME], (instrs FDIVDrr)>;
// FP square root, H-form
-def : InstRW<[C1UWrite_5c_1V1], (instrs FSQRTHr)>;
+def : InstRW<[C1UWrite_5c_1V1_CME], (instrs FSQRTHr)>;
// FP square root, S-form
-def : InstRW<[C1UWrite_8c_1V1], (instrs FSQRTSr)>;
+def : InstRW<[C1UWrite_8c_1V1_CME], (instrs FSQRTSr)>;
// FP square root, D-form
-def : InstRW<[C1UWrite_12c_1V1], (instrs FSQRTDr)>;
+def : InstRW<[C1UWrite_12c_1V1_CME], (instrs FSQRTDr)>;
// FP multiply
def : WriteRes<WriteFMul, [C1UUnitV]> { let Latency = 3; }
// FP multiply accumulate
-def : InstRW<[C1UWr_FMA, ReadDefault, ReadDefault, C1URd_FMA],
+def : InstRW<[C1UWr_FMA_CME, ReadDefault, ReadDefault, C1URd_FMA],
(instregex "^FN?M(ADD|SUB)[HSD]rrr$")>;
// FP round to integral
-def : InstRW<[C1UWrite_2c_1V0134], (instregex "^FRINT[AIMNPXZ][HSD]r$",
+def : InstRW<[C1UWrite_2c_1V0134_CME], (instregex "^FRINT[AIMNPXZ][HSD]r$",
"^FRINT(32|64)[XZ][SD]r$")>;
@@ -971,49 +1170,49 @@ def : InstRW<[C1UWrite_2c_1V0134], (instregex "^FRINT[AIMNPXZ][HSD]r$",
// -----------------------------------------------------------------------------
// FP convert, from gen to vec reg
-def : InstRW<[C1UWrite_3c_1M0], (instregex "^[SU]CVTF[SU][WX][HSD]ri$")>;
+def : InstRW<[C1UWrite_3c_1M0_CME], (instregex "^[SU]CVTF[SU][WX][HSD]ri$")>;
// FP convert, from vec to gen reg
-def : InstRW<[C1UWrite_3c_1V01],
+def : InstRW<[C1UWrite_3c_1V01_CME],
(instregex "^FCVT[AMNPZ][SU][SU][WX][HSD]ri?$")>;
// FP convert, Javascript from vec to gen reg
-def : SchedAlias<WriteFCvt, C1UWrite_3c_1V01>;
+def : SchedAlias<WriteFCvt, C1UWrite_3c_1V01_CME>;
// FP convert, from vec to...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/194850
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