[llvm] [AArch64][ISel] Prefer SVE over NEON for CTLZ (PR #194839)
Harry Ramsey via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 29 05:01:43 PDT 2026
https://github.com/Harry-Ramsey updated https://github.com/llvm/llvm-project/pull/194839
>From f1789db01ffa26b22dd62a0614d27ee2a6ef926e Mon Sep 17 00:00:00 2001
From: Harry Ramsey <harry.ramsey at arm.com>
Date: Tue, 28 Apr 2026 11:45:10 +0000
Subject: [PATCH] [AArch64][ISel] Prefer SVE over NEON for CTLZ
This commit enables SVE instructions for i64 data types that are
unsupported on NEON but supported on SVE.
---
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index b23bbd7234177..a2f9845fa5214 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1931,9 +1931,11 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::MULHU, VT, Custom);
}
- // NEON doesn't support 64-bit vector integer muls, but SVE does.
+ // NEON doesn't support 64-bit vector integers, but SVE does.
setOperationAction(ISD::MUL, MVT::v1i64, Custom);
setOperationAction(ISD::MUL, MVT::v2i64, Custom);
+ setOperationAction(ISD::CTLZ, MVT::v1i64, Custom);
+ setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
// With SVE2 we can try lowering these to pairwise operations (e.g. smaxp).
if (Subtarget->hasSVE2() || Subtarget->isStreamingSVEAvailable()) {
@@ -1970,8 +1972,6 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
// These operations are not supported on NEON but SVE can do them.
setOperationAction(ISD::BITREVERSE, MVT::v1i64, Custom);
- setOperationAction(ISD::CTLZ, MVT::v1i64, Custom);
- setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
setOperationAction(ISD::SMAX, MVT::v1i64, Custom);
setOperationAction(ISD::SMAX, MVT::v2i64, Custom);
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