[llvm] [WebAssembly][GlobalISel] Remove unecessary `-verify-machineinstrs` from tests (NFC) (PR #194799)

via llvm-commits llvm-commits at lists.llvm.org
Wed Apr 29 00:25:34 PDT 2026 

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-webassembly

Author: Demetrius Kanios (QuantumSegfault)

<details>
<summary>Changes</summary>

Removes all uses of `-verify-machineinstrs` from the Wasm GISel tests.

This only impacts `*.ll` in practice, as `-verify-machineinstrs` appears to be implicitly enabled when processing `.mir` files.

---
Full diff: https://github.com/llvm/llvm-project/pull/194799.diff


17 Files Affected:

- (modified) llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.mir (+1-1) 
- (modified) llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctlz.mir (+1-1) 
- (modified) llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctpop.mir (+1-1) 
- (modified) llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/cttz.mir (+1-1) 
- (modified) llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshl.mir (+1-1) 
- (modified) llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshr.mir (+1-1) 
- (modified) llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/implicit_def.mir (+1-1) 
- (modified) llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.mir (+1-1) 
- (modified) llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotl.mir (+1-1) 
- (modified) llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotr.mir (+1-1) 
- (modified) llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.mir (+1-1) 
- (modified) llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-simd.ll (+3-3) 
- (modified) llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-swiftcc.ll (+2-2) 
- (modified) llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args.ll (+2-2) 
- (modified) llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-aggregates.ll (+4-4) 
- (modified) llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-basics.ll (+2-2) 
- (modified) llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-simd.ll (+2-2) 


``````````diff
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.mir
index d9306410d3fee..c81eba50ead57 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
 
 ---
 name: ashr_i32_i8
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctlz.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctlz.mir
index 0817eb8f77d40..e8bdb5cb911c2 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctlz.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctlz.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
 
 ---
 name: ctlz_i32_i8
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctpop.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctpop.mir
index 77c7735a8fca4..97c9ffb90a7cb 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctpop.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctpop.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
 
 ---
 name: ctpop_i32_i8
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/cttz.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/cttz.mir
index 5fad67e3873d0..465b4a051cf73 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/cttz.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/cttz.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
 
 ---
 name: cttz_i32_i8
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshl.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshl.mir
index 28866a87fe3cc..d7e4daef5dc61 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshl.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshl.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
 
 ---
 name: fshl_i32_i8
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshr.mir
index 4e893e247b812..c95466a33e311 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshr.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshr.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
 
 ---
 name: fshr_i32_i8
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/implicit_def.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/implicit_def.mir
index cabb6584aad83..38d464c113123 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/implicit_def.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/implicit_def.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
 
 ---
 name:            implicit_def_i8
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.mir
index 4164438b39662..53805d9fae2cc 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
 
 ---
 name: lshr_i32_i8
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotl.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotl.mir
index 4806838fb6bdb..f977a269c8a34 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotl.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotl.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
 
 
 ---
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotr.mir
index 5c47bf654c372..12fd666d7128a 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotr.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotr.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
 
 
 ---
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.mir
index 756bf4769dea7..296be9adeb440 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
 
 ---
 name: shl_i32_i8
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-simd.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-simd.ll
index 772558ebfe111..6c4675f79087d 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-simd.ll
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-simd.ll
@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=wasm32 -mattr=-simd128 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck %s -check-prefixes=NO-SIMD
-; RUN: llc -mtriple=wasm32 -mattr=+simd128,-fp16 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck %s -check-prefixes=SIMD,SIMD-NO-F16
-; RUN: llc -mtriple=wasm32 -mattr=+simd128,+fp16 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck %s -check-prefixes=SIMD,SIMD-F16
+; RUN: llc -mtriple=wasm32 -mattr=-simd128 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=NO-SIMD
+; RUN: llc -mtriple=wasm32 -mattr=+simd128,-fp16 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=SIMD,SIMD-NO-F16
+; RUN: llc -mtriple=wasm32 -mattr=+simd128,+fp16 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=SIMD,SIMD-F16
 
 define void @test_v16i8_arg(<16 x i8> %arg) {
   ; NO-SIMD-LABEL: name: test_v16i8_arg
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-swiftcc.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-swiftcc.ll
index a2d1f01508a96..8668b1d9539f8 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-swiftcc.ll
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args-swiftcc.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=wasm32 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,WASM32
-; RUN: llc -mtriple=wasm64 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,WASM64
+; RUN: llc -mtriple=wasm32 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=CHECK,WASM32
+; RUN: llc -mtriple=wasm64 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=CHECK,WASM64
 
 define swiftcc void @test_implicit_self_and_error(float %arg) {
 
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args.ll
index f694ca625205a..152a607b14d5a 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args.ll
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=wasm32 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,WASM32
-; RUN: llc -mtriple=wasm64 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,WASM64
+; RUN: llc -mtriple=wasm32 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=CHECK,WASM32
+; RUN: llc -mtriple=wasm64 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=CHECK,WASM64
 
 define void @test_i8_arg(i8 %arg) {
   ; CHECK-LABEL: name: test_i8_arg
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-aggregates.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-aggregates.ll
index 97c2512a93d85..115f322ceef96 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-aggregates.ll
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-aggregates.ll
@@ -1,8 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=wasm32 -mattr=-simd128 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck %s -check-prefixes=WASM32-NOMULTIVAL
-; RUN: llc -mtriple=wasm64 -mattr=-simd128 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck %s -check-prefixes=WASM64-NOMULTIVAL
-; RUN: llc -mtriple=wasm32 -mattr=-simd128,+multivalue -target-abi=experimental-mv -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck %s -check-prefixes=MULTIVAL,WASM32-MULTIVAL
-; RUN: llc -mtriple=wasm64 -mattr=-simd128,+multivalue -target-abi=experimental-mv -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck %s -check-prefixes=MULTIVAL,WASM64-MULTIVAL
+; RUN: llc -mtriple=wasm32 -mattr=-simd128 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=WASM32-NOMULTIVAL
+; RUN: llc -mtriple=wasm64 -mattr=-simd128 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=WASM64-NOMULTIVAL
+; RUN: llc -mtriple=wasm32 -mattr=-simd128,+multivalue -target-abi=experimental-mv -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=MULTIVAL,WASM32-MULTIVAL
+; RUN: llc -mtriple=wasm64 -mattr=-simd128,+multivalue -target-abi=experimental-mv -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=MULTIVAL,WASM64-MULTIVAL
 
 define i128 @test_ret_i128() {
   ; WASM32-NOMULTIVAL-LABEL: name: test_ret_i128
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-basics.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-basics.ll
index 35153b5cfbd2b..b076dfd2005c0 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-basics.ll
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-basics.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=wasm32 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,WASM32
-; RUN: llc -mtriple=wasm64 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,WASM64
+; RUN: llc -mtriple=wasm32 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=CHECK,WASM32
+; RUN: llc -mtriple=wasm64 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=CHECK,WASM64
 
 define void @test_ret_void() {
   ; CHECK-LABEL: name: test_ret_void
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-simd.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-simd.ll
index 898b28aa90295..950e92e86adeb 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-simd.ll
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/ret-simd.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=wasm32 -mattr=+simd128 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,NO-FP16
-; RUN: llc -mtriple=wasm32 -mattr=+fp16,+simd128 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,FP16
+; RUN: llc -mtriple=wasm32 -mattr=+simd128 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=CHECK,NO-FP16
+; RUN: llc -mtriple=wasm32 -mattr=+fp16,+simd128 -global-isel -stop-after=irtranslator < %s | FileCheck %s -check-prefixes=CHECK,FP16
 
 define <16 x i8> @test_ret_v16i8() {
   ; CHECK-LABEL: name: test_ret_v16i8

``````````

</details>


https://github.com/llvm/llvm-project/pull/194799

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