[llvm] [llvm][RISCV] Optimize fneg for fixed vectors (PR #194555)
Brandon Wu via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 28 23:31:43 PDT 2026
================
@@ -2060,10 +2060,23 @@ SDValue VectorLegalizer::ExpandFNEG(SDNode *Node) {
if (!TLI.isOperationLegalOrCustom(ISD::XOR, IntVT))
return SDValue();
- // FIXME: The FSUB check is here to force unrolling v1f64 vectors on AArch64.
- if (!TLI.isOperationLegalOrCustomOrPromote(ISD::FSUB, VT) &&
- !VT.isScalableVector())
- return SDValue();
+ // Heuristic check to determine whether vector should be expanded to integer
+ // operations or unrolled to scalar operations.
+ // 1. Scalable vector is never unrolled.
+ // 2. Fixed vector is unrolled if one of followings is true:
+ // a. Vector only has 1 element and target knows how to handle scalar
+ // FNEG (either legal or custom expand or promote).
+ // b. Vector has more than 1 element and target supports scalar
+ // FNEG natively and vector length <= 3 (2 AND + 1 OR).
----------------
4vtomat wrote:
oops, I forgot to change the operations here😅
https://github.com/llvm/llvm-project/pull/194555
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