[llvm] [llvm][RISCV] Optimize fabs for fixed vectors (PR #194554)

[Craig Topper via llvm-commits]

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@@ -2080,10 +2080,23 @@ SDValue VectorLegalizer::ExpandFABS(SDNode *Node) {
   if (!TLI.isOperationLegalOrCustom(ISD::AND, IntVT))
     return SDValue();
 
-  // FIXME: The FSUB check is here to force unrolling v1f64 vectors on AArch64.
-  if (!TLI.isOperationLegalOrCustomOrPromote(ISD::FSUB, VT) &&
-      !VT.isScalableVector())
-    return SDValue();
+  // Heuristic check to determine whether vector should be expanded to integer
+  // operations or unrolled to scalar operations.
+  // 1. Scalable vector is never unrolled.
+  // 2. Fixed vector is unrolled if one of followings is true:
+  //      a. Vector only has 1 element and target knows how to handle scalar
+  //         FABS(either legal or custom expand or promote).
+  //      b. Vector has more than 1 element and target supports scalar
+  //         FABS natively and vector length <= 3(2 AND + 1 OR).
+  if (VT.isFixedLengthVector()) {
+    EVT EltVT = VT.getVectorElementType();
+    if ((VT.getVectorNumElements() == 1 &&
+         TLI.isOperationLegalOrCustomOrPromote(ISD::FCOPYSIGN, EltVT)) ||
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topperc wrote:

FCOPYSIGN->FAB?

https://github.com/llvm/llvm-project/pull/194554