[llvm] [PowerPC] Fix assert which caused by PR 190606 (PR #194040)
zhijian lin via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 28 08:40:27 PDT 2026
https://github.com/diggerlin updated https://github.com/llvm/llvm-project/pull/194040
>From 44a5a4d914c0a64beaaba4f8594f7fabc470cbbe Mon Sep 17 00:00:00 2001
From: zhijian <zhijian at ca.ibm.com>
Date: Fri, 24 Apr 2026 19:14:57 +0000
Subject: [PATCH 1/3] add a pre-commit test case
---
llvm/test/CodeGen/PowerPC/test-issue-98598.ll | 47 +++++++++++++++++++
1 file changed, 47 insertions(+)
create mode 100644 llvm/test/CodeGen/PowerPC/test-issue-98598.ll
diff --git a/llvm/test/CodeGen/PowerPC/test-issue-98598.ll b/llvm/test/CodeGen/PowerPC/test-issue-98598.ll
new file mode 100644
index 0000000000000..c07f0d4e128f7
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/test-issue-98598.ll
@@ -0,0 +1,47 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-32BIT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix CHECK-64BIT
+
+define dso_local zeroext range(i8 -1, 1) i8 @f(i8 noundef zeroext %x) {
+; CHECK-32BIT-LABEL: f:
+; CHECK-32BIT: # %bb.0: # %entry
+; CHECK-32BIT-NEXT: cmpwi r3, 0
+; CHECK-32BIT-NEXT: li r3, 0
+; CHECK-32BIT-NEXT: li r4, 255
+; CHECK-32BIT-NEXT: iseleq r3, r4, r3
+; CHECK-32BIT-NEXT: blr
+;
+; CHECK-64BIT-LABEL: f:
+; CHECK-64BIT: # %bb.0: # %entry
+; CHECK-64BIT-NEXT: cmpwi r3, 0
+; CHECK-64BIT-NEXT: li r3, 0
+; CHECK-64BIT-NEXT: li r4, 255
+; CHECK-64BIT-NEXT: iseleq r3, r4, r3
+; CHECK-64BIT-NEXT: blr
+entry:
+ %cmp = icmp eq i8 %x, 0
+ %conv2 = sext i1 %cmp to i8
+ ret i8 %conv2
+}
+
+define i32 @compare2(i64 %conv1) {
+; CHECK-32BIT-LABEL: compare2:
+; CHECK-32BIT: # %bb.0: # %entry
+; CHECK-32BIT-NEXT: or. r3, r4, r3
+; CHECK-32BIT-NEXT: li r3, 0
+; CHECK-32BIT-NEXT: li r4, -1
+; CHECK-32BIT-NEXT: iseleq r3, r4, r3
+; CHECK-32BIT-NEXT: blr
+;
+; CHECK-64BIT-LABEL: compare2:
+; CHECK-64BIT: # %bb.0: # %entry
+; CHECK-64BIT-NEXT: addic r3, r3, -1
+; CHECK-64BIT-NEXT: subfe r3, r3, r3
+; CHECK-64BIT-NEXT: blr
+entry:
+ %tobool2.not = icmp eq i64 %conv1, 0
+ %cond = sext i1 %tobool2.not to i32
+ ret i32 %cond
+}
>From 0708236674acc5bd89eaab64512554a067ae3bd0 Mon Sep 17 00:00:00 2001
From: zhijian <zhijian at ca.ibm.com>
Date: Fri, 24 Apr 2026 20:11:14 +0000
Subject: [PATCH 2/3] fix assert which caused by the fix of issue# 98598
---
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 16 ++++++++------
llvm/test/CodeGen/PowerPC/test-issue-98598.ll | 21 ++++++++-----------
2 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 7c7032762c5c9..5c61f606af19c 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -15869,7 +15869,8 @@ SDValue PPCTargetLowering::combineSignExtendSetCC(SDNode *N,
if (Subtarget.isISA3_1())
return SDValue();
- if (N->getValueType(0) != MVT::i32 && N->getValueType(0) != MVT::i64)
+ EVT VT = N->getValueType(0);
+ if (VT != MVT::i32 && VT != MVT::i64)
return SDValue();
SDValue N0 = N->getOperand(0);
@@ -15886,20 +15887,23 @@ SDValue PPCTargetLowering::combineSignExtendSetCC(SDNode *N,
SDLoc dl(N);
SelectionDAG &DAG = DCI.DAG;
- EVT VT = N->getValueType(0);
SDValue X = isNullConstant(LHS) ? RHS : LHS;
EVT XVT = X.getValueType(); // The type of x in the setcc x, 0, eq.
+ if (!Subtarget.isPPC64() && XVT == MVT::i64)
+ return SDValue();
+
// On PPC64, i32 carry operations use the full 64-bit XER register,
// so we must use i64 operations to avoid incorrect results.
// Use i64 operations and truncate the result if needed.
EVT OpVT = VT;
- if (Subtarget.isPPC64() && VT == MVT::i32)
+ if (Subtarget.isPPC64()) {
OpVT = MVT::i64;
- // Zero-extend if input type differs from operation type.
- if (XVT != OpVT)
- X = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, X);
+ if (XVT != OpVT)
+ // Zero-extend if input type is not 64bits.
+ X = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, X);
+ }
// Generate: SUBFE(ADDC(X, -1)).
SDValue MinusOne = DAG.getAllOnesConstant(dl, OpVT);
diff --git a/llvm/test/CodeGen/PowerPC/test-issue-98598.ll b/llvm/test/CodeGen/PowerPC/test-issue-98598.ll
index c07f0d4e128f7..c50c2250d865d 100644
--- a/llvm/test/CodeGen/PowerPC/test-issue-98598.ll
+++ b/llvm/test/CodeGen/PowerPC/test-issue-98598.ll
@@ -7,18 +7,16 @@
define dso_local zeroext range(i8 -1, 1) i8 @f(i8 noundef zeroext %x) {
; CHECK-32BIT-LABEL: f:
; CHECK-32BIT: # %bb.0: # %entry
-; CHECK-32BIT-NEXT: cmpwi r3, 0
-; CHECK-32BIT-NEXT: li r3, 0
-; CHECK-32BIT-NEXT: li r4, 255
-; CHECK-32BIT-NEXT: iseleq r3, r4, r3
+; CHECK-32BIT-NEXT: addic r3, r3, -1
+; CHECK-32BIT-NEXT: subfe r3, r3, r3
+; CHECK-32BIT-NEXT: clrlwi r3, r3, 24
; CHECK-32BIT-NEXT: blr
;
; CHECK-64BIT-LABEL: f:
; CHECK-64BIT: # %bb.0: # %entry
-; CHECK-64BIT-NEXT: cmpwi r3, 0
-; CHECK-64BIT-NEXT: li r3, 0
-; CHECK-64BIT-NEXT: li r4, 255
-; CHECK-64BIT-NEXT: iseleq r3, r4, r3
+; CHECK-64BIT-NEXT: addic r3, r3, -1
+; CHECK-64BIT-NEXT: subfe r3, r3, r3
+; CHECK-64BIT-NEXT: clrldi r3, r3, 56
; CHECK-64BIT-NEXT: blr
entry:
%cmp = icmp eq i8 %x, 0
@@ -29,10 +27,9 @@ entry:
define i32 @compare2(i64 %conv1) {
; CHECK-32BIT-LABEL: compare2:
; CHECK-32BIT: # %bb.0: # %entry
-; CHECK-32BIT-NEXT: or. r3, r4, r3
-; CHECK-32BIT-NEXT: li r3, 0
-; CHECK-32BIT-NEXT: li r4, -1
-; CHECK-32BIT-NEXT: iseleq r3, r4, r3
+; CHECK-32BIT-NEXT: or r3, r4, r3
+; CHECK-32BIT-NEXT: addic r3, r3, -1
+; CHECK-32BIT-NEXT: subfe r3, r3, r3
; CHECK-32BIT-NEXT: blr
;
; CHECK-64BIT-LABEL: compare2:
>From 9877b4dd1b977fc1935c25867c8c6245cc973469 Mon Sep 17 00:00:00 2001
From: zhijian <zhijian at ca.ibm.com>
Date: Tue, 28 Apr 2026 15:53:58 +0000
Subject: [PATCH 3/3] address comment
---
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 5c61f606af19c..583481c9673f8 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -15890,7 +15890,7 @@ SDValue PPCTargetLowering::combineSignExtendSetCC(SDNode *N,
SDValue X = isNullConstant(LHS) ? RHS : LHS;
EVT XVT = X.getValueType(); // The type of x in the setcc x, 0, eq.
- if (!Subtarget.isPPC64() && XVT == MVT::i64)
+ if (XVT == MVT::i64 && !Subtarget.isPPC64())
return SDValue();
// On PPC64, i32 carry operations use the full 64-bit XER register,
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